# EE573 Introduction to VLSI Systems -Final Exam- 1.(30) Design a 4-bit Manchester carry chain using Multiple-output footer-less Domino logic for use in 16-bit carry-skip adder.(10) Draw a block diagram of the 16-bit carry- skip adder consisting of four 4-bit blocks(10) and show how 13+26=39 is performed(10). No students, alas, have included a bypass switch in the Manchester carry Chain enabled by P=P P P Pwhich is a key in the carry skip adder. I admit the example was too simple.

Electronique - Appareils

27 nov. 2013 (il y a 5 années et 1 mois)

156 vue(s)

EE573

Introduction to VLSI Systems
-
F
i
nal Exam
-

1.

(30)
Design a 4
-
bit
Manchester

carry chain using Multiple
-
output footer
-
less Domino
logic for use in 16
-
bit carry
-
(10)

Draw a block diagram of the 16
-
bit carry
-

consisting of four 4
-
bit blocks(10)
and show how 13+26=39 is performed
(10)
.

No students, alas, have included a bypass switch in the
Manchester

carry Chain enabled
by P=P
1

P
2

P
3

P
4, ,
which is a key in th
simple.

2.

D
esign a A+B=K addressed adder. Explain how it can be faster than A+B evaluation using
(
10
)

First key concept in this design is to compare the required carry in and the actually
generated carry
out from the lower bit position. Second key is to actually generated carry
out from each bit position without carry propagation. Please ry to understand equ 10.41
in the textbook.

Interesting case is when A EXOR B=1, and K=0. For A+B=K to hold in
this case
, carry in to this bit must be 1, which makes carry out from this bit equal to 1.
T
herefore carry is produced in this case.

3.

What is the purpose of boundary scan?
(10)

Boundary scan is NOT the same as full scan, partial scan or parallel scan, which are
all
techniques of utilizing the storage cells such as flipflops or latches already built for testing
the combinational logic within the chip. Boundary scan is mainly for testing the
interconnection between chips on the board. Each chip must be tested throu
mentioned techniques such as scan chain. How about faulty interconnection among chips
on the PCB? Boundary scan is for that, although it can still be used for testing the
functions within each chip after on
-
board attachment. You need to think ho
w this is
possible. JTAG is a standard for reducing costs for this board
-
level interconnection testing.

This is especially important as nail bed testing is not possible with surface mount
attached IC

s.

4.

Explain why IDDQ testing has become less useful w
ith

recent CMOS technology? (10)

IDDQ testing is for testing bridging faults, i.e., undesirable

short

between two points
such that a MOSFET is bypassed. Normally, in static CMOS, for any combination of input
patterns, there should be no static current. Howe
ver, if there

s some short

shorting

a
MOSFET
, some DC current called IDDQ (I
DD

quiescent) would be observed
even though a
test vector which tries to turn off that specific MOSFET is applied.

This is
the

IDDQ
testing. Now, with higher leakage current flow
current becomes less and less observable.

5

W
hy
is
bit line folding necessary
?
(
5
)

a. speed b. power
c. process variation

6

Why is bit line twisting necessary?(5)
a. noise

b. speed c. process variation

7

Explain the role of
the dummy circuit in the dynamic PLA circuit below.
(
1
0
)

If you mentioned self
-
timed, it is good. If you further mentioned this circuit is process
variation
-
tolerant, it is impeccable, wow, truly excellent.

8.
Explain

how CLB(Configurable Logic B
lock) and routing cells in FPGA are programmed to
achieve the desired logic function, and routing, respectively. (
20)

9.
Comment on how you have mostly benefitted from this course.(
10
)

Also comment in
what respect this course needs to be modified.(
10
)

I also thank you all for your sincere participation throughout the semester. It, definitely, was
not an easy task. Sorry for the poor quality of the recorded lectures, which s
o
me students
mentioned. Sorry for not sharing the Q&A with other students. I t
hought they were being
shared in the web site.

Again, that is due to my carelessness.

I am pleased to learn that
quite
many of
you enjoyed

co
-
emulation project. Thank you for your participation and support!