# Solution

CS423 Homework 1
-

Solution

Processes and Threads

1.

Processes may be in one of three states: Running, Ready, or Blocked. However, not all
sequences of these three states are possible. In the list below, identify the sequence of states that
is possible.

(a)
Blocked

Ready

Run
ning

Blocked

(b)

Running

Ready

Blocked

Running

(c)
Running

Ready

Blocked

Ready

(d)

Blocked

Running

Ready

Blocked

(e)

None of the above

Solution: (a)

Blocked can only be followed by Ready, and Ready can only be followed by Running.

Thus, any sequence in which
Blocked is followed immediately by Running is wrong, and so is any sequence where Ready is followed
immediately by Blocked.

2
.

A producer P and consumer C communicate by means of three semaphores and a buffer that
has a capa
city of 10.

Semaphore M enforces mutual exclusion; it is in
i
tially 1, is decremented by whichever
process wants to enter its critical region (the code that adds or removes items from the
buffer), and incremented back to 1 after leaving the critical region
.

Semaphore F counts the number of full slots in the buffer. It is initially 0, is decremented
by C before entering its critical region, and incremented by P after leaving its critical
region.

Semaphore E counts the number of empty slots in the buffer. I
t is initially 10, is
decremented by P before entering its critical region, and incremented by C after leaving
its critical region.

Before entering a critical region, a process first tries to decrement E or F, and then tries to
decrement M. On leaving a c
ritical region, a process first raises M and then E or F. Under these
assumptions, what are the possible combinations of values of E, F, and M that can exist?
Identify, in the list below, the combination that
cannot

exist.

(a)

M = 0, E = 5, F = 3

(b)

M = 0, E = 8, F = 0

(c)

M = 0, E = 7, F = 1

(d)

M = 1, E = 7, F = 0

(e)
M =
1
, E =
9
, F = 1

CS423 Homework 1
-

Solution

Solution: (d)

When neither P nor C is in its critical region or attempting to enter its critical region, F+E=10 and M=1. If one tries
to enter its critical region, it decrements E or F, in which case E+F=9, while M is still 1. It is possible that, at the
same time, the
other process also tries to enter its critical region, and decrements the other of E and F, resulting in
E+F=8 with M=1. Then, one of these processes must set M=0 and enter its critical region. On exiting the critical
region, M becomes 1 again, while E and

F are unchanged; their sum is either 8 or 9. However, the process exiting
the critical region will increment one of E or F, resulting in M=1 and E+F=9 or 10. If E+F=9, the other process may
set M=0 and enter its critical region. If E+F=10, then M will sta
y 1 until P or C decrements E or F.

The only other constraints are that neither E, F, nor M can be negative.

The conclusion is that if M=0, then E+F = 8 or 9, and if M=1, then E+F = 8, 9 or 10. Since executing P increments F
and decrements E, while execu
ting C does the opposite, we conclude that any of these combinations of M, E, and F
described above are possible, subject only to the constraints of no negative values.

Paging:

3
.
Consider a memory
-
management system based on paging.

Let the total si
ze of the physical
memory be 2GB
,

laid out over pages of size 4KB.

Let the logical address space of each process
be limited to 128MB.

Based on the information above, determine the physical address layout in the system (i.e., the
total number of bits in a

physical address, the number of bits specifying the physical frame
number, and the number of bits specifying the page displacement). How many physical frames
are there in the system?

Determine the logical address layout in a similar way. How many pages a
re there in the logical
address space of each process?

Finally, compute the number of entries in each page table and the size of each page table entry.

Based on the computation above, identify the TRUE statement from among those below.

(a)

1 Each page
table entry has 13 bits (including 1 valid/invalid bit).

(b)

Each logical address has a total of 27 bits, with 17 bits for the page number and 10 bits for
displacement.

(c)
Each logical address

has a total of 27 bits, with 13 bits for the page number and

14 bits for
displacement.

(d)

Each physical address has a total of 31 bits, with 19 bits for the page frame number and 12
bits for the displacement.

(e)

There are a total of 32,768 frames in the system.

CS423 Homework 1
-

Solution

Solution:

(
d
)

The total physical memory size is 2
GB, so each physical address requires 31 bits. The page size is 4KB, requiring 12
bits of displacement in each address. Thus, the physical address layout is 31 bits, including 19 bits for the page
frame number and 12 bits of displacement. Note that there a
re 512K page frames in the system.

The logical address space for each process is 128MB, requiring a total of 27 bits. The page size is the same as that
of the physical pages (i.e., 4KB). Therefore the logical address layout is 27 bits, with 15 bits for pa
ge number and 12
bits for displacement. Note that there are 32K pages in the address space of each process.

Each page table should contain as many entries as there are logical pages in the address space of each process.
Therefore, there are 32K entries in

each page table. Each entry in a page table contains a valid/invalid bit and a
page frame number. Since the page frame number has 19 bits, the length of each entry in the page table is 20 bits.

Please refer to Section 3.3.1 (p. 189) for a discussion of P
aging.

4
.

C
onsider a system with 16MB of physical memory laid out over pages of 8KB size. Let P1 be
a process in this system with the following page table:

Valid Bit

Frame Number

1

205

1

109

1

304

0

0

0

0

0

0

0

0

0

0

Let P2 be another proce
ss in this system with the following page table:

Valid Bit

Frame Number

1

245

1

378

1

184

1

642

CS423 Homework 1
-

Solution

1

525

1

712

1

435

0

0

Consider the logical addresses 0x26ca and 0x54b9 of process P1. Note that the addresses are
represented in hexadecimal notation
(e.g., 0x26ca refers to 0010 0110 1100 1010). Also,
consider the logical addresses 0x56d8 and 0xd695 of process P2. For these four logical
addresses, determine the corresponding physical addresses. Note that the frame numbers in the
page tables are given i
n decimal notation.

In the following answer choices, let (A, L, P) denote that the logical address L of process A
translates to the physical address P. Identify the triple that denotes a correct address translation.

(a)
(P1, 0x26ca, 0x19a6ca)

(b)

(P1,

0x26ca, 0x26c930)

(c)
(P2, 0xd695, 0x367695)

(d)

(P1, 0x54b9 0xa814b9)

(e)

(P2, 0x56d8, 0x2f56d8)

Solution:

(
c
)

The page displacement is 13 bits because the page size is 8KB. The physical addresses and the logical address must
match in the displacemen
t section. That is, the last 13 bits of each physical address must match its corresponding
logical address.

The physical frame number has 11 bits because there are a total of 2K pages in the system (since, the total
memory size is 16 MB). For each of the
logical addresses, we can obtain the corresponding physical address by
finding the logical page number (the first three bits of the logical address), indexing the page table of the process
with the logical page number, determining the physical frame number

in the page table entry, and using the
physical frame number obtained to generate the first 11 bits of the physical address.

For the logical address 0x26ca of process P1, we can see the displacement (the last 13 bits are) 0 0110 1100 1010,
and the logica
l page number (the first three bits) is 001. The corresponding page frame number in the page table
of P1 is 109. Accordingly, the physical address is 0x0da6ca.

Similarly, we can determine that the logical address 0x54b9 of process P1 translates to the phy
sical address
0x2614b9, the logical address 0x56d8 of process P2 translates to the physical address 0x1716d8, and the logical
address 0xd695 of process P2 translates to the physical address 0x367695.

Please refer to Section 3.3 (p. 188) for a discussion o
f address translation using a page table.

CS423 Homework 1
-

Solution

5
.

C
onsider three memory
-
management systems S1, S2 and S3 that use simple paging for
memory management and employ associative registers to speed up page lookups.

Let S1 have a set of associative registers, with

lookup performance of 120ns and a hit rate of
60%. Let S2 have a larger set of slower associative registers with lookup performance of 180ns
and a hit rate of 80%. Let S3 have a set of associative registers with lookup performance of
120ns and a hit rate
of 80%. Let the main
-
memory page
-
table lookup take 600ns in all the three
systems.

In terms of the lookup algorithm, let S3 employ the serial algorithm where the lookup is first
conducted in the associative registers and only after the lookup miss in the
associative registers,
the main
-
memory lookup is initiatied. In contrast, let S1 and S2 employ the parallel algorithm
where the lookup is conducted in parallel in both the associative registers and the main
-
memory
page table.

Determine the page
-
lookup per
formance for the three schemes. In particular, compute the
average time for page lookup as well as the lookup time in the case of a page hit and a page miss.
Based on this computation, identify the FALSE statement among the following.

(a)
S2 has better
overall page
-
lookup performance than S3

(b)

Page
-
lookup hits take longer in S2 than in S3

(c)
Page
-
lookup misses take longer in S3 than in S2

(d)

Page
-
lookup misses take the same time in S1 and S2

(e)

S2 has better overall page
-
lookup performance than
S1

Solution:

(
a
)

In the case of S1, it takes 120ns for a page lookup hit in the associative registers and 600ns if there is a page miss.
Thus, the overall performance (average page
-
lookup time) of S1 is 0.6 * 120 + 0.4 * 600 = 312ns.

In the case of S2, i
t takes 180ns for a page lookup hit in the associative registers and 600ns if there is a page miss.
Thus, the overall performance (average page
-
lookup time) of S2 is 0.8 * 180 + 0.2 * 600 = 264ns.

In the case of S3, it takes 120ns for a page lookup hit in

the associative registers and 720ns if there is a page miss
(because it uses a serial lookup algorithm). Thus, the overall performance (average page
-
lookup time) of S3 is 0.8 *
120 + 0.2 * 720 = 240ns.

Therefore, S3 has the best overall performance while

S1 has the worst overall performance.

Please refer to Section 3.3.3 (p. 194) for a discussion of paging performance.

CS423 Homework 1
-

Solution

6
.

Consider four system configurations involving demand paging.

In system S1, the main memory size is 1 GB with a cost of \$100. The

memory access time (i.e.,
when a page is accessed without a page fault) is 0.1 ms. The disk drive in this system
configuration costs \$75 and the page fault service time (i.e., the average time to identify a page
to replace, write it out if needed, and bri
ng in the new page from disk) is 2 ms.

In system S2, the main memory size is 0.5 GB and its cost is \$75. The memory access time is
0.075 ms. The disk drive costs \$125 and the page fault service time is 1.5 ms.

In system S3, the main memory size is 2 GB a
nd its cost is \$125. The memory access time is 0.1
ms. The disk drive costs \$125 and the page fault service time is 1.5 ms.

In system S4, the main memory size is 2 GB and its cost is \$100. The memory access time is 0.2
ms. The disk drive costs \$125 and th
e page fault service time is 1 ms.

Let the page fault rate in the four systems be 10%, 15%, 7.5% and 7.5% respectively.

Determine the performance, in terms of the effective memory access time (i.e., the time it takes
on average to access a page in memory
), for the four system configurations S1, S2, S3, S4.
Identify the TRUE statement from the following choices regarding the price
-
performance ratios
of the four systems (note that in this context, system A will have a better price
-
performance ratio
if the p
roduct of its total cost of main memory as well as disk drive and its effective memory
access time is smaller than the corresponding value for system B)?

(a)
S3 has the best price
-
performance ratio.

(b)

S1 has the best price
-
performance ratio.

(c)
S2 h
as the worst price
-
performance ratio.

(d)

S4 has better price
-
performance ratio than S3.

(e)

S2 has better price
-
performance ratio than S1.

Solution:

(
b
)

In order to compare the system configuration with respect to their price
-
performance ratios, we nee
d to compute
the effective memory access time for each one.

The effective memory access time in S1 is 0.90 * 0.1 + 0.10 * 2 = 0.29 ms. The effective memory access time in S2 is
0.85 * 0.075 + 0.15 * 1.5 = 0.28875 ms. The effective memory access time in S3

is 0.925 * 0.1 + 0.075 * 1.5 = 0.205
ms. The effective memory access time in S4 is 0.925 * 0.2 + 0.075 * 1 = 0.26 ms.

The price performance ratios for the various systems can now be obtained by multiplying their effective memory
access times and the tota
l cost of the system configuration. These values for the four systems are: 50.75, 57.75,
51.25 and 58.5.

Therefore, the system configuration with the best price
-
performance ratio is S1, followed by S3, S2 and S4.

Please refer to Section 3.3 (p. 188) for
a discussion of virtual memory through Paging.

CS423 Homework 1
-

Solution

Page
-
Replacement

7
.

Consider four processes P1, P2, P3 and P4 in a demand
-
paging system in which process P1 is
allocated three frames, process P2 is allocated four frames, P3 is allocated five frames and
p
rocess P4 is allocated six frames. Let the Least Recently Used (LRU) page
-
replacement scheme
be employed in the system.

Let P1 have the following sequence of page references: 1, 3, 5, 1, 5, 1, 3, 2, 3, 1, 2, 7, 4, 2, 4, 2,
5, 2, 4, 6.

Let P2 have the fol
lowing sequence of page references: 1, 5, 3, 6, 5, 1, 3, 2, 6, 1, 2, 5, 4, 2, 4, 2,
1, 7.

Let P3 have the following sequence of page references: 1, 5, 1, 3, 5, 6, 4, 2, 7, 6, 2, 4, 6, 4, 1, 6,
1, 7, 1, 6.

Let P4 have the following sequence of page refere
nces: 1, 2, 4, 1, 4, 6, 5, 1, 7, 6, 1, 3, 1, 2, 3, 4,
5, 2.

Determine the total number of page faults for each of the above four processes. Which of the
following is a TRUE statement about the page faults of these processes?

(a)
P1 and P2 have the same

number of page faults.

(b)

P2 and P3 have the same number of page faults.

(c)
P3 has more page faults than P4.

(d)

P1 has more page faults than P3.

(e)

P2 has more page faults than P1
.

Solution:

(
e
)

For each process, we can identify the references th
at cause page faults. For P1, the reference sequence is 1, 3, 5, 1,
5, 1, 3, 2, 3, 1, 2, 7, 4, 2, 4, 2, 5, 2, 4, 6. Given that P1 is allocated three frames, the references with the * cause
page faults: 1*, 3*, 5*, 1, 5, 1, 3, 2*, 3, 1, 2, 7*, 4*, 2, 4, 2,
5*, 2, 4, 6*. Thus, the number of page faults for P1 is 8.

For P2, the reference sequence is 1, 5, 3, 6, 5, 1, 3, 2, 6, 1, 2, 5, 4, 2, 4, 2, 1, 7. Given that P2 is allocated four
frames, the references with the * cause page faults: 1*, 5*, 3*, 6*, 5, 1, 3
, 2*, 6*, 1, 2, 5*, 4*, 2, 4, 2, 1, 7*. Thus,
the number of page faults for P2 is 9
.

For P3, the reference sequence is 1, 5, 1, 3, 5, 6, 4, 2, 7, 6, 2, 4, 6, 4, 1, 6, 1, 7, 1, 6. Given that P3 is allocated five

frames, the references with the * cause page
faults: 1*, 5*, 1, 3*, 5, 6*, 4*, 2*, 7*, 6, 2, 4, 6, 4, 1*, 6, 1, 7, 1, 6.
Thus, the number of page faults for P3 is 8.

CS423 Homework 1
-

Solution

For P4, the reference sequence is 1, 2, 4, 1, 4, 6, 5, 1, 7, 6, 1, 3, 1, 2, 3, 4, 5, 2. Given that P4 is allocated six frames
,
the ref
erences with the * cause page faults: 1*, 2*, 4*, 1, 4, 6*, 5*, 1, 7*, 6, 1, 3*, 1, 2*, 3, 4*, 5*, 2. Thus, the
number of page faults for P4 is 10.

Therefore, the numbers of page faults for the four processes are 8, 9, 8 and 10 respectively.

Please refer

to Section 3.4.6 (p. 206) for a discussion of the LRU page
-
replacement algorithm.

8
.

Consider a demand
-
paging system in which a process is allocated three frames. Let the Least
Recently Used (LRU) page
-
replacement algorithm be used in the system. Let t
he sequence of
page references for the process be as follows: 1, 3, 4, 1, 5, 2, 3, 1, 6, 2, 4, 3, 2, 4, 1, 6, 5, 6, 1, 5,
3, 1, 2, 4, 1, 2.

When processing each of the above page references, determine the set of pages resident in
memory. Now, identify a t
riple from the following that represents a set of pages of the process
that do NOT reside together in memory at the same time?

(a)
{1, 4, 5}

(b)

{1, 2, 3}

(c)
{2, 3, 6}

(d)

{1, 2, 6}

(e)

{2, 3, 5}

Solution:

(
c
)

In order to figure out if a given set

of three pages reside together in memory, we just have to see if those three
pages appear next to each other in the sequence of page references. For instance, {1, 4, 5} is a set of pages that
reside together in memory because they appear next to each othe
r from the third to the fifth reference in the
sequence, whereas {2, 3, 6} is a set of pages that do not reside together in memory because those three pages do
not appear next to each other in the page reference sequence.

In this manner, we can identify t
he following sets of pages as NOT residing together in memory at a time:

{2, 3, 6}

{2, 4, 5}

{2, 5, 6}

{3, 4, 5}

{3, 4, 6}

{3, 5, 6}

{4, 5, 6}

All other sets of three pages of the process reside together in memory at some point in time.

Please ref
er to Section 3.4.6 (p. 206) for a discussion of the LRU page
-
replacement algorithm.

CS423 Homework 1
-

Solution

9
.

In a demand
-
paging system, let the memory frames be allocated in a global manner across all
processes, using a global page
-
replacement scheme based on the First
-
In F
irst
-
Out (FIFO)
criterion. That is, whenever a process references a page that is not in memory, if there is a free
frame available in the system, it is allocated to the process and its page is loaded into that frame.
If there is no free frame available in
the system, a page to be replaced is selected across all
processes using the FIFO criterion, the page is swapped out as needed, and the new page is
brought into the newly freed memory frame.

Consider the following sequence of references for three processe
s, P1, P2 and P3:

1.

page 1 of P1

2.

page 3 of P1

3.

page 3 of P3

4.

page 1 of P2

5.

page 3 of P2

6.

page 2 of P3

7.

page 1 of P1

8.

page 2 of P1

9.

page 1 of P3

10.

page 3 of P3

11.

page 2 of P2

12.

page 1 of P3

13.

page 1 of P2

14.

page 3 of P2

15.

page 3 of P1

16.

page 1 of P2

17.

page 3 of P3

18.

page 2 of P2

Let the system start with six available frames globally. For each page reference in the sequence
above, determine if the reference causes a page fault or not. Now, identify the page reference
from the following that does NOT cause a page fau
lt?

(a)

Reference #7 to page 1 of P1

(b)

Reference #8 to page 2 of P1

(c)

Reference #9 to page 1 of P3

(d)

Reference #11 to page 2 of P2

(e)

Reference #15 to page 3 of P1

Solution:

(
a
)

The problem can be simplified by considering the list of refere
nces as if they are all issued by a single process, just
different pages (i.e., we can consider page 1 of two different processes as two different pages). Then, we can apply
CS423 Homework 1
-

Solution

the FIFO page
-
replacement scheme to the problem as if there is a sequence of 18 pa
ge references by a single
process that is allocated six frames.

Based on the above simplification, the references that cause page faults are 1, 2, 3, 4, 5, 6, 8, 9, 11, 15, 16 and 17.
The other six references, namely 7, 10, 12, 13, 14 and 18, do not cause

page faults.

Please refer to Section 3.4.3 (p. 204) for a discussion of the FIFO page
-
replacement algorithm.

10
.

Consider a demand
-
paging system employing the Least Recently Used (LRU) policy to
select pages for replacement. Let the sequence of page r
eferences of a process be as follows: 4, 1,
5, 3, 5, 1, 5, 4, 5, 1, 7, 8, 5, 7, 5, 8, 5, 7, 5, 8, 7, 9, 8, 5, 9, 8, 7, 5, 1, 4.

In order to find the number of page faults for a given reference string in the LRU scheme, we can
compute the
distance string

f
or the given reference string as follows. Imagine a stack of page
references maintained when processing the reference string. We define the ith element in the
distance string to be the distance of the page from the top of the stack when the ith page
refere
nce is issued. Note that the top of the stack is considered to be at a distance of 1. For
instance, the 6th element of the reference string is page reference 1, and the corresponding 6th
element of the distance string is 3, because page 1 is the third page

from the top in the stack
when it appears as the 6th element of the reference string.

Note that the
i
th element of the distance string is INF (representing infinity), whenever the
i
th
element of the reference string is a page that is referenced for the f
irst time. Also remember that
a page is moved to the top of the stack when it is referenced (or pushed onto the top of the stack
if it has not been referenced previously).

Once the distance string is computed, we can determine the number of page faults fo
r a given
allocation of page frames by counting the number of elements of the distance string that are
greater than the number of page frames allocated.

For the reference string given above, compute the distance string and accordingly determine the
number

of page faults when the process is allocated 2, 3, 4, 5 and 6 frames. Based on this
computation, identify the TRUE statement from the following.

(a)
There will be 10 fewer page faults if the number of frames allocated is increased from 2 to 4.

(b)

The
re will be 16 more page faults if the number of frames allocated is decreased from 4 to 2.

(c)
There will be 10 fewer page faults if the number of frames allocated is increased from 2 to 3.

(d)

There will be 16 fewer page faults if the number of frames a
llocated is increased from 2 to 6.

(e)

There will be 4 fewer page faults if the number of frames allocated is increased from 3 to 4.

Solution:

(
c
)

CS423 Homework 1
-

Solution

The first four elements of the distance string are INF, because the first four elements of the reference st
ring refer
to pages that are not on the page stack. The fifth reference is for page 5, and that is at a distance of 2. So the fifth
entry of distance string is 2, and page 5 is moved to the top of the stack. Next reference is for page 1, and that is at
a d
istance of 3, thus making the 6th element of the distance string 3. Similarly, we can compute the remaining
entries of the distance string.

For the given reference string, the distance string is INF, INF, INF, INF, 2, 3, 2, 4, 2, 3, INF, INF, 4, 3, 2, 3,
2, 3, 2, 3, 3,
INF, 3, 4, 3, 3, 4, 4, 5, 6.

For an allocation of 2 page frames, there will be an estimated 24 page faults; for 3 page frames the number of page
faults is 14; for 4 page frames the number of page faults is 9; for 5 page frames the number of

page faults it 8 and
for 6 page frames the number of page faults is 7.

Page faults are discussed in Section 3.3.1 (p. 189), and the LRU algorithm is in Section 3.4.6 (p. 206).

11
.

Consider a pool of three page frames and the following sequence of req
uests, where each
number is the ID of a disk page.

1 2 3 3 1 4 2 5 1 4

Suppose we use the
clock

replacement policy. Assume the clock hand rotates clockwise. Every
time the clock replaces a frame, it automatically moves to the next fram
e. Compute the
following:

Number of disk IO's.

The pages that remain in frames at the end.

The number of hits (i.e., page requests that are not page
-
misses).

Which of the following statements is true?

(a)
The number of hits is 5.

(b)

The number
of hits is 3.

(c)
The number of disk IO’s is 8.

(d)

The number of hits is 2.

(e)

The pages that remain in frames at the end are
4,1,5

Solution:

(
e
)

The "clock" policy arranges all the frames in the pool in a circle logically. Each frame has a use bit,
0 or 1. Every
time a disk page is read into a frame, the use bit of the frame is set to 1. In addition, each time a frame's page is
accessed, its use bit is set to 1.

The clock has a hand that rotates clockwise. It tries to find the first frame with a "
0" use bit. If the current frame's
use bit is "0", this frame is replaced. If the frame's use bit is "1," the clock sets it to "0," and moves on, until it finds

a frame with a "0" use bit.

CS423 Homework 1
-

Solution

1

2

3

3

1

4

2

5

1

4

1(1)*

1(1)

>1(1)

>1(1)

>1(1)

4(1)*

4(1)

>4(1)

4(0)

4(0)

>E(0)

2(1)*

2(1)

2(1)

2(1)

>2(0)

>2(1)

2(0)

1(1)*

1(1)

E(0)

>E(0)

3(1)*

3(1)

3(1)

3(0)

3(0)

5(1)*

>5(1)

>5(1)

"E" means "empty." The number in each pair of parentheses is the current use
-
bit value. "*" means a page is
retrieved from disk, and

">" is the clock hand. Therefore:

The number of disk IO's is 6.

The pages that remain in frames at the end are 4, 1, 5.

The number of hits is 4.

Memory Allocation

12
.

Consider a memory management system that allows
overlays

to accommodate proces
ses that
have larger overall memory requirements than can be allocated in one shot in the main memory.
Let a process P be restricted to a total main memory of 512KB at any time. In order to work with
this restriction, let process P be structured as two ove
rlays A and B.

Let the code specific to overlay A have a size of 180KB, let the data specific to overlay B have a
size of 40KB and let the common data across the two overlays be 80KB in size.

Let X represent the size of the code common to both the overla
ys, Y represent the size of the
code specific to overlay B, and Z represent the size of the data specific to overlay A. Which of
the following (X,Y,Z) triples would allow process P to execute in the system?

(a)

(220KB, 140KB, 40KB)

(b)

(220KB, 180KB, 1
0KB)

(c)
(160KB, 240KB, 60KB)

(d)

(160KB, 200KB, 100KB)

(e)

(160KB, 220KB, 80KB)

CS423 Homework 1
-

Solution

Solution:

(
e
)

The total size of overlay A is

X + 80KB + 180KB + Z = X + Z + 260KB

The total size of overlay B is

X + 80KB + Y + 40KB = X + Y + 120KB

Given that pro
cess P is restricted to a main memory size of 512KB, the total main memory required for each
overlay of process P must be at most 512KB. Therefore, each correct answer choice needs to satisfy the two
inequ
alities: X+Z≤252KB and X+Y≤392KB.

Please refer to Section 3.3 (p. 188) for a discussion of Overlays.