Metal Oxide TFTs for Circuit Applications

woundcallousSemiconductor

Nov 1, 2013 (3 years and 5 months ago)

375 views

Metal Oxide TFTs

for Circuit Applications

Arokia Nathan

an299@cam.ac.uk

Engineering Department

Cambridge University

Orama

Summer School: 21 Oct 2012

Contents


Applications of Oxide Transistors


Part 1. Device Physics


Part 2. I
-
V Relations


Part 3. Parameter Extraction


Part 4. Compact Modeling


Part 5. Simulation for Display and Sensor Applications


Summary and Conclusion

Applications of Oxide Transistors

Tfts

must perform analog and digital functions

Physics
-
based compact models needed for circuit design

f
system
(Hz)

frame
-
rate

µ
TFT

(cm
2
/V
-
s)

Application

< 100

< 1

AMLCD, AMOLED, AMFPI

< 1 kHz

< 10

3
-
D displays, RF ID tags, smart cards

< 100 kHz

10


100

adaptable surfaces, embedded imaging,
interactive screens, HDTV, 3D

< 1 MHz

100


1000

distributed sensors/networks, low frequency RF,
NW TFTs and flex computers, holographic displays

Part 1: Device Physics

Density of States

Reduced density of tail states


l敳s trapping.

Pot敮eial barri敲s abov攠E
m




s捡l敤eband mobility by p敲捯cation 捯cdu捴ion

P.V. Erslev et al., Appl. Phys. Lett. 95 (2009) 192115.

Localized Tail States (kT
t
<kT)

• Exponential distribution of tail states.

• Steep tail states: characteristic temperature of tail states (kT
t
) = 20meV < kT of 26meV.

Conduction Mechanisms

M
odified band mobility while considering potential barriers

E
m

E
T

E

E
F

filled tail/deep

states

W
B

D
B

q

B0


q

B

E

f(E)

1

0.5

at T=300K

E
F0

unfilled tail states

Lee
et al.
, Applied Physics Letters 98, 203508 2011.

TLC (Trap
-
limited conduction)

Percolation

Mobility with TLC & Percolation

Modes

Equations for kT
t
< kT

Free

Carrier

Trapped

Carrier

Mobility

where

TLC (Trap
-
limited conduction)

Percolation

V
GS
-
Dependent Mobility

where

If N
C
>> 0.5N
tc
kT
t

Gauss’s law:

Solution of Poisson’s Eq. and Gauss’s law

yields
Δ
E
F

as a function of V
GS
, allowing

Part 2: I
-
V Relations

Above
-
threshold Regime

where

Approximations for Linear Regime

(ignoring higher order terms)

Linear regime

Source

Drain

Gate

Insulator

Oxide semiconductor




Accumulation

Analytical Expression for V’
DS

C
GDO

C
GSO

R
D

R
S

R
dyn

C
t

R
t

C
t

R
t

I
Dt

I
St

I
DS

+

-

+

-

Drain

V
C
/2

V’
DS

Source

Gate

V
C
/2

Pinch
-
off and Saturation Regime

where

Source

Drain

Gate

Insulator

Oxide semiconductor




Pinch
-
off

Source

Drain

Gate

Insulator

Oxide semiconductor




Sub
-
T Current due to Interface States

For Sub
-
Threshold Regime at V
GS

close to V
FB

;

Diffusion current predominant by Interface states (D
it
) (I
it
).

where

Interface state density

E

[eV]

DOS [cm
-
3
eV
-
1
]

E
m

N
dc

(log
-
scale)

tail

deep

E
F0

E
F

Interface states

Sub
-
T Current due to Deep States

For Sub
-
Threshold Regime at V
GS
close to V
T

;

Trap
-
limited conduction due to deep states at bulk (I
deep
).

where

E

[eV]

DOS [cm
-
3
eV
-
1
]

E
m

N
dc

(log
-
scale)

tail

deep

kT
d

E
F

Total Drain Current

1) Linear regime:

2) Saturation regime:


h
armonic average of three
components for each regime

Summary of I
-
V Relations


V
FB

V
T

I
DS
(log
-
scale)

V
GS

Sub
-
T Regime

Above
-
T regime

Sub
-
T current due to interface states

Above
-
T current due to percolation and tail states

Sub
-
T current due to deep states (dangling bonds at bulk)

Part 3: Parameter Extraction

Extraction Procedure

C
-
V Measurements

(at low freq. for a different L)

I
-
V Measurements

(Transfer/Output for a different L)

DOS Extraction

Contact Resistance

Extraction

Extraction of Model Parameters

(power parameters and constants)

C
ox

and
C
ov

Extraction

Parameters for Pinch
-
off Voltage, V
DS
’, etc.

Simulation and Verification (VerilogA)

Q
ref
,

p



Measurements



Device


Characterization

Extraction of Device
Parameters (V
T
, SS, V
FB
)



Model Parameter


Extraction



Circuit Design

for linear regime

for saturation regime

N
tc
, kT
t

R
SD
,

L


sat

m



A
C

Extraction of Tail State DOS

I
-
V Measurement

and Free /Total Charges

Mapping between Surface
Potential and Gate Voltage

Extraction of

Trapped Carrier Density

First Derivative of

Trapped Carrier Density



Sub
-
gap DOS

When kT
t
> kT :

Lee et al.
, Electron Device Letters,
33 (7), 2012
.

Parameter

Value

N
tc

2x10
19
cm
-
3
eV
-
1

kT
t

20meV

S. Lee
et al.
,
Applied Physics Letters
,
101,
036238
, 2012
.

Extracted Tail State DOS

Extraction of R
SD

&

L

V
GS

20

17.5

15

12.5

10

L [



R
tot

[M
W
z

L [



R
tot

[M
W
z

R
SD
=9637
W


L
G
=
-
3.5

m

at V
DS
= 0.1V

R
SD
= 9637
W



R
SD
W= 96.37
W
-



L㴠
-
3.5

m(數eansin)

L [



R
SD

L’ [

m]

15

9637
W

18.5

25

9637
W

28.5

50

9637
W

53.5

100

9637
W

103.5

Negative

L(㴠

3.5

m)


捨cnnel length e硰xnsi潮.

W= 100

m

Extraction of C
ov

& C
ox

V
GS

[V]

C
gs

[pF]

L=100

m

L=50

m

L=25

m

L=15

m

f=1kHz

V
S
= V
D
= 0V

C
gs

[pF]

L’

[



C
ov
= 0.45pF

L’ [

m]

103.5

53.5

28.5

18.5

C
meas
[F/cm
2
]

1.60pF

1.03pF

0.741pF

0.637pF

C
ov
[F/cm
2
]

0.45pF

0.45pF

0.45pF

0.45pF

C
ox
[F/cm
2
]

11.5nF

11.6nF

11.6nF

12.5nF

Linear extrapolation for V
T

extraction



log(I
DS
) vs. V
GS

plot for S extraction

L=15

m

L㴲5

m

L㴵0

m

L㴱00

m

at
DS
= 0.1V


GS

[V]

I
DS

[



V
GS

[V]

Log(I
DS
) [A]

L=15

m

L㴲5

m

L㴵0

m

L㴱00

m

at
DS
= 0.1V

Parameters

L=15 um

L=25 um

50 um

100 um

V
T
[V]

4.34

3.86

3.98

4.33

S

[V/dec]

0.15

0.16

0.17

0.19

D
it
[cm
-
2
eV
-
1
]

1.07x10
11

1.19x10
11

1.31x10
11

1.55x10
11

Extraction of
V
T
, S,
&
D
it

Non
-
iterative solution of V’
DS

log(V
GS
-
V
T
)

log(
z

DS
,I
DS
))

V
GS
[V]

V’
DS
[V]

V
GS
[V]

error

[%]

Parameter

Value

A
C

1.63x10
-
7

R
SD

9637



0.9954



Error Less than 0.1%

Extraction of

p

log(V
GS
-
V
T
)

log(I
DS
/(V
DS
-
R
SD
I
DS
))

slope = 1.0206

=

p
+1

L= 100

m

at
DS
= 0.1V

slope

Parameters

Value

Slope

1.0206


p

0.0206

K (Constant)

Constant

Extraction of Q
ref

V
GS
[V]

Q
ref
[C/cm
2
]

Q
ref

= 7.28
x10
-
8

L= 100

m

at V
DS
= 0.1V

Parameters

Value

Q
ref

7.28x10
-
8

Model Parameters (Above
-
T)

Parameters

Description

Value

Unit


0
*

Effective band mobility scaled by percolation term

15

[cm
2
/V
-
s]

R
SD

S/D total contact resistance for W=100

m

9637

[ohm]

R
SD
W

S/D total contact resistance (standardized)

96.37

[ohm
-
cm]


L

Channel length reduction or expansion

-
3.5

[mm]

C
ov

Total overlap parasitic capacitance

0.45p

[F/cm
2
]

C
ox

Gate capacitance

11.5n

[F/cm
2
]

Q
ref

Reference charge density for above
-
threshold regime

72.8n

[C/cm
2
]


p

Power parameter for above
-
threshold regime

0.0206

unitless


sat

Power parameter for saturation regime

1.08

unitless

n

Harmonic averaging
parameter

5

unitless



Ee捴ive灯per灡rameter

0.9954

畮tless

A
C

Constant for effective drain voltage

0.163m

[ohm
-
1
V
-
h
]

for linear regime

for saturation regime

Model Parameters (Sub
-
T)

Parameters

Description

Value

Unit

Q
fi

Intrinsic charge density

7.05X10
-
14

C/cm
2

V
FB

Flat band voltage

0.55

V

D
it

Interface state density

1.64X10
11

cm
-
2
eV
-
1

C
ox

Gate
-
insulator capacitance

1.15

F/cm
2


d

Exponent for linear regime

2.26

Unitless

Q
d

Reference charge for linear regime

7.80X10
-
8

C/cm
2

Material Parameters

Parameters

Description

Value

Unit

T

Ambient Temperature

300

[K]

kT

Thermal Energy

26m

[eV]

kT
t

Tail State Energy

20m

[eV]

N
C

Effective DOS

5x10
18

[cm
-
3
]

N
tc

Density of Tail States at E
m


2x10
19

[cm
-
3
eV
-
1
]

m
n

Effective Mass for Electrons

0.34m
0

[kg]


S

Channel Permittivity

11.8e
0

[F/cm]

E
F0
-
E
m

Fermi Energy at Flat Band

-
1.175

[
eV
]

Part 4: Compact Modeling

Equivalent Circuit

Static

I
DS
= voltage
-
dependent current source.

R
D
, R
S

= contact resistances (=0.5R
SD
).


Dynamic

C
GDO
, C
GSO

= overlap capacitances (=0.5C
OV
).

I
Dt

= current associated with traps near drain.

I
St
= current associated with traps near source.

R
dyn
= for the transit time for carriers.

C
t
, R
t

= for time constants associated with defects.



Implementation in
VerilogA

or VHDL

C
GDO

C
GSO

R
D

R
S

R
dyn

C
t

R
t

C
t

R
t

I
Dt

I
St

Drain

Source

Gate

V’
DS

I
DS

Transfer Characteristics

at V
DS
= 0.1V

V
GS

[V]

I
DS

[



V
GS

[V]

Error [%]

Measured

Modeled

L=100

m

I
DS

[A] (log
-
scale)

at V
DS
= 20V

I
DS

[



Measured

Modeled

L=100

m

I
DS

[A] (log
-
scale)

V
GS

[V]

Linear regime

Saturation regime

V
GS

[V]

Error [%]

Sub
-
T

Sub
-
T

Above
-
T

Above
-
T

Transfer Characteristics for Different L’s

100

m



m

L㴠25

m

㄰1

m



m

L= 25

m

V
GS

[V]

I
DS

[



V
GS

[V]

I
DS

[



Measured

deled

easred

deled

V
GS

[V]

Error [%]

at V
DS
= 0.1V

L=25

m

L㴵0

m

L㴱00

m

V
GS

[V]

Error [%]

at V
DS
= 20V

L=25

m

L㴵0

m

L㴱00

m

at V
DS
= 0.1V

at
DS
= 20V

Linearregime

atratinr敧ime

Measured

deledFr䰽100

m


V
GS
= 20V

17.5

15V

12.5

㄰1

V
DS

[V]

I
DS

[



Error [%]

V
DS

[V]

V
GS
=10V


GS
=17.5V


GS
=12.5V


GS
=20V

V
GS
=15V

Output Characteristics



Error less
than

3%

Part 5: Circuit Simulation

Examples

OLED Display Pixel

Δ
V
T

[V]

Δ
I
OLED

[



2
-
T Pixel Structure

3
-
T Pixel

OLED

Sel.

VDD

VDATA

I
OLED

2
-
T Pixel

time [sec]

I
OLED

[



V
DATA

[V]

Sel. (i+1) [V]

Sel. (i) [V]

3
-
T Pixel Structure

OLED

Sel. (i)

VDD

VDATA

I
OLED

Sel. (i+1)

hv

Image Sensor Pixel

time [sec]

Vout [V]

Vout [V]

Vout [V]

Vout [V]

Reset

at I
ph
= 5nA

at I
ph
= 10nA

at I
ph
= 15nA

at I
ph
= 20nA

I
ph

[nA]

|
Δ
V
out
| [V]

Dark Signal

Δ
V
out

Δ
V
out

Δ
V
out

Δ
V
out

3
-
T Pixel Structure

PD

VDD

I
ph

Reset

hv

I
Bias

Sel.

V
out

I
ph

C
PD


Material and physical properties of oxide TFTs considered for

modeling
.


Percolation mobility model combined with trap
-
limited
conductiondeduced

from DOS of oxide TFTs.


Current
-
voltage relation derived based on these mobility models

and
device physics, allowing derivation of physically
-
based

compact
model for oxide transistors.


Model parameters extracted using measured I
-
V and C
-
V.


Static and dynamic results of the model with a good agreement

with
measured results.


Simulation for
display
and
sensor applications
performed
based
on
the developed compact model.

Conclusions

Thank
you!