6.4 The Metal-Insulator-Semiconductor FET

woundcallousSemiconductor

Nov 1, 2013 (4 years and 12 days ago)

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6.1 Transistor Operation

6.2 The Junction FET

6.3 The Metal
-
Semiconductor FET

6.4 The Metal
-
Insulator
-
Semiconductor FET

6.5 The MOS Field
-
Effect Transistor

1.
The

channel

current

is

controlled

by

a

voltage

applied

at

a

gate

electrode

that

is

isolated

from

the

channel

by

an

insulator
.

2.
Also

referred

to

as

an

insulated
-
gate

field


effect

transistor
.

(IGFET)

3.
Since

most

such

devices

are

made

using

silicon

for

the

semiconductor,

SiO
2

for

the

insulator,

and

metal

or

heavily

doped

polysilicon

for

the

gate

electrode,

the

term

MOS

field

effect

transistor

(MOSFET)

is

commonly

used
.

1.
When

a

positive

voltage

is

applied

to

the

gate

relative

to

the

substrate

(which

is

connected

to

the

source

in

the

case),

positive

charges

are

in

effect

deposited

on

the

gate

metal
.

2.
In

response,

negative

charges

are

induced

in

the

underlying

Si,

by

the

formation

of

a

depletion

region

and

a

thin

surface

region

containing

mobile

electrons
.

3.
These

induced

electrons

form

channel

of

the

FET,

and

allow

current

to

flow

from

drain

to

source
.

1.
Since

electrons

are

electrostatically

induced

in

the

p
-
type

channel

region,

the

channel

becomes

less

p
-
type,

and

therefore

the

valence

band

moves

down,

farther

away

from

the

Fermi

level
.

2.
Reduces

the

barrier

for

electrons

between

the

source,

the

channel,

and

the

drain
.

3.
If

the

barrier

is

reduced

sufficiently

by

applying

a

gate

voltage

in

excess

of

what

is

known

as

the

threshold

voltage

V
T
,

there

is

significant

current

flow

from

the

source

to

the

drain
.

4.
Thus,

one

view

of

a

MOSFET

is

that

it

is

a

gate
-
controlled

potential

barrier
.

More

common

case

1.
The

voltage

difference

between

the

gate

and

the

channel

reduces

from

V
G

near

the

source

to

(V
G
-
V
D
)

near

the

drain

end
.

2.
Once

the

drain

bias

is

increased

to

the

point

that

(V
G
-
V
D
)

=V
T
,

threshold

is

barely

maintained

near

the

drain

end,

and

the

channel

is

said

to

be

pinched

off
.

3.
Increasing

the

drain

bias

beyond

this

point

(V
D
(sat
.
))

causes

the

point

at

which

the

channel

gets

pinched

off

to

move

more

and

more

into

the

channel
.

Fabrication

of

n
-
channel

MOSFET

0
.

Thick

SiO
2

isolation

layer

by

local

oxidation

of

silicon
.

1.
An

ultrathin

dry

thermal

silicon

dioxide

is

grown

on

the

p
-
type

substrate
.

2.
Cover

it

with

LPCVD

polysilicon,

which

is

doped

heavily

n+
.

3.
The

doped

polysilicon

is

then

patterned

to

form

the

gate,

and

etched

anisotropically

by

RIE

to

achieve

vertical

walls
.

4.
The

gate

itself

is

used

as

an

implant

mask

for

the

n+

implant

which

forms

the

source/drain

junction

abutted

to

the

gate

edges,

but

is

blocked

from

the

channel

region
.

(self
-
aligned

process)

5.
Implanted

dopants

is

annealed
.

6.
Finally,

MOSFETs

have

to

be

properly

connected

according

to

the

circuit

layout,

using

metallization
.


LPCVD

of

an

oxide

dielectric


Etching

contact

holes

by

RIE


Sputter

depositing

a

suitable

metal

such

as

Al,

patterning

and

etching

it
.

6.4.2 The ideal MOS capacitor

Modified work function q
Ф
m

The

modified

work

function

q
Ф
m

is

measured

from

the

metal

Fermi

level

to

the

conduction

band

of

the

oxide
.

Similarly,

q
Ф
s

is

the

modified

work

function

at

the

semiconductor
-
oxide

interface
.

Assume
Ф
m
=
Ф
s

q

F

measures

the

position

of

the

Fermi

level

below

the

intrinsic

level

Ei

for

the

semiconductor
.

This

quantity

indicates

how

strongly

p
-
type

the

semiconductor

is
.

Effectively

deposit

a

negative

charge

on

the

metal
.

In

response,

we

expect

an

equal

net

positive

charge

to

accumulate

at

the

surface

of

the

semiconductor
.

In

case

of

p
-
type

substrate

this

occurs

by

hole

accumulation

at

the

semiconductor
-
oxide

interface
.

Since

the

applied

negative

voltage

depresses

the

electrostatic

potential

of

the

metal

relative

to

the

semiconductor,

the

electron

energies

are

raised

in

the

metal

relative

to

the

semiconductor
.

As

a

result,

the

Fermi

level

for

the

metal

E
Fm

lies

above

its

equilibrium

position

by

qV
,

where

V

is

the

applied

voltage
.

Negative voltage between the metal and the semiconductor

Moving

E
Fm

up

in

energy

relative

to

E
Fs

causes

a

tilt

in

the

oxide

conduction

band
.

We

expect

such

a

tilt

since

an

electric

field

causes

a

gradient

in

E
i

(and

similarly

in

E
v

and

E
c
)
.

Tilt in energy band of the oxide

The

energy

bands

of

the

semiconductor

bend

near

the

interface

to

accommodate

the

accumulation

of

holes
.

It

is

clear

that

an

increase

in

hole

concentration

implies

an

increase

in

E
i
-
E
F

at

the

semiconductor

surface,

since

Tilt in the energy band of the semiconductor

Since

no

current

passes

through

the

MOS

structure,

there

can

be

no

variation

in

the

Fermi

level

within

the

semiconductor
.

Therefore,

if

E
i
-
E
F

is

to

increase,

it

must

occur

by

E
i

moving

up

in

energy

near

the

surface
.

The

result

is

a

bending

of

the

semiconductor

bands

near

the

interface
.

The

Fermi

level

near

the

interfacee

lies

colser

to

the

valence

band,

indicating

a

larger

hole

concentration

than

that

arising

from

the

doping

of

the

p
-
type

semiconductor
.

This

raises

the

potential

of

the

metal
.

Lowering

the

metal

Fermi

level

by

qV

relative

to

its

equilibrium

position
.



Tilt

of

oxide

energy

band
.



Bending

of

the

semiconductor

band
.

The

positive

voltage

deposits

positive

charge

on

the

metal

and

calls

for

a

corresponding

net

negative

charge

at

the

surface

of

the

semiconductor
.

Such

a

negative

charge

in

p
-
type

material

arises

from

depletion

of

holes

from

the

region

near

the

surface,

leaving

behind

uncompensated

ionized

acceptors
.



This

is

analogous

to

the

depletion

region

at

a

p
-
n

junction
.

In

the

depleted

region

the

hole

concentration

decreases,

moving

E
i

closer

to

E
F
,

and

bending

the

bands

down

near

the

semiconductor

surface
.

Positive voltage between the metal and the semiconductor

If

we

continue

to

increase

the

positive

voltage,

the

bands

at

the

semiconductor

surface

bend

down

more

strongly
.

In

fact,

a

sufficiently

large

voltage

can

bend

E
i

below

E
F
.

This

is

particularly

interesting

case,

since

E
F

>>

E
i

implies

a

large

electron

concentration

in

the

conduction

band
.

The

n
-
type

surface

layer

is

formed

not

by

doping,

but

instead

by

inversion

of

the

originally

p
-
type

semiconductor

due

to

the

applied

voltage,

since

Positive voltage (
enhanced
) between the metal and the semiconductor

Inversion region

Define

a

potential



at

any

point

x,

measured

relative

to

the

equilibrium

position

of

E
i
.

This



>

0

This


F

>

0







(V

>

0
)





Strong inversion region



Surface perpendicular electric field

Surface perpendicular electric field

Gauss’s law

We

can

relate

the

integrated

space

charge

per

unit

area

to

the

electric

displacement,

keeping

in

mind

that

the

electric

field

or

displacement

deep

in

the

substrate

is

zero
.

Space charge density Q
s

as a function of surface potential

s

When

the

surface

potential

is

zero

(flat

band

condition),

the

net

space

charge

is

zero
.


When

the

surface

potential

is

negative,

it

attracts

and

forms

an

accumulation

layer

of

the

minority

carrier

holes

at

the

surface
.

The

first

term

in

equation

is

the

dominant

one,

and

the

accumulation

space

charge

increases

very

strongly

(exponentially)

with

negative

surface

potential
.

The

integrated

accumulation

charge

involves

averaging

over

depth

and

introduces

a

factor

of

2

in

the

exponent
.

Since

the

charge

is

due

to

the

mobile

majority

carriers

(holes

in

this

case),

the

charge

piles

up

near

the

oxide
-
silicon

interface
.

(typically

~

20

nm)

The

band

bending

is

generally

small

or

is

said

to

be

pinned

to

nearly

zero
.


For

a

positive

surface

potential,

the

second

term

(linear

term)

of

the

equation

is

the

dominant

one
.

Although

the

exponential

term

exp(q

s
/kT)

is

very

large,

it

is

multiplied

by

the

ratio

of

the

minority

to

majority

carrier

concentration

which

is

very

small,

and

is

initially

negligible
.

Hence

the

space

charge

for

small

positive

surface

potential

increases

as

~

.

The

charge

is

due

to

the

exposed,

fixed

immobile

dopants

(acceptor

in

this

case),

corresponding

to

the

depletion

region
.


The

depletion

width

typically

extends

over

several

hundred

nm
.

Space charge density Q
s

as a function of surface potential

s

At

some

point,

the

band

bending

is

twice

the

Fermi

potential


F
,

which

is

enough

for

the

onset

of

strong

inversion
.

Now

the

exponential

term

exp(q

s

(inv
.
)

/kT)

multiplied

by

the

minority

carrier

concentration

n
o

is

equal

to

the

majority

carrier

concentration

p
o
.

Hence,

for

band

bending

beyond

this

point,

it

becomes

the

dominant

term
.

As

in

the

case

of

accumulation,

the

mobile

inversion

charge

now

increases

very

strongly

with

bias
.

The

typical

inversion

layer

thicknesses

are

~

5

nm,

and

the

surface

potential

now

is

essentially

pinned

at

2


F
.


Space charge density Q
s

as a function of surface potential

s

at strong inversion

The

width

of

the

inversion

region

is

exaggerated

for

illustrative

purposes
.

Actually,

the

width

of

this

region

is

generally

less

than

100
A
.