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VSRD

IJEECE, Vol. 2 (8
), 2012
,
1

5
____________________________
1
,2
Research Scholar
,
2
Assistant Professor
,
1,2,3
Department of
Electronics &
Communication
Engineering
,
Swami
Vivekanand
Subharti University, Meerut
,
Uttar Pradesh,
INDIA.
*Correspondence :
p
rashantdixit.pd@gmail.com
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A Study of Si

Nanowire Transistor in
Working Temperature Range
1
Prashant Dixit
*
,
2
Mohini Preetam Singh
and
3
Vivek Gupta
ABSTRACT
This paper represents the temperature
effect on silicon nanowire transistor. Current

voltage characteristics with
practical values of temperature (

23
0
C
to +62
0
C) are simulated. Variation of drain current, ON current to OFF
current ratio (I
on
/I
off
) and threshold voltage at above temperatures
are investigated. We observed that first in
linear region there is an increasing trend in current with increasing temperature, while in saturation region there
is decreasing pattern in drain current with increasing temperature
.
Keywords :
Nanowire Transist
or, Threshold
Voltage
, Temperature.
1.
INTRODUCTION
The silicon nanowire transistor (Si

NWT) has attracted broad attention from both the semiconductor industry
and academic fields [1]

[3]. Silicon nanowires are attractive option for many nano

electronic applications.
Nanowires are nanoscale structures which
are frequently single crystal materials and are typically cylindrical in
shape. They can be formed in a variety of materials including metals and insulators, but are most frequently
fabricated using semiconducting materials. Since semiconductors are used
in transistors, semiconducting
nanowires are of the most interest. They have attracted attention not only because of their extremely small size,
but because their size causes new physics (quantum effects) to apply, which do not occur classically, that can
cause changes in material properties [4]. Further the temperature can also change the band gap of
semiconductors so it is practical to study the temperature behaviour of Si nanowire transitors. The operation of
future electronic devices, and a wide array o
f additional applications, will depend on the properties of these
nanowires. A new generation of ultra small transistors and more powerful computer chips using tiny structures
called semiconducting nanowires will be more applicable in the future after more
discoveries by researchers.
The fabrication of nanowire FETs is still a technology under development that requires further innovations
before challenging state

of

the

art MOSFETs. To understand device physics in depth and to assess the
Prashant Dixit
et al
/ VSRD
International Journal of Electrical, Electronics
& Comm. Engg. Vol. 2 (8
), 2012
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performance limits
of SNWTs, simulation is becoming increasingly important. Simulation tools can support the
experimental work to accelerate the development of NW FETs. The temperature dependence of the drive current
in Si

nanowire Field

Effect Transistors is very important
part of this paper.
Fig.
1 :
SNWT
Structur
e
2.
SIMULATION
The simulation tool we used here for investigation of the effects of temperature on nanowire
transistors
. This
simulation tool is for nano

scale
s
u
rrou
nding

gate FET structure.
The simulation tool based on PROPHET or
PADRE simulators and both are developed in Bell Laboratories. PROPHET is a partial differential equation
solver for 1, 2, or 3 dimensions and PADRE is a device

oriented simulator for 2D or 3D device with arbitrary
ge
ometry [12]. It provides many useful plots for engineers and deep understanding of physics. The simulation
tool provides self

consistent solutions to the Poisson and drift

diffusion equation [11]. The simulation tool is
used to simulate ballistic transport
in the calculation of the characteristics for SiNWT [12]. At room
temperature, the devices have high normalized ON

current (I
ds
at V
ds
= V
gs
= 1.2 V) of 0.68 mA/µm
(normalized to wire thickness of 7 nm), Vth =
0.2
V, with Ion/Ioff >
and low gate lea
kage of
2
–
5 pA at
room temperature. When the temperature is reduced, the measured Ids

Vgs characteristics with Vds = 50 mV
at different temperatures in both linear and log scales to delineate the subthreshold and strong inversion regions.
Similar to th
e low

temperature effect in bulk devices in the subthreshold region , Ids reduces as temperature
decreases on account of increase in Vth. However, even in the strong inversion, the current remains lower at
lower temperatures than that at higher temperature
, as can be seen from the linear scale. This is contrary to the
intuitive expectation, since the increase in mobility (
ph) from reduced phonon scattering would be expected to
enhance the current at lower temperatures.
3.
RESULT
& DISCUSSION
At the first, the
characteristics of silicon nanowires transistor were simulated at different values of temperature
(250, 275, 300, 315, and 335
k) with following parameters: channel concentration (intrinsic) =
,
source length = drain length = 10nm, source and drain concentration (n

type) =
, channel length =
10nm, channel diameter = 6nm and oxide thickness = 2nm. For gate leakage current and according to
calculation of Y. Taur at gate oxide 1nm thick a
nd gate voltage range (0

1 V) gate current density range is (1

A/
), which mean for our transistor gate area (942
) leakage current will be 9.42pA at Vg = 1V and
this is very small and has no effect on drain current as in “Fig. 2. It can be not
ed that current (normalized to
diameter) increases with increasing temperature at low Vg (>0.4V) and decreasing at high Vg (<0.4V). Also it
can be noted that changing in working temperature tends to change in ON current to OFF current ratio (I on/I
Prashant Dixit
et al
/ VSRD
International Journal of Electrical, Electronics
& Comm. Engg. Vol. 2 (8
), 2012
Page
3
of
7
off), t
hreshold voltage (VT). VT decrease with increasing temperature and temperature effects parameter
(
Id/
T) increase with increasing gate voltage and the greatest effect done at Vg = 1V. Therefore, gate and
drain electrodes must connect directly to Vdd = 1 a
nd source electrode connects to be ground (as shown in “fig.
4”) to get the best used of a transistor as a transistor as a temperature sensor.
“fig. 3” illustrate the effect of temperature on (I on/I off). Value of (I on/I off) ratio decrease exponentiall
y with
increasing temperature, it can be noted that at 275
k greater Ion with smaller Ioff and this tend to best (I on/I
off) ratio. to get the best sensitivity of current with temperature gate and drain electrode connects to be ground
(shown in “fig. 4”)
to get greater (
Id/
T) to use a transistor as a temperature sensors.
Fig.
2
:
Variation
Current With Working
Temperature
if Vd=1V In Current Above
Fig.
3
:
Variation of ON
Current
to OFF
Current
(Ion/Ioff)
With Working
Temperature When
Vd=1V
.
0.01
0.015
0.02
0.025
250
275
300
325
350
I
DS (A/um)
Temperature (K)
1.00E+05
2.10E+06
4.10E+06
6.10E+06
8.10E+06
1.01E+07
250
300
350
I
ON
/I
OFF
Temperature (K)
Prashant Dixit
et al
/ VSRD
International Journal of Electrical, Electronics
& Comm. Engg. Vol. 2 (8
), 2012
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of
7
F
ig.
4
:
Variation of T
hreshold Voltage (Vth)
With Working
Temperature When
Vd=1V
.
4.
CONCLUSION
Temperature
effects
of silicon nanowire transistor were simulated
using simulation tool.
Transfer characteristic
at Vd = 1V was investigated with different values
of working
temperature (250, 275, 300, 315
, and 3
35
k
).The
result
can be divided into two regions, at first region t
here is an increasing in (I on/I off) with increasing
with
increasing temperature, while the second region there is decreas
ing in the thresh
old voltage (Vth
) and (I on/I
off) ratio with increasing working temperature. Maximum sensitivity of current with temperature done at Vd =
Vg = 1V
.
5.
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& Comm. Engg. Vol. 2 (8
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