Microelectronics and VLSI Design
COURSE SCHEME
For
MASTER OF ENGINEERING
(
ELECTRONICS AND COMMUNICATION ENGG.
(
WITH
SPECIALIZATION
Microelectronics and VLSI Design
)
(REGULAR)
(SEMESTER SYSTEM)
YEAR 201
3

201
4
Batch 201
3
Microelectronics and VLSI Design
S.No
Subject
code
Subject
Contact hrs/
Marks
Credits
SEMESTER
–
I
L
T
P
INT
EXT
TOTAL
1.
ECT 501
Advanced
Engineering
Mathematics
4
0
0
4
0
6
0
100
4
2.
ECT 512
Embedded
Systems
4
0
0
4
0
6
0
100
4
3.
ECT 513
Advanced
VLSI
Design
4
0
0
4
0
6
0
100
4
4.
ECT 51
X
Elective I
4
0
0
4
0
6
0
100
4
5.
ECT 51
X
Elective II
4
0
0
40
60
100
4
6.
ECP 51
4
Lab I
0
0
4
40
60
100
2
7.
ECT 505
SEMINAR
2
0
0
100
0
100
1
Total
2
2
0
4
34
0
36
0
7
00
2
3
SEMESTER

II
9.
ECT 56
5
VLSI Signal
Processing
4
0
0
40
60
100
4
10.
ECT 56
6
VLSI
Architectures
4
0
0
40
60
100
4
11.
ECT 5X
X
Elective III
4
0
0
40
60
100
4
12.
ECT 5X
X
Elective IV
4
0
0
40
60
100
4
13.
ECT 5
XX
Elective V
4
0
0
40
60
100
4
14.
ECP 554
Lab II
0
0
4
40
60
100
2
15.
ECT 599
SEMINAR
2
0
0
100
0
100
1
Total
2
2
0
4
3
4
0
36
0
7
00
2
3
SEMESTER

III
1
7
.
ECP 601
Research Project
100
0
100
4
18
.
ECT 602
SEMINAR
2
0
0
100
0
100
1
19
.
ECT 60X
Elective VI
4
0
0
40
60
100
4
2
0
.
CME 604
Research
Methodology
4
0
0
40
60
100
4
Total
1
0
0
0
28
0
12
0
4
00
1
3
SEMESTER

IV
22
.
ECT 6
5
1
Thesis
20
Total
20
Microelectronics and VLSI Design
Specialization: Microelectronics and VLSI Design
Elective I
& II
S.No
Subject code
Subject
Credits
1.
ECT 515
IC Fabrication
Technology
4
2.
ECT 516
Synthesis Using HDLS
4
3.
ECT 517
ASICs and FPGAs
4
4.
ECT 518
Sensor
Technology &
MEMS
4
ELECTIVE III, IV & V
1.
ECT 56
7
Design of Analog/Mixed
Signal VLSI Circuits
4
2.
ECT 56
8
Testing and Fault
Tolerance of VLSI
Circuits
4
3.
ECT 56
9
MOS Device Modeling
4
4.
ECT 5
70
Optical VLSI
4
5.
ECT 57
1
Digital VLSI Design
4
6.
ECT 57
2
Low Power VLSI Design
4
ELECTIVE VI
1.
ECT 606
RF IC Design
4
2.
ECT 607
High Speed VLSI Design
4
Microelectronics and VLSI Design
ECT

501
ADVANCED ENGINEERING MATHEMATICS
L T C
4 0
4
Max Marks: 60
Contact Hours:48
Course objectives
To reinforce the mathematical foundation with advanced topics.
To enable the student to appreciate the engineering aspect of mathematics.
To equip the student with tools to confront continual mat
hematical challenges
.
Unit1
Review of FT & it’s Proof, properties of FT

:
Fourier Transform, Fourier Integral Theorem,
Complex Form of Fourier Integral . DFT and its inverse, Properties of DFT, Inverse Fast
Fourier Transform, Wavelet Transform, Multi resolution Analysis by the wavelet method.
(12)
Unit

II
Z

Transform, Introduction, Properties of Z

Tr
ansform, Evaluation of inverse Z
–
Transform,
Applications.
(8)
Conformal Mapping, Introduction, Linear mapping, Bi

linear mapping, Schwarz

Christoffel
transformation.
(7)
Unit

III
Vector spaces. Subspaces, Linear independence, Basis, Dimension, Finite dimensional vector
spaces, Direct sum. Vector space of matrices. Linear Transformatio
n, Matrix representation
of linear transformation. Change of basis.
(8)
Calculus Of Variations : Euler

Lagrange’s differential equation, Brachistochrone problem
and other applications. Isoperimetric problem, Hamilton’s Principle and Lagra
nge’s
Equation.
(10)
Convolution
: Properties of convolution, Circular convolution, Deconvolution
(3)
Recommended Books:
1. Higher Engineering Mathematics

by Dr. B.S. Grewal; Khanna Publishers
2. Fourier Series and Boundary Values Problems

by Churchill; McGraw Hill.
3. Complex Variables & Applications

by Churchill; McGraw Hill.
4. Calculus of Variations

by Elsgol
e; Addison Wesley.
5. Calculus of Variations

by Galfand & Fomin; Prentice Hall.
6. The Use of Integral Transforms

by I.N. Sneddon., Tata McGraw Hill
Microelectronics and VLSI Design
ECT 512
EMBEDDED SYSTEMS
L T C
4 0 4
Max Marks: 60
Contact Hours:48
Course objectives
To understand embedded processing concepts and embedded processors.
To understand Real time operating system and its
relevance to embedded systems.
To understand system design and emulation concepts.
UNIT I
Embedded Processing:
Introduction to Embedded Computing, Difference between
Embedded and General

Purpose Computing, Characterizing Embedded Computing,
Design Philos
ophies,
RISC, CISC, VLIW versus superscalar, VLIW versus DSP Processors,
Role of the Compiler,
Architectural structures, The datapath, Registers and Clusters,
Memory Architecture, Branch
architecture, Speculation and prediction, Prediction in
the embedded
domain, Register File
Design, Pipeline Design, the control unit, control
registers.
(12
)
Embedded Processors:
Microprocessor versus Microcontroller architecture, ARM
architecture,
Embedded Cores, Soft and Hard Cores, Architecture of Configurable
Microblaze soft core,
Instruction set, Stacks and Subroutines, Microblaze Assembly
Programming, Input

Output
interfacing, GPIO, LCD interfacing, Peripherals, DDR
Memory, S DRAM, Microblaze i
nterrupts,
Timers, Exceptions, Bus Interfacing, DMA,
On

chip Peripheral bus (OPB), OPB Arbitration,
OPB DMA.
(12
)
UNIT II
RTOS and Application design:
Programming language choices, Traditional C and
ANSI C,
C++ and Embedded C++, matlab, Embedded JAVA, Embedded C
extensions, Real time
operating systems, Embedded RTOS, Real time process
scheduling, structure of real time operating system, Memory management in
Embedded operating system, operating system
overhead
, interprocess communication
mechanisms, File systems in Embedded devices, Different types of locks, Semaphores,
Application studies with Vxworks, Montavista Linux etc.
(12
)
UNIT III
System Design and Simulation:
System

on

a

Chip (SoC), IP Bloc
ks and Design
Reuse,
Processor Cores and SoC, Non

programmable accelerators, reconfigurable logic,
multiprocessing
on a chip, symmetric multiprocessing, heterogeneous
multiprocessing, use of simulators,
Compilers, Loaders, Linkers, locators, assemblers,
Li
braries, post run optimizer, debuggers,
profiling techniques, binary utilities, linker
script, system simulation, In Circuit Emulation,
Validation and verification, Hardware
Software partitioning, Co

design.
(12
)
Microelectronics and VLSI Design
Recommended Books
1.
Wolf, W.,
High

Performance Embedded Computing Architectures, Applications,
and Methodologies, Morgan Kaufman Publishers (2007).
2.
Heath, S., Embedded Systems Design, Elsevier Science (2003).
3.
Fisher, 1.A., Faraboschi, P. and Young, C., Embedded Computing

A VLIVV
Approach to Architecture, Compilers and Tools, Morgan Kaufman
(2005)
4.
Simon, D.E., An Embedded Software Primer, Dorling Kindersley (2005).
Microelectronics and VLSI Design
ECT

5
1
3
A
DVANCED
VLSI DESIGN
L T C
4 0 4
Max Marks: 60
Contact Hours:48
Course objectives
To facilitate the student with VLSI design and simulation procedures.
To understand the working and results of various digital circuits and
components.
To understand various stages in design of VLSI.
UNIT I
I
ntroduction to VLSI:
Introduction to solid state electronics, CMOS Logic, VLSI Design Flow.
(2)
MOS FET theory: Ideal V

I Characteristics, C

V Characteristics, Non

ideal I

V
Characteristics,
(4
)
CMOS processing technology: P

well, N

well, Twin Tub and silicon on Insulator
processing, layout Design rules, CMOS Process enhancement.
(4
)
CMOS Circuit and Logic design:
Combinational Circuit Design: Introduction, circuit Families like static CMOS, Ratioed
circuits, CVSL, Dynamic Circuits, Pass Transistor circuit,.
(3
)
Sequential Circuit design: Sequencing methods, Max

Delay constraints, Min

delay
constraints, time bo
rrowing, and clock skew.
(3
)
Data Path Subsystems: Adders, Sub tractors, Comparators, flip

flops, Shifter, counters,
Multiplie
r
(6
)
UNIT II
Design Methodology
&
Tools:
Design
Methodology: Introduction, structured Design, Programmable logic, fully Custom
design, CAD tools in VLSI Design Process.
(6
)
Floor Planning: Introduction, Block Placement and Channel Definitions, Global Routing,
Switchbox routing, Power Distribution
, clock Distribution.
(6
)
Architecture Design: Introduction, HDLs, High level synthesis, Logic Synthesis.
(6
)
UNIT III
VLSI Simulation and Algorithm:
Hierarchy of simulation tools, Switch level simulations, Layout synthesis, Placements
and routing algorithms, spice simulation.
(8
)
Microelectronics and VLSI Design
Recommended Books:
1.
CMOS Vlsi design by Neil H.E. Weste, David Harris, Ayan Banerjee
(Pearson Educati
on)
2.
Modern VLSI Design by Wayne Wolf (Pearson education)
3.
FPGA

Based system design by Wayne Wolf (Pearson Education)
4.
Introduction to VLSI Systems by Mead and Conway (Addison wisely)
5.
VLSI Desiogn by Puckneel.
Microelectronics and VLSI Design
ECP
–
514
VLSI LAB
L
T
C
0
0
2
List of Experiments
1.
To Study the basic features of Xilinx and Design Methodologies used for digital
design.
2.
Design, Synthesis and Simulation of Basic Gates.
3.
Design, Synthesis and Simulation of following.
a)
Half Adder
b)
Full Adder
4.
Design,
Synthesis and Simulation of following.
a)
4:1 Multiplexer
b)
1:4 Demultiplexer
5.
Design, Synthesis and Simulation of following.
a)
SR flip

flop
b)
Jk flip

flop
c)
T flip

flop
6.
Design, Synthesis and Simulation of following.
a)
SR flip

flop
b)
J
K
flip

flop
c)
T flip

flop
7.
Design, Synth
esis and Simulation of 4

bit up and 4

bit up down counter.
8.
Design, Synthesis and Simulation of 4

bit parallel to serial convertor.
9.
Design, Synthesis and Simulation of 4

bit serial to parallel convertor.
10.
Minor Project

Design, Synthesis and Simulation of 4

bit Airthmatic Logic Unit.
Microelectronics and VLSI Design
SEMESTER

2
Microelectronics and VLSI Design
ECT 5
6
5
VLSI
SIGNAL PROCESSING
L T C
4 0 4
Max Marks: 60
Contact Hours:48
Course objectives
The students will be able to
1.
Analyse the DSP systems’ features.
2.
Design the optimum architecture for various signal processing algorithms on VLSI
based platforms.
3.
Optimize the algorithms for fast and efficient calculation required for VLSI based
Signal processing systems.
Introduction
:
Introduction to DSP Systems, Terminating and Non

Terminating,
Representation of DSP programs, Data Flow graphs (DFGs), Single rate and multi rate DFGs,
Iteration bound, Loop, Loop Bound, Iteration rate, Critical loop, Critical path, Area

Speed

Power trad
e

offs, Precedence constraints, Acyclic Precedence graph, Longest Path Matrix
(LPM) and Minimum Cycle Mean (MCM) Algorithms, Pipelining and parallel processing of
DSP Systems, Low Power Consumption.
(8)
Algorithmic Transformations:
Retiming, Cut

set
retiming, Feed

Forward and Feed

Backward, Clock period minimization, register minimization, Unfolding, Sample period
reduction, Parallel processing, Bit

serial, Digit

serial and Parallel Architectures of DSP
Systems, Folding, Folding order, Folding Factor,
Folding Bi

quad filters, Retiming for
folding, Register Minimization technique, Forward Backward Register Allocation technique.
(9)
Unit

II
Systolic Architecture Design and Fast Convolution:
Systolic architecture design
methodology, Projection vector,
Processor Space vector, Scheduling vector, Hardware
Utilization efficiency, Edge mapping, Design examples of systolic architectures, Cook

Toom
Algorithm and Modified Cook

Toom Algorithm, Wniograd Algorithm and Modified
Winograd Algorithm, Iterated Convolut
ion, Cyclic Convolution.
(14)
Unit

III
Algorithm Strength Reduction:
Introduction, Parallel FIR filters, Polyphase decomposition,
Fast FIR filters Algorithms, Discrete Cosine Transform and Inverse Discrete Cosine
Transform, Algorithm

Archi
tecture Transformation, DIT Fast DCT, Pipelined and Parallel
Recursive and Adaptive Filters, Look

Ahead Computation, Look

Ahead Pipelining,
Decompositions, Clustered Look

Ahead Pipelining, Scattered Look

Ahead pipelining,
Parallel processing in IIR Filters
, Combining Pipelining and Parallelism.
(10)
Scaling and Round

off Noise:
Introduction, State variable description of Digital Systems,
Scaling and Round

off Noise Computation, Slow

Down Approach, Fixed

point digital filter
implementation.
(7)
Microelectronics and VLSI Design
Recommended Books:
1. Parhi, K.K., VLSI Digital Signal Processing Systems: Design and Implementation, John
Wiley (2007).
2. Oppenheim, A.V. and Schafer, R.W., Discrete

Time Signal Processing, Prentice Hall
(2009) 2nd ed.
3. Mitra, S.K., Digital
Signal Processing. A Computer Based Approach, McGraw Hill
(2007)3rd ed.
4. Wanhammar, L., DSP Integrated Circuits, Academic Press (1999).
Microelectronics and VLSI Design
ECT 5
6
6
VLSI ARCHITECTURES
L T C
4 0 4
Max Marks: 60
Contact Hours:48
Course objectives
To appreciate the differences between RISC and CISC.
To understand pipeline processing and memory architecture.
To facilitate the student with concepts
UNIT I
Complex Instruction Set Computers (CISC):
Instruction Set, Characteristics and
Functions,
Addressing Modes, Instruction Formats, Architectural Overview, Processor
Organization,
Regis
.
ter Organization, Instruction Cycle, Instruction Pipelining, Pentium
Proc
essor, PowerPC Processor.
(10
)
Reduced Instruction Set Computers (RISC):
Instruction execution Characteristics,
Register
Organization, Reduced Instruction Set, Addressing Modes, Instruction Formats,
Architectural
Overview, RISC Pipelining,
Motorola 88510, MIPS R4650, RISC Vs. CISC.
(8
)
UNIT II
Pipeline Processing:
Basic Concepts, Classification of Pipeline Processors, Instruction
and
Arithmetic Pipelining: Design of Pipelined Instruction Units, Pipelining Hazards and
Scheduling
, Principles of Designing Pipelined Processors.
(6
)
Memory Architectures:
Memory hierarchy design, Multiprocessors, thread level parallelism
and
multi

core architectures, I10 buses. Arithmetic: Fixed point, Floating point and
residue
arithmetic,
Multiply and Divide Algorithms.
(9
)
Issues in arithmetic system design, Issues in the applications (optimizing the hardware
—
software interface), AM', reconfigurable computing, Future'microprocessor architectures.
(5
)
UNIT III
Superscaler Processors:
Overview, Design Issues, PowerPC, Pentium.
(10)
Microelectronics and VLSI Design
Recommended Books
1.
Patterson, D.A. and Hennessy, J., Computer Architecture: A Quantittthve
Approach, Morgan Kaufmann (2003)3
rd
ed.
2.
Stallings, W., Computer Organization and
Architecture: Designing for
Performance, Prentice Hall (2003) 7th ed.
3.
Patterson, D.A. and Hennessy,J., Computer Organization and Design,
Elsevier(2004). 3
r4
ed.
4.
Flynn, M.J. and Oberman, S.F., Advanced Computer Arithmetic Design, Wiley
(2001).
5.
Parhami, B., Computer Arithmetic Algorithms and Hardware Design, Oxford
(2000).
Microelectronics and VLSI Design
SEMESTER

3
Microelectronics and VLSI Design
CME

604
RESEARCH METHODOLOGY
L T C
4 0 4
Max. Marks: 60
Contact Hours : 48
Course Objectives:
Formulize the research / project proposals.
Analyse the parameters involved in the research.
Test the hypothesis formulated.
Unit
–
1
Introducti
on:
Nature and objectives of research,
Types of research,
, Research methods
vs
Methodology, Types of research , Descriptive
vs
. Analytical, Applied
vs
. Fundamental,
Quantitative
vs
. Qualitative, Conceptual
vs
. Empirical
criteria of good research, defining
the
research problem,
Preparation and presentation of research proposals, Selection of thrust area
of research, defining scope of the research problem.
(7)
Research Formulation
and Design
:
D
efining and formulating the research problem, selecting
the problem, Necessity of defining the problem, Importance of literature review in defining
a problem,
Research Design:
Meaning and need for research design, Features of a good design,
important
concepts relating to research design , Observation and Facts, Laws and Theories,
Prediction and explanation, Induction, Deduction, Development of Models. Developing a
research plan, Exploration, Descript
ion, Diagnosis, Experimentation,
Determining
experim
ental and sample designs.
(9)
Unit
–
2
Sample
Design
s
:
Sampling and its need
,
criteria of selecting a sampling procedure,
characteristics of a good sample designs, Diffe
rent types of sample designs.
Data Collection
and analysis:
Collection of Primary data and secondary data, Data Processing and Analysis
strategies
(7)
Introduction to Statistical Analysis:
Measures of Central Tendency and Dispersion,
Ran
dom
Variables and Probability
, Mathematical Expectation, Probability distributions, Binomial,
Poisson, Geometric, Exponential, Normal and log

normal distributions.
Hypothesis Testing:
Tests of Significance based on normal, t and chi

square
distributions, Analysis of variance technique
s.
Correlation and Regression:
Introduction to growth curves and multiple regression, Linear
regression, Least square principle and fitted models, Karl Pearson’s correlation coefficient, Rank
Correlation, Lines of regression
(11)
Unit
–
3
Reporting writin
g:
Structure and components of scientific reports,
types of report
,
technical
reports and thesis
, significance
, different steps in the preparation,
layout, structure a
nd
Language of typical reports
, Illustrations and tables

Bibliography, referencing and
footnotes
,
Microelectronics and VLSI Design
oral presentation Planning
,
preparation,
practice,
making presentation, use of visual aids,
importance of effective communication
(9
)
Application of results and ethics
Environmental impacts,
ethical issues,
ethical committees, commercialization Intellectual
property rights
and patent law
, Trade Related aspects of Intellectual Property Rights,
reproduction of
published material, plagiarism,
citation and acknowledgement
,reproducibility and accountability.
(5)
Recommended Books:
1.
Dowdy, S., Wearden, S. and Chilko, D., Statistics for Research, Wiley
Series (2004)
2.
Walpole, R.E., Myers, R.H., Myers, S.L. and Ye, K., Probability and Statistics for
Engineers and Scientists, Pearson Education (2002).
3.
Kothari C.R., Research Methodology: Methods and Techniques, New Age
International Publishers, 2
nd
Edition
.
4.
Bordens K.S., Abbott B.B., Research and Design Methods, 6
th
Edition, TMH
Publishing Company Limited.
5.
Johnson, R.A, Probability and Statistics by , PHI

2
nd
edition
6.
Trivedi K.S., Probability & Statistics With Reliability, Queuing And Computer
Science Appli
cations , 2
nd
Edition, John Wiley & Sons
7.
Meyer, P.L., Introduction to Probability & Statistical, Applications, Oxford, IBH
8.
Johnson, R.A., Probability and Statistics, PHI, New Delhi
9.
Krishnaswami, K.N., Sivakumar, A. I. and Mathirajan, M., Management Researc
h
Methodology, Pearson Education: New Delhi
10.
Zikmund, W.G., Business Research Methods, 7
th
Edition, Thomson South

Western
11.
Cooper, D. R. and Schindler, Business Research Method , P.S Tata McGraw Hill,
New Delhi
2
nd
edition (2010)
Microelectronics and VLSI Design
ELECTIVE I & II
Microelectronics and VLSI Design
ECT

515
IC FABRICATION TECHNOLOGY
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives
To understand various stages of IC fabrication in depth.
To
understand techniques and procedures involved at each stage.
To appreciate sub micron process techniques
UNIT I
Crystal Growth and Wafer Preparation:
Electronic Grade Silicon, Czochralski
Crystal
Growing, Silicon Shaping, Processing Considerations.
(4)
Epitaxy:
Vapour Phase Epitaxy

Basic Transport Processes and Reaction Kinetics, Doping
and
Auto

Doping, Equipments and Safety Considerations, Buried Layers, Epitaxial
Defects,
Molecular Beam Epitaxy

Equipment Used, Film Characteristics, S
OI Structures.
(8)
UNIT II
Diffusion:
Models of Diffusion in Solids, Fick's laws for Diffusion, Measurement
Techniques,
Fast Diffusion in Silicon, Diffusion in Polycrystalline Silicon and SiO2.
(5)
Oxidation:
Growth Mech
anism and Kinetics, Silicon Oxidation Model, Interface
Considerations,
Orientation Dependence of Oxidation Rates Thin Oxides. Oxidation
Technique and Systems

Dry and Wet Oxidation, Plasma Oxidation, Masking Properties of
Si02.
(
9
)
UNIT III
Li
thography:
Optical Lithography

Optical Resists, Contact and Proximity Printing,
Projection
Printing, Electron Lithography

Resists, Mask generation, Electron Optics

Roaster Scan and Vector Scan, variable beam shape, X

ray lithography

Resists and
Pri
nting, X

ray sources and
masks, Ion

Lithography.
(10
)
Etching:
Reactive plasma etching, AC and DC plasma excitation, plasma properties,
chemistry and surface interactions, feature size control and an isotropic etching, ion
enhanced and induce
d
etching, properties of etch processes. Reactive

Ion

Beam
—
Etching, Specific etch processes: PolySi/Polycide, Trench etching, SiO
2
and Si3N4.
(10
)
Sub

micron Process Techniques; ULSI Technology; Nano

Fabrication.
(2)
Microelectronics and VLSI Design
Recommended Books
1.
Sze, S.M.,
VLSI Technology, Tata McGraw Hill (2008).
2.
Plummer, J.D., Deal M.D. and
Griffin P.B.,
VLSI Technology:
Fundamentals,
Practice, and Modeling, Prentice Hall
(2000).
3.
Nagcliodhari, D., Principles of Microelectronics Technology,
A
H Wheeler
998).
4.
Gand
hi, S.K., VLSI Fabrication Principles, John
,
Wiley
(2003)
2I
ed.
Microelectronics and VLSI Design
ECT

516
SYNTHESIS USING HDLS
L T C
4 0 4
Max
Marks: 60
Contact Hours : 48
Course Objectives
To appreciate the use of HDLs for synthesis of digital circuits.
To introduce various operators, libraries and tools for synthesis.
To facilitate the student with detailed information about need and results of
each step.
UNIT I
Introduction:
Concepts of Hardware Description Languages and logic synthesis.
(
1)
Logic synthesis:
Design cycle, types of synthesizers, design testing and verification,
design
optimization
.
techniques, technology mapping, VHDL design hierarchy,
objects, types and
subtypes, design organization, VHDL design cycle.
(5
)
RTL Level Design:
RTL design stages, VHDL description of the RTL design.
(2
)
Combinational Logic:
De
sign units, entities and architectures, simulation and synthesis
mo'del,
signals and ports, simple signal assignments, conditional signal assignments,
selected signal
assignment.
(5)
Types: Synthesizable types, standard types, standar
d operators, scalar types, records,
arrays,
attributes.
(3)
UNIT II
Operators:
standard operators, operator precedence, Boolean operators, comparison
operators, arithmetic operators, concatenation operators.
(1)
Package std_logic_arith:
std_logic_arith package, making the package visible, contents of
std_logic_arith, resize functions, operators, shift functions, type conversions, constant
values,
mixing types in expressions, numeric packages.
(3)
S
equential VHDL:
Processes, signal assignments, variables, if statements, case statements.
(2)
Registers:
Simulation and synthesis model of register, register templates, clock types,
gated
registers, resettable registers, simulation model of asynchronous reset,
asynchronous reset
templates, registered variables.
(4)
Hierarchy:
Role of components, using components, component instances,
component
declaration, Configuration specifications
, default binding, binding process,
component packages, generate statements.
(4)
Sub programs:
Functions, type conversions, procedures, declaring subprograms.
(2)
Microelectronics and VLSI Design
UNIT III
Test Benches:
Test benches, verifying responses, c
locks and resets, printing response
values,
reading data files, reading standard types, error handling.
(5)
Libraries:
Standard libraries, organising files, library names, library work,
incremental
compilation.
(6
)
Basic principles of
Combinational logic design, sequential logic design, arithmetic circuit
design
and control logic design.
(5
)
Recommended Books
1.
Naylor,
D.
and Jones, S., VHDL: A Logic Synthesis Approach, Springer (1997).
2.
Rushton, A., VHDL for Logic Synthesis,
Wiley (1998) 2
.1
Ed.
3.
Ashenden P., The Designer’s Guide to VHDL, Elsevier(3
rd
Ed)
Microelectronics and VLSI Design
ECT 517
ASICs
AND FPGA
s
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives:
To provide a review of concepts and procedures of HDLs.
To appreciate the differences between ASIC and FPGA.
To understand the underlying techniques of ASIC and FPGA
UNIT I
Overview:
Digital system design options and tradeoffs, Design methodology and
technology
overview, High Level System Architecture and Specification:
Behavioral modeling and
simulation.
(6)
Review HDLs:
Hardware description languages, combinational and sequential design,
state
machine design, synthesis issues, and test benches.
(4)
FPGA Architectures and Technologies:
FPGA Architectural options, granularity of
function
and wiring resources, coarse
vs
.
fine grained vendor specific issues (emphasis on
Xilinx).
(6
)
UNIT II
Logic Block Architecture:
FPGA logic cells, timing models, power dissipation.
(
4
)
I/O block architecture:
Input and Output cell characteristics, clock input
, Timing,
Power
dissipation. Programmable interconnect

Partitioning and Placement. Routing
resources, delays.
(7)
Applications:
Embedded system design using FPGAs, DSP using FPGAs, Dynamic
architecture
using FPGAs, reconfigurable
systems, application case studies.
(5)
UNIT III
ASICs:
Types of ASICs, ASIC design flow, Programmable ASICs, Anti

fuse, SRAM,
EPROM,
EEPROM based ASICs, Programmable ASIC logic cells and I10 cells,
Programmable
interconnects.
(8
)
ASIC Methodologi
es (classical) and ASIC Methodologies (aggressive).
(8
)
Microelectronics and VLSI Design
Recommended Books
1.
Smith, M.J.S., Application Specific Integrated Circuits, Pearson
education
(2006).
2.
Wolf W, FPGA Based System Design, Morgan Kaufinann (2007).
3.
Ashenden, P., Digital Design
using VHDL, Prentice Hall (2008).
4.
Maxfield, C., The Design Warriors's Guide to FPGAs, Elsevier (2004).
Microelectronics and VLSI Design
ECT 518
SENSOR TECHNOLOGY & MEMS
L T C
4 0 4
Max Marks: 60
Course Objectives:
To
provide an overview of microsensors and microactuation.
To understand various design considerations and tradeoffs.
To introduce CAD tools for MEMS design and simulation.
UNIT I
Overview, Working principle of microsensors & microactuation, Scaling laws
in
geometry, electrostatic & electromagnetic forces, electricity, fluid mechanics
and heat
transfer.
(9)
Materials for MEMS, active substrate materials, pol ymers as MEMS
materials.
Considerations for micro fabrication, bulk micro manufacturing, surface
rnicro machining,
LIGA process.
(8)
UNIT II
Micro system packaging, die

, devices

and system

level packaging, interfaces
in
micro system packaging for different applicat
ions, signal mapping and transduction.
(7)
Micro system design considerations, process design, mechanical design,
mechanical
design using FEM, design considerations for optical, fluidic, RF and Bio

MEMS.
(8)
UNIT III
Overview
of CAD tools for MEMS design and simulation.
(
16
)
Recommended Books:
1.
MEMS & Micros ystem

Design & Manufacture, Tai

Ran Hsu, Tata McGraw
Hill.2002
2.
Fundamentals of Micro fabrication, Marc Madou, CRC press. 199
0
3.
Micro system Design, Stephen Senturia, Kluwer Academic Publishers. 2000
4.
An Introduction to Micro electromechanical System Engineering, Nadim
Maluf, Artech
House. 1998
5.
Microsensors MEMS and Smart Devices, Gardner and Varaden, John
Wiley & sons.
1995
Microelectronics and VLSI Design
ELECTIVE III, IV & V
Microelectronics and VLSI Design
ECT 567
DESIGN OF
ANALOG/MIXED SIGNAL VLSI CIRCUITS
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives:
To introduce the concept of analog VLSI.
To understand
various converter architectures.
To understand the design process and challenges of high performance converters.
UNIT I
Introduction:
Device Models, IC Process for Mixed Signal, Concepts of MOS Theory.
(2)
Comparators:
Circuit Modeling, Auto Zeroing Comparators, Differential
Comparators,
Regenerative Comparators, Fully Differential Comparators, Latched
Comparator.
(7
)
Data Converters:
Requirements, Static and Dynamic P
erformance, SNR
and BER, DNL,
IN
L
(4)
High Speed AID Converter Architectures:
Flash, Folding, Interpolating, Piplelined.
(3)
UNIT II
High Speed D/A Converter Architectures:
Nyquist

Rate D/A Converters, Thermometer
Coded
D/A Converters, Binary Weighted D/A Con
verters.
(3)
Design
of multi channel low level and high level data acquisition systems using ADC/DAC,
SHA and Analog multiplexers, Designing of low power circuits for transducers.
(3)
Sigma

Delta Data Converter Architectures:
Programma
ble Capacitor Arrays (PCA),
Switched Capacitor converters, Noise Spectrum, Sigma

Delta Modulation Method, Sigma

Delta AID and D/A'Converters, Non Idealities.
(5)
Key Analog Circuit Design:
Analog VLSI building blocks, Operationa
l
Amplifiers for
converters, advanced op

amp design techniques, Voltage
Comparators, Sample

and

Hold
Circuits.
(6)
UNIT III
Implementation and Design of High Performance AID and D/A Converters:
System
Design,
Digital Compensation, Noise,. and Mismatch, Layout and Simulation
Technologies for Data
Converters.
(6
)
Design Challenges:
Low Voltage Design, Ultra

High Speed Design, High Accuracy Design.
(3)
Advanced Topics:
Mu
ltipliers, Oscillators, Mixers, Passive Filter Design, Active filter
design,
Switched Capacitor Filters, Frequency Scaling, Phase

Locked Loops, Device
Modeling for AMS
IC Design, Concept of AMS Modeling and Simulation
(6
)
Microelectronics and VLSI Design
Recommended Books:
1.
Plassche,
Rudy
',Van De, Integrated A

D and D

A Converters, Springer (2007)2
nd
ed.
2.
Gregorian, R. and Tellies, C. C., Analog
MOS
Integrated Circuits for Signal
Processing, Wiley (2002).
3.
Baker, R.j.,
Li, H.I.V.
and Boyce,
I).F.,
CMOS: Circuit Design, Layout and
Simulation,
IEEE Press
(2007)2
ND
ed
4.
Gregorian, R., Introduction to CMOS Op

Amps and Comparators, Wiley
(1999).
5.
Jespers, P.G. A., Integrated Converters: D

A. and
A

I.)
Architectures, Analysis
and Simulation, Oxford Press
(20
01).
Microelectronics and VLSI Design
ECT 568
TESTING AND FAULT TOLERANCE OF VLSI CIRCUITS
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives:
To understand the need of fault tolerance and its applications.
To understand the concepts of
reliability and availability.
To understand detection/correction techniques and software reliability model.
UNIT I
Motivation of fault tolerance in arithmetic systems, Fault and error models in VLSI
arithmetic
units, Reliability and fault tolerance definit
ions, Reliability and availability
modeling.
(6
)
Estimation of the reliability and availability of fault tolerant systems, Fault
diagnosis, Fault
tolerance measurement.
(3
)
Fault tolerance strategies: detection,
correction, localization, reconfiguration, Error
recovery,
Error detecting and correcting codes.
(
7
)
UNIT II
Detection/correction techniques: modular redundancy, time redundancy (e.g.,
RESO, RERO,
REDWC, RETWV, REX0), datacoding (e.g., AN
codes, residue codes,
GAN codes, RBR codes, Berger codes, residue number systems), algorithm

based
techniques, Reconfiguration techniques.
(8
)
Applications to arithmetic units and systems (e.g., convolvers, inner product units,
FFT units,
neural
networks), Application levels: unit, processing element,
subsystem, system. Cost/benefit
analysis Fault

tolerant transaction processing systems;
Fault

tolerant Networks; Redundant disks (RAID).
(8)
UNIT III
Software reliability models,
Software fault

tolerance methods: N

version programming,
recovery blocks, rollback and recovery.
(8)
Architecture and design of fault
—
tolerant computer systems using protective redundancy.
(
8
)
Microelectronics and VLSI Design
Recommended Books
1.
Prad
han, D.K., Fault Tolerant Computer System Design, Prentice Hall (1996).
2.
Johnson, B.W., Design and Analysis of Fault Tolerant Digital Systems,
Addison
Wesley (1989).
3.
Nelson, V.P. and Carroll, B. D., Tutorial: Fault Tolerant Computing,
IE
EE
Computer Society
Press (1990).
4.
Slewiorek, D.P.,
Swarz,
R. S. and Peters AK., Reliable Computer
Systems:
Design and Evaluation, A K Peters (1998) 3
0
ed.
Microelectronics and VLSI Design
ECT 569
MOS DEVICE MODELING
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives:
To refresh semiconductor, quantum mechanics fundamentals.
To understand MOSFET modeling and underlying techniques.
To introduce advanced device technologies.
UNIT I
Semiconductor Fundamentals:
Poisson and Continuity Equations, Recombination,
Equilibrium
carrier concentrations (electron statistics, density of states, effective mass,
bandgap narrowing),
Review of PN and MS diodes.
(7)
Quantum Mechanics Fun
damentals:
Basic Quantum Mechanics, Crystal symmetry and
band structure, 2D/1D density of states, Tunneling.
(4)
Modeling and Simulation of Carrier Transport:
Carrier Scattering (impurity, phonon,
carrier

carrier, remote/interface), Boltz
mann Transport Equation, Drift

diffusion.
(5)
UNIT II
MOS Capacitors:
Modes of operation (accumulation, depletion, strong/weak
inversion),
Capacitance versus voltage, Gated diode, Non

ideal effects (poly depletion,
surface charges),
High field effects (t
unneling, breakdown).
(5)
MOSFET Modeling:
Introduction Interior Layer, MOS Transistor Current, Threshold
Voltage, Temperature Short Channel and Narrow Width Effect, Models for Enhancement,
Depletion Type MOSFET, CMOS Models in SPICE, Long Channel MOSF
ET Devices, Short
Channel MOSFET Devices.
(7)
Parameter Measurement:
General Methods, Specific Bipolar Measurement,
Depletion
Capacitance, Series Resistances, Early Effect, Gummel Plots, MOSFET: Long
and Short Channel Parameters, Statistical Model
ing of Bipolar and MOS Transistors.
(6
)
UNIT III
Advanced Device Technology:
501, SiGe, strained Si, Alternative oxide/gate
materials,
Alternative geometries (raised source/drain, dual gate, vertical, FinFET),
Memory Devices
(DRAM, Flash).
(10
)
Sub

micron and Deep sub

micron Device Modeling
(4
)
Microelectronics and VLSI Design
Recommended Books
1.
Tsividis,
Y.,
Operation and Modeling of the MOS Transistor, Oxford University
Press,(2008) 2
,2d
ed.
2.
Sze, S.M., Physics of Semiconductor Devices
, Wiley (2008).
3.
Muller, R.S., Kamins, TI., and Chan, M., Device Electronics for Integrated
Circuits, John Wiley (2007) 3
rd
ed.
4.
Tour,
Y.
and Ning, T.H., Fundamentals of Modern VLSI Devices,
Cambridge University
Press (2009).
5.
Massobrio, G. and Antognetti, P.
, Semiconductor Device Modeling, McGraw
Hill (1998).
6.
Dieter, K.S., Semiconductor Material and Device Characterization, John Wiley (2006)
3
0
ed.
7.
Tor, A., Fjeldly, T.Y., and Michael, S., Introduction to Device Modeling and
Circuit Simulation, John Wiley
(1998).
Microelectronics and VLSI Design
ECT 570
OPTICAL VLSI
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives:
To provide overview of optical communication.
To
understand working and need of CMOS optical receivers.
To understand challenges to Mixed mode ICs.
UNIT I
Introduction: Optical communication:
An historical overview, Optical fiber versus
copper
wire, Integration of Optical communication systems. Optical
communication link.
(8
)
The CMOS Optical Receiver:
Simple Resistor Optical Receiver, Transimpedance amplifier,
Comparison of transimpedance amplifiers, Multiple

Stages feedback amplifiers, Noise
aspects of
the transimpedance amplifier, Post amplifier.
(8)
UNIT II
Integrated CMOS Optical Receivers:
DC

Coupled 0.8um Digital CMOS 155 Mb/s
Optical
receiver; 240 Mb/s 18 THz Optical receiver with rail to rail output swing; 1 Gb/s
0.7um standard CMOS optical receiver; Performance evaluation.
(9)
Full Integration of a Standard CMOS Optical Transmitter:
LED driver, Integrated
CMOS
optical fiber link, Integrated CMOS photodiodes, Integrated Photodiodes in sub

micron CMOS.
(8)
UNIT III
Electrical Interference in Mix
ed

Mode Integrated Circuits:
Aspects of the
electrical
Interference Problem, Switching Noise Generation Reduction, On chip Power
supply Decoupling,
Noise propagation limitation in integrated circuits, The Generalized
use of differential structures
in integ
rated circuits, Practical implementation.
(1
5
)
Microelectronics and VLSI Design
Recommended Books
1.
Ingels, M. and Steyaert, M., Integrated CMOS Circuits for Optical
Communications, Springer (2008).
2.
Radovanoic, S., Anne

Johan, Annema and Bram, Nauta, High Speed
Photodiodes in
Standard CMOS Technology, Springer (2006).
3.
Muller, P., CMOS Multi

channel Single

Chip Receivers for Multi

Gigabit Optical
Data Communications, Springer(2007)
.
Microelectronics and VLSI Design
ECT 571
DIGITAL VLSI DESIGN
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives:
To introduce MOSFET modeling.
To facilitate the student with concepts of dynamic logic circuits.
To study the effect of technology
scaling on CMOS logic styles.
UNIT I
Physics and Modeling of MOSFETs:
Basic MOSFET Characteristics
—
Threshold Voltage,
Body Bias
concept, Current

Voltage Characteristics
—
Square

Law Model, MOSFET Modeling
—
Drain

Source.
Resistance, MOSFET Capacitances,
Geometric Scaling Theory
—
Full

Voltage
Scaling, Constant

Voltage
Scaling.
(5)
Fabrication and Layout of CMOS Integrated
Circuits: Overview of Integrated Circuit
Processing
—
Oxidation, Photolithography, Self

Aligned MOSFET, Isolation and Wells
—
LOCOS, Trench
Isolation, CMOS Process flow, Mask design and Layout
—
MOSFET
Dimensions, Design Rules,
Latch

up.
(5)
CMOS Inverter:
Basic Circuit and DC Operation
—
DC Characteristics, Noise Margins, Layout
considerations, Inverter Switching Characteristics
—
Switching Inte
rvals, High

to

Low time, Low
to

High
time, Maximum Switching Frequency, Transient Effects on the VTC, RC Delay
Modeling, Elmore
Delay, Output Capacitance, Inverter Design
—
DC Design, Transient Design, Driving Large Capacitive Loads
(6)
UNIT II
Switching Properties of
MOSFETs:
nMOSFET/ pMOSFET Pass Transistors, Transmission
Gate
Characteristics, MOSFET Switch Logic, TG

based Switch Logic, D

type Flip

Flop. (5)
Static CMOS Logic Elements:
Complex Logic Functions, CMOS NAND Gate, CMOS NOR
Gate,
Complex Logic Gates, Exclusive OR and Equivalence Gates, Adder Circuits, Pseudo
nMOS Logic
Oates, Schmitt Trigger Circuits, SR and D

type Latch, CMOS SRAM Cell, Tri

state O
utput Circuits.
(6)
Power Dissipation in CMOS
Digital Circuits
: Dynamic Power Dissipation
—
Switching Power
Dissipation,
Short Circuit Power Dissipation, Glitching Power Dissipation, Static Power
Dissipation
—
Diode
Leakage Current, Subthreshold
Leakage Current.
(5)
UNIT III
Dynamic Logic Circuit Concepts and CMOS Dynamic Logic Families
: Charge Leakage,
Charge
Sharing, Dynamic RAM Cell, Bootstrapping, Clocked

CMOS, Pre

Charge/ Evaluate
Logic, Domino
Logic, Multiple

Output Domino Logic, N
ORA Logic, Single

Phase Logic.
(5)
Effects of
Technology Scaling
on CMOS Logic Styles:
Trends and Limitations of CMOS
Technology Scaling
—
MOSFET Scaling Trends, Challenges of MOSFET Scaling
—
Short

Channel
Effects, Subthreshold Leakage Currents, D
ielectric Breakdown, Hot Carrier effects, Soft Errors, Velocity
Saturation and Mobility Degradation, DIBL, Scaling down V
dd
/V
ih
ratio.
(6)
CMOS Differential
Logic Styles
: Dual

Rail Logic, CVSL, CPL, DPL, DCVS, MCML.
Issues in Chip Design:
ESD Protect
ion, On

Chip Interconnects
—
Line Parasitics, Modeling of
the
Interconnect Line, Clock Distribution, Input

Output circuits.
(5)
Microelectronics and VLSI Design
Recommended Books
1.
Kang, S. and Labelici, Y., CMOS Digital Integrated Circuits
–
Analysis and Design,
Tata
McGraw Hill(2008)3
rd
ed.
Weste, N.H.E and Eshraghian., K.,CMOS VLSI
Design : A Circuits and Systems Perspertive, Addision Wesley(1998)2
nd
ed.
2.
Weste, N.H.E and Eshraghian., K.,CMOS VLSI Design : A Circuits and Systems
Perspertive, Addision Wesley(1998)2
nd
ed.
3.
Rabaey, J.M Chanderakasen, A.P and Nikolic, B., Digital Integrated Circuits
–
A
Design Perspective, Pearson Education(2007) 2
nd
ed.
4.
Aker, R.J., H.W and Boyce, D.E.,CMOS Circuit Design, Layout and Simulation,
Wiley
–
IEEE Press (2004)2
nd
ed.
5.
Weste,
N.H.E., Harris, D. and Banerjee, A., CMOS VLSI Design, Dorling
Kindersley( 2006) 3
rd
ed.
Microelectronics and VLSI Design
ECT 572
LOW POWER VLSI
DESIGN
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives:
To introduce the
concept of Low power microelectronics.
To introduce Low voltage technologies and circuits.
To understand circuit and logic styles.
UNIT I
Low' Power Microelectronics:
Retrospect and Prospect, Fundamentals of power dissipation in
microelectronic devices,
Estimation of power dissipation due to switching, short circuit, sub
threshold
leakage, and diode leakage currents.
(16)
UNIT II
CMOS Scaling:
Scaling for High Performance and Low

Power,
Low Voltage Technologies and Circuits:
Threshold Voltage Scaling and Control, Multiple
Threshold
CMOS (MTCMOS), Substrate Bias Controlled Variable Threshold CMOS, Testing
Issues: Design and test
of low

Voltage CMOS circuits.
(16)
UNIT III
Circuit and Logic Styles:
Power

conscious logic Styles, Adiabatic Logic Circuits. Power
Analysis
and optimization: Power Analysis Techniques, Power Optimization Techniques, Energy
recovery techniques,
Software power estimation and optimization Low

Power Memory Circuits
and architec
tures.
Power Conscious High

Level Synthesis. Silicon

On

Insulator Based Technologies.
(16)
Recommended Books
1.
Roy, K. and Prasad, Sharat C., Low Power CMOS VLSI: Circuit Design, John
Wiley (2009).
2.
Chandrakasan, A.P. and Broderson, R.W., Low Power Digit
al CMOS Design,
Kluwer (1995).
3.
Rabaey, J.M. and Pedram, M., Low Power Design Methodologies, Springer
(1996).
4.
Yea, K.S. and Roy K., Low Voltage, Low Power VLSI Subsystems, McGraw Hill
(2004).
5.
Sanchez

Sinencio, E. and Andreou, A. G., Low

Voltage/Low

Power In
tegrated
Circuits and Systems: Low

Voltage Mixed

Signal Circuits, IEEE Press (1999).
6.
Bellaouar, A. and Elmasry, MI., Low

Power Digital VLSI Design: Circuits and
Systems, Kluwer
(1995).
Microelectronics and VLSI Design
ELECTIVE VI
Microelectronics and VLSI Design
ECT 606
RF IC DESIGN
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives:
To understand concepts of RF design and Communication.
To
appreciate various multiple access techniques and wireless standards.
To facilitate the student with knowledge of different types of oscillators, power
amplifiers and frequency synthesizers.
UNIT I
Introduction to RF and Wireless Technology:
Complexity comparison, Design bottleneck,
Applications, Analog and Digital systems and choice of technology.
(2)
Basic Concepts in RF Design:
Non linearity and time variance

Effects of non
lineari
ty and
cascaded nonlinear stages, Inter symbol interference, Random Processes and
noise, Sensitivity
and dynamic range, Passive Impedance Transformation.
(3)
Modulation and Detection: General considerations, Analog Modulation:
Amplitude
modu
lation, phase and frequency modulation, Digital modulation

basic
concepts, binary
modulation and quadrature modulation, Power efficiency of modulation
schemes

constant and variable envelope signals and spectral regrowth, Noncoherent
detection.
(7)
UNIT II
Multiple Access Techniques and Wireless Standards:
Multiple RF communications,
Multiple
Access Techniques Time and frequency division duplexing. Frequency division
multiple access,
Time division multiple access and Code division multiple a
ccess. Wireless
Standards

Advanced
mobile phone services, North American Digital Standard,
Global system for mobile
communi cat ion, Qual comm CDMA and Di git al
European Cordl ess Tel ephone.
(6)
Transceiver Architectures:
General consideration,
Receiver Architectures, Heterodyne
and
Homodyne receivers, Image reject receivers, Digital IF receivers and Subsampling
receivers; Transmitter Architectures, Direct conversion transmitters and two step transmitters,
Transceiver performance tests.
(4)
Low Noise Amplifiers and Mixers:
Low noise amplifiers

General considerations,
Input
matching, Bipolar LNAs and CMOS LNAs; Down conversion mixers

General
considerations, Bipolar mixers, CMOS mixers and noise in mixers, Cascaded stages.
(4)
Microelectronics and VLSI Design
UNIT III
Oscillators:
General considerations, Basic LC Oscillator Topologies, Voltage

Controlled
Oscillators, Phase Noise

Effect of phase noise in RF communications, Q of
an oscillator, Phase
noise mechanisms, noise power trade

off, effect o
f frequency
division and multiplication on
phase
.
noise, oscillator pulling and pushing, Bipolar and
CMOS LC Oscillators, Negative Gn,
oscillators and interpolative oscillators, Monolithic
inductors, Resonator

less VC0s, Quadrature
Signal Generations, RC

C
R network,
Havens technique, frequency division, Single sideband
generation.
(9)
Frequency Synthesizers:
General considerations, Phase lock loops

basic concepts, basic
PLL,
Charge pump PLLs, Types I and II PLLs, noise in PLLs, phase noise at
input,
phase noise of
VCO and frequency multiplication, RF synthesizer architectures,
Integer N architecture,
fractional N architecture, Dual loop architecture and direct digital
synthesis, Frequency dividers
divide by two circuits and dual modulus divide
rs.
(7)
Power Amplifiers:
General considerations, linear and nonlinear PAs, Classification of power
Amplifiers, Class A, B, and C PAs, High efficiency power amplifiers, Large signal
impedance
matching, Linearization techniCiues, feedforward, feedback, e
nvelope
elimination and restoration and LINC, Design examples.
(6)
Recommended Books
1.
Razavi, B., RF Microelectronics, John Wiley (2008).
2.
Lee, T.H., The Design of CMOS Radio

Frequency Integrated Circuits,
Cambridge University Press (2003) 2
,0
ed.
3.
Tsividis, Y.P., Mixed Analog and Digital VLSI Devices and Technology, World
Scientific (2002).
4.
Baker,
R.
Jacob, Li, H.W. and Boyce, D.E., CMOS Circuit Design, Layout and
Simulation, Prentice

Hall of India(2004) 2
nd
ed.
Microelectronics and VLSI Design
ECT 607
HIGH SPEED VLSI DESIGN
L T C
4 0 4
Max Marks: 60
Contact Hours : 48
Course Objectives:
To understand the concept of the method of logic effort.
To appreciate the differences between different Logic
styles.
To facilitate the student with various interfacing techniques.
UNIT I
Introduction of High Speed VLSI Circuits Design.
(1)
Back

End

Of

Line Variability Considerations:
Ideal and non ideal interconnect
issues,
Dielectric
Thickness and Permittivity.
(3)
The Method of Logical Effort:
Delay in a logic gate, Multi

stage logic networks,
Choosing the
best number of stages.
(3)
Deriving the Method of Logical Effort:
Model of a logic, De
lay in a logic gate,
Minimizing
delay along a path, Choosing the length of a path, Using the wrong number of
stages, Using the
wrong gate size.
(
9
)
UNIT II
Non

Clocked Logic Styles:
Static CMOS, DCVS Logic, Non

Clocked Pass Gate
Families.
(3
)
Clocked Logic Styles:
Single

Rail Domino Logic Styles, Dual

Rail Domino Structures,
Latched Domino Structures, Clocked Pass Gate Logic.
(4)
Circuit Design Margining:
Process Induced Variations, Design Induced Variations,
Appl
ication Induced Variations, Noise.
(3)
Latching Strategies:
Basic Latch Design, Latching single

ended logic, Latching
Differential
Logic, Race Free Latches for Pre

charged Logic Asynchronous Latch
Techniques.
(6
)
UNI
T III
Interface Techniques:
Signaling Standards, Chip

to

Chip Communication Networks,
ESD
Protection.
(7
)
Clocking Styles:
Clock Jitter, Clock Skew, Clock Generation, Clock Distribution,
Asynchronous Clocking Techniques.
(7
)
Skew
Tolerant Design.
(
2
)
Microelectronics and VLSI Design
Recommended Books:
1.
Bernstein, K., Carrig, KM., Durham, Hansen, C.M., Hogenmiller, E. I., Nowak
and Rohrer, N.J., High Speed CMOS Design Styles, Kluwer (2007).
2.
Sutherland, I.E., Sproul', B.F. and Harris, DL., Logical Effort:
Designing Pat
CMOS
Circuits, Elsevier/MK (1999).
3.
Jho
nson, H.W., High Speed Digital Design, Prentice Hall PTR (2008).
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