ABSTRACT - kpadhnan

ukrainianlegalElectronics - Devices

Nov 2, 2013 (3 years and 9 months ago)

140 views

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


1


VAST
















INTRODUCTION












Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


2


VAST



1. INTRODUCTION

1.1
Introduction


The conventional system of
marking attendance

is
manually

entering
attendance in the register

and entering the data to the campus automation software.
This require lots of time.

Our system proposes automated attendance marking system.



This system consists of an attendance entering device (transmitter) and a main server
(receiver). Using th
is method the data are entered directly into the
automation
software
. The system is simple, easy to operate and the data is more secure.






The attendance entering device consists of microcontroller, 4x4 keypad, LCD
display and ZIGBEE module. Using
the keypad the user can enter the attendance. The
entered data are transmitted to the main server using ZIGBEE module. The ZIGBEE
is a transceiver, in the transmitter section it can be used as a transmitter.

The ZIGBEE
is in accordance with IEEE 802.15.4 a
nd it uses ISM band.


In the main server
ZIGBEE can be used as the receiver, which receives the data send by the transmitter.
This data is TTL logic which is converted to RS232 logic and interfaced to
automation software.

We developed two transmitters f
or taking attendance from two classes and developed
the interfacing software using Visual Basic 6.



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


3


VAST
















BLOCK DIAGRAMS




Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


4


VAST



2. BLOCK DIAGRAMS




The attendance automation system has mainly two sections, a transmitter section
&

a receiver section. The block diagrams of each section are given below:



2.1 Transmitter Section





















F




LCD DISPLAY



PIC 16F877
A

MICRO

CONTROLLER




4*4

KEY PAD




ZIGBEE

MODULE


Fig.2.1 Block of Transmitter

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


5


VAST





2.2 Receiver Section


























ZIGBEE

MODULE




COMPUTER

INTERFACE




COMPUTER


Fig.2.2 Block of Receiver

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


6


VAST
















BLOCK DIAGRAM DESCRIPTION



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


7


VAST



3. BLOCK DIAGRAM DESCRIPTION




Here we discuss the blocks of transmitter & receiver sections of attendance
automation system. The transmitter will act as the attendance entering system & the
receiver will be the main server. The transmitter is given to the staffs of the college
who tak
e the attendance & the receiver is the department main server. We developed
two transmitters & one receiver.




3.1 Attendance Entering System




The transmitter section will act as the attendance entering system. The block
diagram of the
transmitter section is shown in chapter 2 (Fig.2.1). This section
contains peripheral interface controller (PIC) 16F877A, 4*4 matrix keypad, LCD
display & ZIBEE module. The 16F877A micro controller is the heart of transmitter
section, which controls the da
ta transfer. Here we use wireless transmission system
for data transfer. The 4*4 keypad will act as the input device to the controller & the
LCD display & ZIGBEE module will act as the output devices to the microcontroller.


The 4*4 keypad section is
provided for entering the attendance; user can enter the
attendance by pressing the keys. The entered data will be displayed on the LCD
screen provided in the transmitter section. This will help for the verification of the
entered data. The verified data w
ill be transmitted to the main server through the
ZIGBEE module. ZIGBEE is a wireless transmission system also it is a low cost low
power mesh networking system based on IEEE 802.15.4. Here the ZIGBEE module
will act as the transmitter. The entire system w
ill be controlled by PIC 16F877A.



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


8


VAST




3.2 Main Server





The
receiver section will act as the main server. The block diagram of the receiver
section is shown in chapter 2 (Fig.2.2). This section contains the ZIGBEE module,
computer interface & compu
ter. The receiver section is present in each department of
the college.


Here the ZIGBEE module will act as the receiver, which receives the transmitted
data from the attendance entering system. These data are giver to the computer of
each department

through a computer interface. The need of the computer interface is
to convert the TTL logic into RS
-
232 logic. Thus the data will be entered into the
computer of each department & links to campus automation software.



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


9


VAST
















CIRCUIT
DESCRIPTION



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


10


VAST



4. CIRCUIT DESCRIPTION



The circuit diagrams of the power supply, attendance entering system
(transmitter) & the main server (receiver) are given below.




4.1 Power Supply Circuitry




The
circuitry of the power supply
is shown below:















Fig.4.1

Supply Circuitry






The
circuit consists of a transformer, bridge rectifier, capacitive filter &
regulator IC. The transformer steps down the ac voltage from 230V to 12V. The
bridged rectifier i
s used for the conversion of ac voltage into pulsating dc voltage. The
ripples in the rectifier output are

eliminated

by the use of capacitive filter. To get
constant dc voltage we use the regulator.




Voltage regulators comprise a class of widely us
ed IC’s. Regulator IC units
contains the circuitry for reference source, comparator amplifier, controlled device,
and overload protection all in single IC. IC units provide regulation of a fixed +
voltage, a fixed negative voltage, or an adjustably set vol
tage. The regulators can be
selected for operation with load currents of 100’s of m A to 10’s of a, corresponding

to current ratings from mill watts to 10’s of watts. A fixed 3 terminal voltage regulator

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


11


VAST



has an unregulated dc input voltage vi, applied to one i/p terminal, a regulated dc o/p

voltage, v0, from a second terminal, with 3
rd

terminal connected to ground. The series
78 regulators provide fixed + regulator voltages from 5
-
24 V
.
Here we use IC 780
5 to
get 5V dc output.



For PIC, LCD & PC Inter phase we require 5V & for ZIGBEE module we require
3.3 V. IC LM 317 is used for adjusting the regulator output voltage.



4.2

Transmitter Circuitry




The

circuitry of the transmitter section is shown below:





Fig. 4.2

Transmitter Circuitry




As in every embedded system, here also microcontroller is the
heart of the project
.

PIC 16F877A microcontroller controls the entire system.

The microcontroller has

mainly
five

ports A, B, C, D
, & E. E
ach port is
controlled by the TRIS register, which

can be used either as input port or as output port, this can

be

done through the
program. The transmitter section contains the keypad section,
LCD display &

the

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


12


VAST



ZIGBEE module,

w
here key pad act as
the input device and

LCD display,

ZIGBEE
module are acting as the
output

device
.



The 4*4 matrix keypad is interfaced to
the port B of the PIC 16F877A as shown in
fig 4.2. Each column of the keypa
d section is scanned
by the program when a key is
pressed
.

The output from the PIC is given to the rows of the key pad & the outputs
from the columns of the key pad are given as input to the PIC. Thus the TRIS B
register is set such that the

lower bits are

all 0s (input) and

upper bits are all 1s
(outputs). Each key is a simple push button with each number having unique paths

from the PIC through the key
pad and back into the PIC micro
controller. A continuous
unique path is created when the key is pressed. E
ach key pressing having unique
value corresponds to the key press.

The
details of this interface are

given in chapter 5
(5.2).




The LCD display is connected to port D of the PIC.
This interface is shown in fig
4.2. Pin 1 of the LCD is connected to gro
und & pin 2 is connected to supply (5V). A
potentiometer is connected to pin 3 for contrast adjustment. Pin 4
is the register select;
its value is made 1 by the program to display the data. Pins 11, 12, 13 & 14 are used
for data transfer and are connected
to RD4, RD5, RD6 & RD7 respectively of the
PIC. That is here four bits are transmitted at a time. For back light we connect pin 15
to supply & pin 16 to ground.
Since t
he LCD is an output device, the

upper part of
TRIS D register is set to 0 by the program
.

The details of this interface is given is
chapter 5 (5.3).






The ZIGBEE interface is another part of the transmitter section.
The pin 3 (data
in) of ZIGBEE module is

connected to

the USART

transmission (TX
-
25) pin of port
C in PIC. This wireless tran
smission follows USART protocols and is according to
IEEE 802.15.4.

ZIGBEE is a transceiver, in the transmitter section it is used as the
transmitter. The receiver address of this ZIGBEE module is set as the address of the
ZIGBEE module in the main server,

so that data is send to this receiver only.
It is
a
low power, low cost wireless mesh networking standard and it uses the ISM band for
it
s

transmission. The
details of this interface are

given in chapter5 (5.4).



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


13


VAST








The PIC requires
oscillator for
clock generation, for this a crystal oscillator

16
MHZ

is connected between pin 13 & 14. Parasitic capacitor of 33pf is used to
increase the stability of the oscillator.






In pin 1 of the PIC a switch is connected for resetting the registers.
Pin

1 is

the
master clear. During normal operation its value is high, when the switch is pr
essed
all

the registers of the PIC is

clear
ed
.







The supply to the PIC
(5V) is given by the supply circuitry given in fig 4.1. The
supply is
given to

pin 11of the PIC. T
he supply to ZIGBEE module (3.3V) is given by

LM317, which is given to pin 1 of ZIGBEE.












Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


14


VAST




4.3

Receiver Circuitry





Fig.4.3

Receiver Circuitry







The receiver
circuitry consists

of ZIGBEE

module, MAX232 and RS232 serial
port.


Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


15


VAST







In the receiver section the ZIGBEE module can be used as receiver. This module
receives the data send by the transmitters. The supply to the ZIGBEE module (3.3V)
is given by the supply circuitry in fig 4.1 with LM311.






To interface with the computer
we have to convert the TTL logic into RS232 logic
,
for

this purpose we use the IC MAX232.

MAX232

is

a

dual

driver/receiver

that

includes

a

capacitive

voltage

generator
.

The

drivers

(T
1

&

T
2
),

also

called

transmitters
,

convert

the

TTL/CMOS

logic

input

level

into

RS232

level.

The

transmit
ter

(
pin

10
-
T2

in
)

take

input

from

ZIGBEE’s

data

out

pin

(pin

2

of

ZIGBEE
)

and

send

the

output

to

RS232’s

receiver

at

pin

7

(T2

out)

of

MAX232
.

We

use

four

capacitors,

two

for

doubling

the

voltage

and

other

two

for

inverting

the

voltage.

The

capacitors

are

connected

between

pin

1

and

pin

3,

pin

4

and

pin5,

pin

2

and

VCC,

and

pin

6

and

GND.

The

details

of

MAX

232

are

given

in

chapter

6

(6.2).




The

transmitter

output

(T2

out)

from

MAX232

(RS232

logic)

is

connected

to

pin

2

(
receive

data)

of

RS232

port.

Thus

the

data

received

are

given

to

PC.

The

pin

5

of

RS232

port

is

connected

to

ground.



















Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


16


VAST
















TRANSMITTER SECTION




Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


17


VAST



5. TRANSMITTER SECTION




The transmitter part of the attendance automation system contains the following
parts:



Peripheral Interface Controller (PIC)



4*4 matrix keypad



LCD display



ZIGBEE module



Crystal oscillator for clock generation


The circuitry of the transmitter sectio
n

is shown in chapter 4 (Fig.4.2
). Each part
of the transmitter section is explained below:



5
.1 Peripheral Interface Controller (PIC)




Peripheral Interface Controllers (PIC) is one of the advanced microcontrollers
developed by microchip technologies. These microcontrollers are widely used in
modern electronics applications.


A PIC controller integrates all type of advanced
interfacing por
ts and memory modules. These controllers are more advanced than
normal microcontroller like INTEL 8051. The first PIC chip was announced in 1975
(PIC1650). As like normal microcontroller, the


PIC


chip also combines
a

microprocessor unit called CPU and
is integrated with various types of memory
modules (RAM, ROM, EEPROM, etc), I/O ports, timers/counters, communication
ports, etc.





Fig.5
.1

PIC 16F877A

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


18


VAST




PIC 16F877 is one of the most advanced microcontroller from Microchip.

PICs
are popular with
both industrial developers and hobbyists alike due to their low cost,
wide availability, large user base, extensive collection of application notes,
availability of low cost or free development tools, and serial programming (and re
-
programming with flash m
emory) capability. The figure of a PIC1
6F877 chip is
shown

(Fig.5
.1)
.



All PIC microcontroller family uses Harvard architecture. This architecture has the
program and data accessed from separate memories so the device has a program
memory bus and a da
ta memory bus (more than 8 lines in a normal bus). This
improves the bandwidth (data throughput) over traditional von Neumann architecture
where program and data are fetched from the same memory (accesses over the same
bus). Separating program and data mem
ory further allows instructions to be sized
differently than the 8
-
bit wide data word. The PIC has number of advanced features,

the important features of PIC16F877 series is given below.



5
.1.1
General Features




It is a high performance RISC CPU.



Only 35

simple word instructions.



All single cycle instructions except for program branches which are two
cycles.



Operating speed: clock input (200MHz), instruction cycle (200nS).



Up to 368×8bit of RAM (data memory), 256×8 of EEPROM (data memory),
and 8k×14 of
flash memory.



Pin out compatible to PIC 16C74B, PIC 16C76, PIC 16C77.



Eight level deep hardware stack.



Interrupt capability (up to 14 sources).



Different types of addressing modes (direct, Indirect, relative addressing
modes).



Power on Reset (POR).



Power
-
U
p Timer (PWRT) and oscillator start
-
up timer.

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


19


VAST





Low power
-

high speed CMOS flash/EEPROM.



Fully static design.



Wide operating voltage range (2.0


5.56)volts.



High sink/source current (25mA).



Commercial, industrial and extended temperature ranges.



Low power
consumption (<0.6mA typical @3v
-
4MHz, 20µA typical @3v
-
32MHz and <1 A typical standby).



5
.1.2
Peripheral Features




Timer 0: 8 bit timer/counter with pre
-
scalar.



Timer 1:16 bit timer/counter with pre
-
scalar.



Timer 2: 8 bit timer/counter with 8 bit period

registers with pre
-
scalar and
post
-
scalar.



Two Capture (16bit/12.5nS), Compare (16 bit/200nS), Pulse Width Modules
(10bit).



10bit multi
-
channel A/D converter



Synchronous Serial Port (SSP) with SPI (master code) and I2C (master/slave).



Universal
Synchronous Asynchronous Receiver Transmitter (USART) with 9
bit addresses detection.



Parallel Slave Port (PSP) 8 bit wide with external RD, WR and CS controls
(40/46pin).



Brown Out circuitry for Brown
-
Out Reset (BOR).



5
.1.3
Key Features




Maximum operat
ing frequency is 20MHz.



Flash program memory (14 bit words), 8KB.



Data memory (bytes) is 368.



EEPROM data memory (bytes) is 256.

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


20


VAST





5 input/output ports.



3 timers.



2 CCP modules.



2 serial communication ports (MSSP, USART).



PSP parallel communication port



10b
it A/D module (8 channels)



5
.1.4
Analog Features




10
-
bit, up to 8
-
channel Analog
-
to
-
Digital Converter (A/D)



Brown
-
out Reset (BOR)



Analog Comparator module with two analog comparators,

p
rogrammable on
-
chip voltage reference (VREF) module,
programmable

input multiplexing
from device inputs and internal voltage reference &
comparator

outputs are
externally accessible
.




5
.1.5
Special Features




100000 times erase/write cycle enhanced memory.



1000000 times erase/write cycle data EEPROM memory.



Self
programmable under software control.



In
-
circuit serial programming and in
-
circuit debugging capability.



Single 5V,DC supply for circuit serial programming



WDT with its own RC oscillator for reliable operation.



Programmable code protection.



Power saving sle
ep modes.



Selectable oscillator options.


Now
we discuss

the important parts of Peripheral Interface Controller



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


21


VAST




5
.1.6 Central Processing Unit (CPU)



The function of CPU in PIC is same as a normal microcontroller CPU. A
PIC CPU consists of several sub units such as instruction decoder, ALU, accumulator,
control unit, etc. The CPU in PIC normally supports Reduced Instruction Set
Computer (
RIS
C) architecture
, a type of microprocessor that focuses on rapid and
efficient processing of a relatively small set of instructions. RISC design is based on
the premise that most of the instructions a computer decodes and executes are simple.
As a result
, RISC architecture limits the number of instructions that are built into the
microcontroller but optimizes each so it can be carried out very rapidly (usually
within a single clock cycle). These RISC structure gives the following advantages.



The RISC stru
cture only has 35 simple instructions as compared to others.



The execution time is same for most of the instructions (except very few
numbers).





The execution time required is very less (5 million instructions/second
a
pproximately).


5
.1.7
Memory Organi
zation of PIC16F877



The memory of a PIC 16F877 chip is divided into 3 sections. They are



Program memory



Data memory and



Data EEPROM


5
.1
.
7
.
1
Program memory


Program memory contains the programs that are written by the user. The
program counter (PC) executes these stored commands one by one. Usually
PIC16F877 devices have a 13 bit wide program counter that is capable of addressing
8K×14 bit program memory space. This memory is primarily used for storing the
programs that are writt
en (burned) to be used by the PIC. These devices also have

8K*14 bits of flash memory that can be electrically erasable /reprogrammed. Each



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


22


VAST



time we write a new program to the controller, we must

delete the old one at that
time.
The
program

memory map an
d stack

is shown in appendix
-
1
.



Program counters (PC) is used to keep the track of the program execution by
holding the address of the current instruction. The counter is automatically
incremented to the next instruction during the current instructi
on execution.




The PIC16F87XA family has an 8
-
level deep x 13
-
bit wide hardware stack. The
stack space is not a part of either program or data space and the stack pointers are not
readable or writable. In the PIC microcontrollers, this is a special b
lock of RAM
memory used only for this purpose
.



5
.1
.
7
.
2 Data Memory




The data memory of PIC16F877 is separated into multiple banks which
contain the general purpose registers (GPR) and special function registers (SPR).
According to
the type of the microcontroller, these banks may vary. The PIC16F877
chip only has four banks (B
ANK 0, BANK 1, BANK 2, and BANK3
). Each bank
holds 128 bytes of addressable memory.

The data memory bank organization is
shown in appendix
-
1.


The bank
ed arrangement is necessary because there are only 7 bits are available
in the instruction word for the addressing of a register, which gives only 128
addresses. The selection of the banks are determined by control bits RP1, RP0 in the
STATUS registe
rs t
og
ether the RP1, RP0 and the specified 7 bits effectively form a 9
bit address. The first 32 locations of Banks 1 and 2, and the first 16 locations of
Banks2 and 3 are reserved for the mapping of the Special Function Registers (SFR’s).







Table 5
.1

Bank Selection


RP1:RP0

BANK

00

0

0
1

1

10

2

11

3

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


23


VAST



A bit of RP1 & RP0 of the STATUS register selects the bank access.






5
.1
.
7
.
3
Data EEPROM and FLASH




The data EEPROM and Flash program memory is readable and writable
during normal

operation (over the full VDD range). This memory is not directly

mapped in the register file space. Instead, it is indirectly addressed through the
Special Function Registers. There are six SFRs used to read and write this memory:



EECON1



EECON2



EEDATA



EEDATH



EEADR



EEADRH



The EEPROM data memory allows single
-
byte read and writes. The Flash
program memory allows single
-
word reads and four
-
word block writes. Program
memory write operations automatically perform an erase
-
before write on blocks of
f
our words. A byte write in data EEPROM memory automatically erases the location
and writes the new data (erase
-
before
-
write). The write time is controlled by an on
-
chip timer. The write/erase voltages are generated by an on
-
chip charge pump, rated
to opera
te over the voltage range of the device for byte or word operations.





5
.1.8 Input/output Ports



PIC16F877 has 5 basic input/output ports. They are usually denoted by PORT A
(R A), PORT B (RB), PORT C (RC), PORT D (RD), and PORT E (RE). These p
orts
are used for input/ output interfacing. In this controller, “PORT A” is only 6 bits wide
(RA
-
0 to RA
-
7), ”PORT B” , “PORT C”,”PORT D” are only 8 bits wide (RB
-
0 to
RB
-
7,RC
-
0 to RC
-
7,RD
-
0 to RD
-
7), ”PORT E” has only 3 bit wide (RE
-
0 to RE
-
7).




Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


24


VAST



PORT
-
A

RA0 to RA5

6 bit wide

PORT
-
B

RB
-
0 to RB
-
7

8 bit wide

PORT
-
C

RC
-
0 to RC
-
7

8 bit wide

PORT
-
D

RD
-
0 to RD
-
7

8 bit wide

PORT
-
E

RE
-
0 to RE
-
2

3 bit wide


Table
5
.2

Ports of PIC




All these ports are bi
-
directional. The direction of the port is controlled by using
TRIS(X) registers (TRIS A used to set the direction of PORT
-
A, TRIS B used to set
the direction for PORT
-
B, etc.). Setting a TRIS(X) bit ‘1’ will set the corresponding

P
ORT(X) bit as input. Clearing a TRIS(X) bit ‘0’ will set the corresponding PORT(X)
bit as output.

(If we want to set PORT A as an input, just set TRIS(A) bit to logical
‘1’ and want to set PORT B as an output, just set the PORT B bits to logical ‘0’.)










5
.1
.
8
.
1 Port A & TRIS A Register





PORTA is a 6
-
bit wide, bidirectional port. The corresponding data direction
register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corres
ponding output driver in a High
-

Impedance mode).
Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin). Reading the PORTA register
reads the status of the pins, whereas
writing to it will write to the port latch. All write
operations are read
-
modify
-
write operations. Therefore, a write to a port implies that
the port pins are
read;

the value is modified and then written to the port data latch. Pin
RA4 is multiplexed with
the Timer0 module clock input to become the RA4/T0CKI
pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open
-
drain output. All
other PORTA pins have TTL input levels and full CMOS output drivers. Other
PORTA pins are multiplexed with analog inputs a
nd the analog VREF input for both
the A/D converters and the comparators. The operation of each pin is selected by
clearing/setting the appropriate control bits in the ADCON1 and/or CMCON
registers.


Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


25


VAST







The TRISA register controls the direction o
f the port pins even when they are
being used as analog inputs. The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs
.





5
.1
.
8
.
2 Port B & TRISB
Register



PORTB is an 8
-
bit wide, bidirectional port. The corresponding data
direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding
PORTB pin an input (i.e., put the corresponding output driver in a High
-
Impedance
mode).

Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output
(i.e., put the contents of the output latch on the selected pin). Three pins of PORTB
are multiplexed with the In
-
Circuit Debugger and Low
-
Voltage Programming
function: RB3/PGM, RB
6/PGC and RB7/PGD. Each of the PORTB pins has a weak
internal pull
-
up. A single control bit can turn on all the pull
-
ups. This is performed by
clearing bit RBPU (OPTION_REG<7>). The weak pull
-
up is automatically turned off
when the port pin is configured a
s an output. The pull
-
ups are disabled on a Power
-
on
Reset. Four of the PORTB pins, RB7:RB4, have an interrupton
-

change feature. Only
pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded fr
om the interrupton
-

change comparison). The
input pins (of RB7:RB4) are compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB
port change interrupt with flag bit RBIF (INTCON<
0>). This interrupt can wake the

device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt
in the following manner: Any read or write of PORTB. This will end the



Mismatch condition.



Clear flag bit RBIF.


A mismatch con
dition will continue to set flag bit RBIF. Reading PORTB will
end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt
-
on
-
change feature is recommended for wake
-
up on key depression operation and
operations where PORTB is only used f
or the interrupt
-
on
-
change feature. Polling of
PORTB is not recommended while using the interrupt
-
on
-
change feature. This

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


26


VAST



interrupt
-
on
-
mismatch feature, together with software configurable pull
-
ups on these
four pins, allow easy interface to a keypad and

make it possible for wake
-
up on key
depression.



5
.1.8.3 Port C & TRIS C Register




PORTC is an 8
-
bit wide, bidirectional port. The corresponding data direction
register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding
PORTC pin
an input (i.e., put the corresponding output driver in

a High
-
Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin). PORTC is multiplexed with
several peripheral functions. PORTC pins have Schmitt Trigger input buffers. When
the I2C module is enabled, the

PORTC<4:3>

pins can be configured with normal I2C
levels, or with SMBus levels, by using the CKE bit (SSPSTAT<6>).





When enabling p
eripheral functions, care should be taken in defining


TRIS

bits for each PORTC pin. Some

peripherals override the TRIS bit to make a
pin

an
output, while other peripherals override the TRIS bit to

make a pin an input. Since the
TRIS bit override is in
effect while the peripheral is enabled, read
-
modify write

instructions (BSF, BCF, XORWF) with TRISC as the destination, should be avoided.
The user should refer

to the corresponding peripheral section for the correct TRIS bit
settings.





5
.1.8.4 Por
t D & TRIS D Register



PORTD is an 8
-
bit port with Schmitt Trigger input buffers. Each pin is
individually configurable as an input

or output. PORTD can be configured as an 8
-
bit
wide microprocessor port (Parallel Slave Port) by setting

control bit, PSPMODE
(TRISE<4>). In this mode, the input buffers are TTL.





Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


27


VAST





5
.1.8.5 Port E & TRIS E Register




PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7)
which are individually configurable as inputs or outputs. These
pins have Schmitt
Trigger input buffers. The PORTE pins become the I/O control inputs for the

microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user
must make certain that the TRISE<2:0> bits are set and that the pins are configured

as
digital inputs. Also, ensure that ADCON1 is configured for digital I/O. In this mode,
the input buffers are TTL. Register 4
-
1 shows the TRISE register which also controls
the Parallel Slave Port operation. PORTE pins are multiplexed with analog inputs.

When selected for analog input, these pins will read as ‘0’s. TRISE controls the
direction of the RE pins, even when they are being used as analog inputs. The user
must make sure to keep the pins configured as inputs when using them as analog
inputs.




5
.1.9 USART



The Universal Synchronous Asynchronous Receiver Transmitter (USART)
module is one of the two serial I/O modules. (USART is also known as a Serial
Communications Interface or SCI).

These ports are used for the transmission (TX)

and reception (RX) of data. These transmissions possible with help of various digital
data transceiver modules like RF, IR, Bluetooth, ZIGBEE etc. This is the one of the
simplest way to communicate the PIC chip with other devices.

The USART can be
configu
red as a full
-
duplex asynchronous system that can communicate with
peripheral devices, such as CRT terminals and personal computers, or

it can be
configured as a half
-
duplex synchronous system that can communicate with
peripheral devices, such as A/D or D/
A integrated circuits, serial EEPROMs, etc.

The USART can be configured in the following modes:



Asynchronous (full
-
duplex)



Synchronous


Master (half
-
duplex)



Synchronous


Slave (half
-
duplex)




Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


28


VAST





Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be
set in order to configure
pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.

The parameters for serial communication are



Data rate (Baud rate in bps)



Data size (packet size)



Start bit (if any)



Stop bit (if any)



Par
ity bit (if any)


PIC 16F877A
have no start bit, one stop bit & no parity bit. Therefore the transmitted
or received information is 9
-
bit in size, where 8
-
bit is data & one bit is stop bit.

The
USART module also has a multi
-
processor communication capabili
ty using 9
-
bit
address detection.



5
.1.10 Pin Diagram of PIC 16F877A



The 40 pin PDIP pin
-

out of PIC 16F877A is shown below:



Fig.5
.2

Pin Out of PIC

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


29


VAST




Some pins for these I/O ports are multiplexed with an alternate function for the
peripheral features on the device.

These are given in appendix
-
2
.



5
.1.11 Master Clear



PIC16F87XA devices have a noise filter in the MCLR Reset path. The filter will
detect and ignore small pulses.

Voltages applied to the pin that exceed its
specification can result in both Resets and current consumption outside of device
specification during the Reset event. For this reason, Microchip recommends that the
MCLR pin no longer be tied directly to VDD. The use of a
n RCR network, as shown
in Fig.5.
3

is suggested.

During normal operation this pin should be high. When reset it
is low, during reset,

the following conditions will occur
:



Queue will clear



All registers will clear



IP points to the first location of memory



RAM will clear


Fig
.5
.3

Master Clear



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


30


VAST




5
.1.12 Limitations of PIC Architecture




Peripheral Interface Controller has only one accumulator.



Small instruction set.



Register banking switch required to access RAM of other devices.



Operations and registers are not orthogonal.



Progra
m memory is not accessible.



The PIC requires external clock generator. We use crystal oscillator for clock
generation.



5
.1.13
Advantages of PIC Controlled System




Reliability:


The PIC controlled system often resides machines that are expected to run
continuously for many years without any error and in some cases recover by
themselves if an error occurs(with help of supporting firmware).



Performance:


Many of the PIC based embedded system use a simple pipelined RISC processor
for computation and most of them provide on
-
chip SRAM for data storage to improve
the performance.




Power consumption:


A PIC controlled system operates with minima
l power consumption without
sacrificing performance. Power consumption can be reduced by independently and
dynamically controlling multiple power platforms.




Memory:


Most of the PIC based systems are memory expandable and will help in easily
adding

more and more memory according to the usage and type of application. In
small applications the inbuilt memory can be used.










Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


31


VAST





5
.2 Matrix Key pad





In this project we use 4*4 matrix key pad. The metrics key pad use a matrix
with the ro
ws and columns made up of 16 push button switches. When a key is
pressed, a one column line makes contact with a row line and completes a circuit.
Thus matrix method was used in order to identify a key through pin coordination. In
the 4x4matrix keypad, eve
ry key is
an

open push button switch. Thus when any of the
switches pressed, the input is read as digital signal into the PIC micro controller. Each
key is assigned to the micro controller inputs. Then keypad controller program detects
this closed circuit
and identifies it as a key press and then respond according to the
key press.




Consider about the Metrics key pad consist of (4×4) 16 keys. Each key has a
unique grid location, much like points on a graph
.



Fig.5
.4

Keypad Matrix





Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


32


VAST




Here R0, R1, R2 & R3 are rows & C0, C1, C2 & C3 are columns. This key pad
matrix is interfaced to PIC 16F877A to Port B. The Key’s in the Metrics key pad and
their corresponding pins of the PIC16F877A microcon
troller are given in the


table 5
.3
.

Ke
y’s

in the

Key pad

Pins in microcontroller

Column
0

PORT B,4 (RB4)

Column
1

PORT B,5 (RB5)

Column
2

PORT B,6 (RB6)

Column
3

PORT B,7 (RB7)

Row
0

PORT B,0 (RB0)

Row
1

PORT B,1 (RB1)

Row
2

PORT B,2 (RB2)

Row
3

PORT B,3 (RB3)


Table 5
.3

Connection of Keypad to PIC




The output from the PIC is given to the rows of the key pad & the outputs from
the columns of the key pad are given as input to the PIC. Thus the TRIS B register is
set such that the lower bits are all 0s (input) &
upper bits are all 1s (outputs). Each
key is a simple push button with each number having unique paths from the PIC
through the keypad and back into the PIC micro controller. A continuous unique path
is created when the key is pressed. Each key pressing ha
ving unique value
corresponds to the key press.




When no key is pressed, then all column outputs are high (1
111), it is clear from
the Fig.5.4
. Now we made the row input as zero one by one by software & the
corresponding column outputs are enumerated

when each key is pressed. Now made
the first row (R0) as zero by software, when the first key in the first row is pressed
then the column output C0 is zero, now the column output is 0111 (7), this is the
output corresponding to the first key in the first

row. Similarly the output
corresponding to the second key in the first row is 1011(B), for the third key in the
first row the output will be 1101 (D) & the output corresponding to the fourth key in
the first is 1110 (F). Now made the remaining rows (R1, R
2 & R3) as zero one by one
the output corresponding to the keys of rows will be the same as that of the first row.
The programming for keyboard interface was done in this manner.

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


33


VAST





That is in order to detect key presses; the keyboard controller will sca
n all rows,
activating each one by one. When a row is activated, the controller search for detect
which columns are “activated”.





5
.3 LCD Display




Liquid crystal display

(
LCD
) is an electronically
-
modulated optical device
shaped into a thin
, flat panel made up of any number of color or monochrome pixels
filled with liquid crystals and arrayed in front of a light source (backlight) or reflector.
It is often utilized in battery
-
powered electronic devices because it uses very small
amounts of e
lectric power. Each pixel of an LCD typically consists of a layer of
molecules aligned between two transparent electrodes, and two polarizing filters, the
axes of transmission of which are (in most of the cases) perpendicular to each other.
With no actual
liquid crystal between the polarizing filters, light passing through the
first filter would be blocked by the second (crossed) polarizer.



The surfaces of the electrodes that are in contact with the liquid crystal material
are treated so as to alig
n the liquid crystal molecules in a particular direction. This
treatment typically consists of a thin polymer layer that is unidirectional rubbed using,
for example, a cloth. The direction of the liquid crystal alignment is then defined by
the direction of

rubbing. Electrodes are made of a transparent conductor called Indium
Tin Oxide (ITO).






An LCD is a small low cost display. It is easy to interface with a micro
-
controller
because of an embedded controller (the black blob on the back of the board).

This
controller is standard across many displays (HD 44780) which means many micro
-
controllers (including the Arduino) have libraries that make displaying messages as
easy as a single line of code. An

HD44780 Character LCD

is a

de facto

industry
standard

Liquid Crystal Display (LCD)
display device designed for interfacing with

embedded systems.
These screens come in a variety of configurations including 8x1,
which is one row of eight characters, 16x2, and 20x4. The most commonly
manufactured configuration

is 40x4 characters, which requires two individually


Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


34


VAST



addressable HD44780 controllers with expansion chips as the HD44780 can

only
address up to 80 characters
. I
n this project we use 16x2 LCD display.



These LCD screens are limited to text only and

are often used in

copiers
,

fax
machines
,

laser printers
, industrial test equipment, networking equipment such
as

routers

and

storage devices
.

Character LCDs can come with or without

backlights
,
which may be

LED
,

fluorescent
, or

electroluminescent
.

Charact
er LCDs use a
standard 14
-
pin interface and those with backlights have 16 pins.



5
.3.1 Font



The character generator ROM contains 208 characters in a 5x8 dot matrix, and
32 characters in a 5x10 dot matrix. There is a Japanese version of the ROM
which
includes

kana

characters, and a European version which includes Cyrillic and Western
European characters.

The 7
-
bit

ASCII

subset for the Japanese version is non
-
standard:
it supplies a Yen symbol where the backslash character is normally found, and l
eft
and right arrow symbols in place of tilde and the rub
-
out character.





A limited number of custom characters can be programmed into the device in the
form of a bitmap using special commands. These characters have to be written to the
device each

time it is switched on, as they are stored in volatile memory.



5
.3.2 Features


The
features of the LCD display are given below:



16 Characters x 2 Lines
.



5x8

Dot Matrix Character + Cursor
.



HD44780 Equivalent LCD Controller/driver Built
-
In
.



4
-
bit or
8
-
bit MPU Interface
.



Standard Type
.



Works with almost any Microcontroller
.



Great Value Pricing
.


Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


35


VAST





5
.3.3 Pin Diagram



The pin diagram & description of pins of 16x2 LCD display is given below:




Fig. 5
.5

LCD display







There may also be a single
backlight pin, with the other connection via Ground or
VCC pin. The two backlight pins may precede the pin 1. The nominal backlight
voltage is around 4.2V at 25˚C using a VDD 5V capable model. Character LCDs can
operate in 4
-
bit or 8
-
bit mode. In 4 bit mod
e, pins 7 through 10 are unused and the
entire byte is sent to the screen using pins 11 through 14 by sending 4
-
bits (
nibble
) at
a time.





For example if we want to display the character ‘A’ on the LCD display, the
ASCII of the character 41 (0100 0001
) will be displayed on the screen in bit wise. If
only four data pins are used then first LSB (0001) will be given to the display then
MSB (0100).






In this project the LCD display interfaced to the PIC in Port D with fo
ur data
pins as shown in Fig
.4.2
. The TRIS D register is set to 0, since LCD display is an
output device.





Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


36


VAST





5
.4 ZIGBEE Module




In this project the data will be transmitted from the attendance entering system to
the main server using wireless technology. The past several

years have witnessed a
rapid growth of wireless networking. However,

up to now wireless networking has
been mainly focused on high
-
speed communications,

and relatively long range
applications such as the IEEE 802.11 Wireless Local Area

Network (WLAN)
stan
dards. The
fi
rst well known standard focusing on Low
-
Rate

Wireless Personal
Area Networks (LR
-
WPAN) was Bluetooth. However it has limited

capacity for
networking of many nodes. There are many wireless monitoring and control

applications in industrial and h
ome environments which require longer battery life,
lower

data rates and less complexity than those from existing standards. For such
wireless

applications, a new standard called IEEE 802.15.4 has been developed by
IEEE. The

new standard is also called Zig
Bee, when additional stack layers de
fi
ned
by the ZigBee

Alliance are used.



ZigBee

is a

specification

for a suite of high level communication protocols
using small, low
-
power

digital radios

based on the

IEEE 802.15.4
-
2003 standard

for



Low

Rate

Wireless Personal Area Networks

(LR
-
WPANs), such as wireless light
switches with lamps, electrical meters with
in
-
home
-
displays

and consumer

electronics equipment via short
-
range radio needing low rates of data transfer. The
technology defined by the

Zigb
ee specification

is intended to be simpler and less
expensive than other

WPANs
, such as

Bluetooth
. ZigBee is targeted at

radio
-
frequency

(RF) applications that require a low data rate, long battery life, and secure
networking.



5
.4.1 Wireless Personal
Area Network (WPAN)



A WPAN (wireless personal area network) is a personal area network
-

a
network for interconnecting devices centered on an individual person's workspace
-

in
which the connections are wireless. Typically, a wireless personal
area network uses


Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


37


VAST




some technology that permits communication within about 10

meters (33

ft) such
as

Bluetooth
, which was used as the basis for a new standard,

IEEE 802.15
.




A
WPAN could serve to interconnect all the ordinary computing and
commun
icating devices that many people have on their desk or carry with them today
-

or it could serve a more specialized purpose such as allowing the surgeon and other
team members to communicate during an operation.




A key concept in WPAN technology is
known as "plugging in". In the ideal
scenario, when any two WPAN
-
equipped devices come into close proximity (within
several meters of each other) or within a few kilometers of a central server, they can
communicate as if connected by a cable. Another impor
tant feature is the ability of
each device to lock out other devices selectively, preventing needless interference or
unauthorized access to information.




The technology for WPANs is in its infancy and is undergoing rapid
development. Proposed operat
ing frequencies are around 2.4

GHz in digital modes.
The objective is to facilitate seamless operation among home or business devices and
systems. Every device in a WPAN will be able to plug in to any other device in the
same WPAN, provided they are within

physical range of one another. In addition,
WPANs worldwide will be interconnected.




5
.4.2 The Name ZIGBEE



The name ZigBee is said to come from the domestic honeybee which uses a zig
-
zag type of dance to communicate important information to other hive members. This
communication dance (the "ZigBee Principle") is what engineers are trying to emulate
wit
h this protocol _ a bunch of separate and simple organisms that join together to
tackle complex tasks.


The domestic honeybee, a colonial insect, lives in a hive that
contains a queen, a few male drones, and thousands of worker bees. The survival,
success,
and future of the colony
are

dependent upon continuous communication of
vital information between every member of the colony. The technique that honey bees
use to communicate new
-
found food sources to other members of the colony is
referred to as the ZigBe
e Principle. Using this silent, but powerful communication

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


38


VAST




system, whereby the bee dances in a zig
-
zag pattern, she is able to share information
such as the location, distance, and direction of a newly discovered food source to her
fellow colony members.

Instinctively implementing the ZigBee Principle, bees around
the world industriously sustain productive hives and foster future generations of
colony members.



5
.4.3
Trademark and Alliance



The ZigBee Alliance is an association of companies wor
king together to enable
reliable, cost
-
effective, and low
-
power wirelessly networked monitoring and control
products based on an open global standard.

The ZigBee Alliance is a group of
companies that maintain and publish the ZigBee standard. The term

ZigBe
e

is a
registered

trademark

of this group, not a single technical standard.


As per its main role, it standardizes the body that defines ZigBee, and also
publishes

application profiles

that allow multiple

OEM

vendors to create
interoperable product
s. The current list of application profiles either published, or in
the works are:



ZigBee Home Automation



ZigBee Smart Energy 1.0



ZigBee Telecommunication Services



ZigBee Health Care



ZigBee Remote Control



5
.4.4 IEEE 802.15.4





Creating wireless networks can be done using a variety of RF protocols. Some
protocols are proprietary to individual vendors, others are industry standards. This
Application Note will explore the ZigBee protocol industry standard for data
transmission, a
nd the IEEE 802.15.4 protocol on which it was built. We will define
the frequencies used, the bandwidth it occupies, and networking features unique to
this protocol. ZigBee is a protocol that uses the 802.15.4 standard as a baseline and


Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


39


VAST




adds additional routing and networking functionality.

What ZigBee is designed to do
is add mesh networking to the underlying 802.15.4 radio.


The goal IEEE had when they speci
fi
ed the IEEE 802.15.4 standard was to
provide a

standard for ultra
-
low co
mplexity, ultra
-
low cost, ultra
-
low power
consumption and low

data rate wireless connectivity among inexpensive devices.



802.15.4
Is

a standard for wireless communication put out by the IEEE (Institute
for Electrical and Electronics Engineers). IEEE
has published the standards that
define communication in areas such as the Internet, PC peripherals, industrial
communication and wireless technology. As a few examples, the IEEE 802.11
standard defines communication for wireless LAN and 802.16 define comm
unication
for broadband wireless Metropolitan Area Networks. While both of those wireless
standards are concerned with higher bandwidth Internet access applications, 802.15.4
was developed with lower data rate, simple connectivity and battery application i
n
mind.



The 802.15.4 standard specifies that communication can occur in the 868
-

868.8MHz, the 902
-
928 MHz or the 2.400
-
2.4835 GHz Industrial Scientific and
Medical (ISM) bands. While any of these bands can technically be used by
802.15.4 devices, t
he 2.4 GHz band is more popular as it is open in most of the
countries worldwide.




The 868 MHz band is specified primarily for European use, whereas the 902
-
928
MHz band can only be used in the United States, Canada and a few other countries
and ter
ritories that accept the FCC regulations. The 802.15.4 standard specifies that
communication should occur in 5 MHz channels ranging from 2.405 to 2.480 GHz. In
the 2.4 GHz band, a maximum over
-
the
-
air data rate of 250 kbps is specified, but due
to the over
head of the protocol the actual theoretical maximum data rate is
approximately half of that. While the standard specifies 5 MHz channels, only
approximately 2 MHz of the channel is consumed with the occupied bandwidth.



At 2.4 GHz, 802.15.4 specifi
es the use of Direct Sequence Spread Spectrum and
uses an Offset Quadrature Phase Shift Keying (O
-
QPSK) with half
-
sine pulse shaping
to modulate the RF carrier.



Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


40


VAST






The relationship between

IEEE 802.15.4

and ZigBee

is similar to that
between

IEEE 802
.11

and the

Wi
-
Fi Alliance
. The ZigBee 1.0 specification was
ratified on 14 December 2004 and is available to members of the ZigBee Alliance.
Most recently, the ZigBee 2007 specification was posted on 30 October 2007. The
first ZigBee Application Profile,
Home Automation, was announced 2 November
2007. As amended by

NIST
, the Smart Energy Profile 2.0 specification will remove
the dependency on IEEE 802.15.4. Device manufacturers will be able to implement
any MAC/PHY, such as

IEEE 802.15.4
(
x) and

IEEE P1901
, under an IP layer based
on

6LoWPAN
.



5
.4.5 Components of the IEEE 802.15.4


IEEE 802.15.4 networks use three types of devices:



The network Coordinator maintains overall network knowledge. It is the most
sophisticated one of the three types, and require
s the most memory and
computing power.



The Full Function Device (FFD) supports all IEEE 802.15.4 functions and
f
eatures specifi
ed by the standard. It can function as a network coordinator.
Additional memory and computing power make it ideal for network rou
ter


functions or it could be used in network
-
edge devices (where the network
touches the real world).



The Reduced Function Device (RFD) carries limited (as speci_ed by the
standard) functionality to lower cost and complexity. It is generally found in
netw
ork
-
edge devices. The RFD can be used where extremely low power
consumption is a necessity.



5
.4.6 ISM Band



The

industrial, scientific and medical (ISM)

radio bands

were originally reserved
internationally for the use of

radio frequency (RF)

ene
rgy for industrial, scientific and



medical purposes other than communications. Examples of applications in these
bands include

radio
-
frequency process heating
,

micro wave ovens
, and

Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


41


VAST




medical

diathermy

machines. The powerful emissions of these devices
can
create

electromagnetic interference

and disrupt

radio communication
using

the
same

frequency
, so these devices were limited to certain bands of frequencies
.
In
general, communications equipment operating in these bands must accept any
interference gene
rated by ISM equipment.




The ISM bands are defined by the

ITU
-
R

in 5.138, 5.150, and 5.280 of the

Radio
Re
gulations
. Individual countries' use of the bands designated in these sections may
differ due to variations in national radio regulations. Beca
use communication devices
using the ISM bands must tolerate any interference from ISM equipment, these bands

are typically given over to uses intended for unlicensed operation, since unlicensed
operation typically needs to be tolerant of interference from
other devices anyway.




In the United States of America, uses of the ISM bands are governed by Part 18
of the FCC rules, while

Part 15

contains the rules for unlicensed communication
devices, even those that use the ISM frequencies.




For many
people, the most commonly encountered ISM device is the
home

microwave ovens
operating at 2.45

GHz. However, in recent years these bands
have also been shared with license
-
free error
-
tolerant communications applications
such as

Wireless sensor Networks

in
the 868

MHz, 915

MHz and 2.450

GHz bands,
as well as

wireless LANs

and

cordless phones

in the 915

MHz, 2.450

GHz, and


5.800

GHz bands.

IEEE 802.15.4
,

Zigbee

and other personal area networks may use
the

915 MHz

and

2450 MHz

ISM bands.



5
.4.7 General char
acteristics of ZIGBEE




ZigBee is a low
-
cost, low
-
power,

wireless mesh networking

standard. First, the
low cost allows the technology to be widely deployed in wireless control and
monitoring applications. Second, the low power
-
usage allows longer

life with smaller
batteries. Third, the mesh networking provides high reliability and more extensive
range.

Because ZigBee can activate (go from sleep to active mode) in 30 msec or less,
the latency can be very low and devices can be very responsive


par
ticularly

compared to Bluetooth wake
-
up delays, which are typically around three seconds.


Attendance Automation


MINI

PROJECT REPORT ‘1
1







Dept. of ECE


42


VAST




Because ZigBees can sleep most of the time, average power consumption can be very
low, resulting in long battery life.

The general characteristics of the zigbee ar
e:



Data rates of 20 kbps and up to 250 kbps



Star or Peer
-
to
-
Peer network topologies



Support for Low Latency Devices



CSMA
-
CA Channel Access



Handshaking



Low Power Usage consumption



3 Frequencies bands with 27 channels



Extremely low duty
-
cycle (<0.1%)


5
.4.8

Device Types


There are three different types of ZigBee devices:



ZigBee coordinator (ZC)
:

The most capable device, the coordinator forms
the root of the network tree and might bridge to other networks. There is
exactly one ZigBee coordinator in each network since it is the device that

started the

network originally. It is able to store informa
tion about the
network, including acting as the Trust Center & repository for security keys.



ZigBee Router (ZR)
:

As well as running an application function, a router can
act as an intermediate router, passing on data from other devices.



ZigBee End Device
(ZED)
:
Contains just enough functionality to talk to the
parent node (either the coordinator or a router); it cannot relay data from other
devices. This relationship allows the node to be asleep a significant amount of
the time thereby giving long battery
life. A ZED requires the least amount of
memory, and therefore can be less expensive to manufacture than a ZR or ZC.


5
.4.9 Different Stacks of ZIGBEE




The first

stack