VLSI Design Lecture 3a: Nonideal Transistors

Electronics - Devices

Nov 2, 2013 (4 years and 8 months ago)

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VLSI Design

Lecture 3a:

Nonideal Transistors

Outline

Transistor I
-
V Review

Nonideal Transistor Behavior

Velocity Saturation

Channel Length Modulation

Body Effect

Leakage

Temperature Sensitivity

Process and Environmental Variations

Process Corners

Ideal Transistor I
-
V

Shockley

1
st

order transistor models

Ideal nMOS I
-
V Plot

180 nm TSMC process

Ideal Models

= 155(W/L)

A/V
2

V
t

= 0.4 V

V
DD

= 1.8 V

Simulated nMOS I
-
V Plot

180 nm TSMC process

BSIM 3v3 SPICE models

What differs?

Simulated nMOS I
-
V Plot

180 nm TSMC process

BSIM 3v3 SPICE models

What differs?

Less ON current

No square law

Current increases

in saturation

Velocity Saturation

We assumed carrier velocity is proportional to E
-
field

v

=

E
lat

=

V
ds
/L

At high fields, this ceases to be true

Carriers scatter off atoms

Velocity reaches
v
sat

Electrons: 6
-
10 x 10
6

cm/s

Holes: 4
-
8 x 10
6

cm/s

Better model

Vel Sat I
-
V Effects

Ideal transistor ON current increases with V
DD
2

Velocity
-
saturated ON current increases with V
DD

Real transistors are partially velocity saturated

Approximate with

-
power law model

I
ds

V
DD

1 <

< 2 determined empirically

-
Power Model

Channel Length Modulation

Reverse
-
biased p
-
n junctions form a
depletion
region

Region between n and p with no carriers

Width of depletion L
d

region grows with reverse bias

L
eff

= L

L
d

Shorter L
eff

gives more current

I
ds

increases with V
ds

Even in saturation

Chan Length Mod I
-
V

=
channel length modulation coefficient

not feature size

Empirically fit to I
-
V characteristics

Body Effect

V
t
: gate voltage necessary to invert channel

Increases if source voltage increases
because source is connected to the channel

Increase in V
t

with V
s

is called the
body effect

Body Effect Model

s

=
surface potential

at threshold

Depends on doping level N
A

And intrinsic carrier concentration n
i

=
body effect coefficient

OFF Transistor Behavior

Simulated results

What differs?

Current doesn’t go

to 0 in cutoff

Leakage Sources

Subthreshold conduction

Transistors can’t abruptly turn ON or OFF

Junction leakage

Reverse
-
biased PN junction diode current

Gate leakage

Tunneling through ultrathin gate dielectric

Subthreshold leakage is the biggest source in
modern transistors

Subthreshold Leakage

Subthreshold leakage exponential with V
gs

n is process dependent, typically 1.4
-
1.5

DIBL

Drain
-
Induced Barrier Lowering

Drain voltage also affect V
t

High drain voltage causes subthreshold
leakage to ________.

DIBL

Drain
-
Induced Barrier Lowering

Drain voltage also affect V
t

High drain voltage causes subthreshold
leakage to
increase
.

Junction Leakage

Reverse
-
biased p
-
n junctions have some
leakage

I
s

depends on doping levels

And area and perimeter of diffusion regions

Typically < 1 fA/

m
2

Gate Leakage

Carriers may tunnel thorough very thin gate oxides

Predicted tunneling current (from [Song01])

Negligible for older processes

May soon be critically important

Temperature Sensitivity

Increasing temperature

Reduces mobility

Reduces V
t

I
ON

___________ with temperature

I
OFF

___________ with temperature

Temperature Sensitivity

Increasing temperature

Reduces mobility

Reduces V
t

I
ON

decreases

with temperature

I
OFF

increases

with temperature

So What?

So what if transistors are not ideal?

They still behave like switches.

But these effects matter for…

Supply voltage choice

Logical effort

Quiescent power consumption

Pass transistors

Temperature of operation

Parameter Variation

Transistors have uncertainty in parameters

Process: L
eff
, V
t
, t
ox

of nMOS and pMOS

Vary around typical (T) values

Fast (F)

L
eff
: ______

V
t
: ______

t
ox
: ______

Slow (S): opposite

Not all parameters are independent

for nMOS and pMOS

Parameter Variation

Transistors have uncertainty in parameters

Process: L
eff
, V
t
, t
ox

of nMOS and pMOS

Vary around typical (T) values

Fast (F)

L
eff
:
short

V
t
:
low

t
ox
:
thin

Slow (S): opposite

Not all parameters are independent

for nMOS and pMOS

Environmental Variation

V
DD

and T also vary in time and space

Fast:

V
DD
: ____

T: ____

70 C

1.8

T

S

F

Temperature

Voltage

Corner

Environmental Variation

V
DD

and T also vary in time and space

Fast:

V
DD
:
high

T:
low

70 C

1.8

T

125 C

1.62

S

0 C

1.98

F

Temperature

Voltage

Corner

Process Corners

Process corners describe worst case
variations

If a design works in all corners, it will probably
work for any variation.

Describe corner with four letters (T, F, S)

nMOS speed

pMOS speed

Voltage

Temperature

Important Corners

Some critical simulation corners include

Pseudo
-
nMOS

Subthrehold

leakage

Power

Cycle time

Temp

V
DD

pMOS

nMOS

Purpose

Important Corners

Some critical simulation corners include

?

?

F

S

Pseudo
-
nMOS

S

F

F

F

Subthrehold

leakage

F

F

F

F

Power

S

S

S

S

Cycle time

Temp

V
DD

pMOS

nMOS

Purpose