VLSI Critical Design Report

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Nov 2, 2013 (3 years and 5 months ago)

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VLSI Critical Design Report

EE715

Spatial Filter Coefficients ROM

James O’Boyle

Pat Friel

Design Progress


0 Bit Cell


1 Bit Cell


Pull
-
Up Network


Array


Buffer Network


Timing & Functionality


Problems

The 0 Bit Cell

The 1 Bit Cell

Forming The Array


This next slide shows how our single array cells, which
store 1 or 0 bits, fit together to form the array.


The metal1 layer in the vertical direction on the right is
the output of the array which is brought down to our
buffer network to boost the 2.5V output to 4.8+V.


The metal2 layer on top is the connection to the gates of
the array transistors. This connection comes from the
decoder which selects the appropriate row in the array.


The metal2 layer on bottom is the ground line for the
nmos array transistors.


We used as little polysilicon as possible to cut down
resistance.

Forming The Array

The Pull
-
Up Network


The Pull
-
Up Network allows the array
transistors to conduct when the decoder
output selects a certain row of transistors.


All the transistors in that row will conduct
sending an output voltage of 2.5V down to
the Buffer Network.

The Pull
-
Up Network

Array


The array is completely programmed with binary
1’s.


Reprogramming of the array will be done with
dummy data.


We are designing the ROM with a 16 bit output
instead of 8 bits and can possibly go to a 32 bit
output.


Current complete size is a 64x16 bit ROM


The next slide shows a close
-
up picture of the
ROM array we have designed.

Array

The Buffer Network


Our buffer network is a series of inverter’s
with modified transistor widths.


This network strengthens the signal sent
from the array and produces it on the
output pins of the chip.


The next slide shows a close
-
up picture of
our buffer network.

The Buffer Network

Timing & Functionality


From addressing the array with signals without
using a decoder, the propagation from the input
signals on the gates of the array transistors to
the waveform produced on the outputs after the
buffer network is approximately 8.216pS. This is
very fast however this is not using the decoder.


Our largest bottleneck in the design will be our
decoder.


So far the functionality of our design is very
acceptable.


Most of our design is done in full custom layout.
The decoder will be one of the few auto placed
components.

Problems & Future Modifications


Trouble with IC Station auto placing our 6
to 64 decoder.


Possibly make the array larger than 64x16
bits.


Extra unused pins on the chip will be
connected at various places throughout
our design for testing.


ROM Programming

VLSI Design


-
James O’Boyle


-
Pat Friel