TRANSISTORS Transistor – a three-terminal device for which the ...

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©
Watkins 2008


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TRANSISTORS


Transistor

a three
-
terminal device for which the voltage or current at one
terminal controls the electrical behavior of the other terminals.


Bipolar Junction Transistor (BJT)

a three
-
terminal device for which the current at
one terminal
controls the electrical behavior of the other terminals.





1 2
3
i
1
i
2
!
i
1




Current
-
Controlled (Dependent) Current Source




i
2
=
β
i
1



Field Effect Transistor (FET)

a three
-
terminal device for which a voltage related
to one terminal controls the electrical beha
vior of the other terminals.





1 2
3
+
v
13
-
i
2
gv
13




Voltage
-
Controlled (Dependent) Current Source




i
2
= g v
13





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TRANSISTOR IV CHARACTERISTICS


IV Characteristic

the current
-
voltage behavior of a transistor is often represented
as a set of curves, each of which co
rresponds to a different control current or
voltage. The desired operation is limited to specific ranges of current and
voltage, e.g. active regions. The nonlinear device must be biased to the
desired operating point by an external circuit.


Examples:




1
2
3
i
1
i
2
+
v
23
-


i
1
i
2
v
23








i
2
=
β
i
1






1
2
3
i
2
+
v
23
-
+
v
13
-


i
2
v
23
v
13








i
2
= g v
13





Typical Applications



Signal Amplification

a small signal is replicated and amplified



Switching

a low
-
power input controls a high power output



Logic Operations

a digital logic function is implem
ented




Transistors may be implemented in semiconductors as discrete devices or as
integrated circuits.


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BIPOLAR JUNCTION TRANSISTOR


Bipolar Junction Transistor (BJT)

device formed by a p
-
type material between
two n
-
type materials or an n
-
type materia
l between two p
-
type materials.



Terminal Nomenclature

Base (B), Collector (C), and Emitter (E)




npn BJT: Structure



Circuit Symbol




B
C
E
i
B
i
C
+
v
CE
-
p
n
n


B
C
E
i
B
i
C
+
v
CE
-





pnp BJT: Structure



Circuit Symbol




B
C
E
i
B
i
C
-
v
EC
+
n
p
p


B
C
E
i
B
i
C
-
v
EC
+



Equilibrium Energy Band Diagram for npn Structure

n
-
type Regio
n

Collector

p
-
type Region

Base

n
-
type Region

Emitter


Junction


Junction











E
F



















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BJT OPERATING CONDITIONS


BJT Operating Conditions



Base
-
Emitter Junction

Forward Bias



Collector
-
Base Junction

Reverse Bias


Energy Band Dia
gram for Biased npn Structure

n
-
type Region

Collector

p
-
type Region

Base

n
-
type Region

Emitter


Junction


Jcn



































Base
-
Emitter Junction under Forward Bias



Junction width narrows



Diffusion current dominates



Holes
injected into the emitter region



Electrons injected (emitted) into the base region


Base
-
Collector Junction under Reverse Bias



Junction width broadens



Drift current dominates



Holes extracted from collector region near the junction



Electrons extracted (coll
ected) from base region near the junction


Desired Operation


Electrons injected from the emitter into the base diffuse across the
undepleted base region and are captured by the high electric field in
the base
-
collector junction. Electrons lost to recombi
nation in the
base region do not contribute to the collector current.


The design depends on the width of the base region, a diffusion
coefficient for electrons, and the average recombination lifetime for
electrons.



©
Watkins 2008


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BJT CURRENTS


BJT Currents

a summary
of important currents in an npn transistor is shown
below. (Some secondary effects are omitted.)



Emitter electron current i
En
and hole current i
Ep




Collector current i
C
~ i
Cn




Base current i
B
~ i
Bp




Reverse
-
bias thermally
-
generated emitter
-
base current
(neglected
in further analysis)







B
C
E
i
B
i
C
p
n
n
i
E
e
h



The emitter injection efficiency
γ
= i
En
/(i
En
+ i
Ep
)


The base transport factor
α
F
= i
Cn
/i
En



Then, the current transfer ratio




α
o
= i
C
/i
E
~ (i
Cn
/i
E
) = (i
Cn
/i
En
) [i
En
/(i
En
+ i
Ep
)] =
α
F

γ



Kirchhoff’s Current Law for the transistor gives




+ i
C
+ i
B


i
E
= 0 or + i
B
=
+ i
E


i
C



Hence, the gain is




β
= i
C
/i
B
= i
C
/(i
E


i
C
) = (i
C
/i
E
)/[1

(i
C
/i
E
)] = (
α
o
)/[1

(
α
o
)]



To produce a large gain
β
, the current transfer ratio
α
o
(and the base
transport factor
α
F
and the emitter injection efficiency
γ
) must be near
unity.


Design optimization



Highly doped emitter (n+): i
E
~ i
En
and
γ
= i
En
/(i
En
+ i
Ep
) is near unity



Narrow base width and light base doping: little recombination in the
base region (i.e.
α
F
is near unity)


Note that the emitter and collector are typicall
y doped differently.


©
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BJT OPERATING CONDITIONS


BJT Operating Conditions



Base
-
Emitter Junction

Forward Bias



Collector
-
Base Junction

Reverse Bias


Energy Band Diagram for Biased pnp Structure

p
-
type Region

Collector

n
-
type Region

Base

p
-
type Region

Em
itter


Junction


Jcn





































Base
-
Emitter Junction under Forward Bias



Junction width narrows



Diffusion current dominates



Electrons injected into the emitter region



Holes injected (emitted) into the base region


Base
-
Collector Junction under Reverse Bias



Junction width broadens



Drift current dominates



Electrons extracted from collector region near the junction



Holes extracted (collected) from base region near the junction


Desired Operation


Holes injected from the emi
tter into the base diffuse across the
undepleted base region and are captured by the high electric field in
the base
-
collector junction. Holes lost to recombination in the base
region do not contribute to the collector current.


The design depends on the
width of the base region, a diffusion
coefficient for holes, and the average recombination lifetime for holes.




©
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BJT CURRENTS


BJT Currents

a summary of important currents in a pnp transistor is shown
below. (Some secondary effects are omitted.)



Emitt
er electron current i
En
and hole current i
Ep




Collector current i
C
~ i
Cp




Base current i
B
~ i
Bn




Reverse
-
bias thermally
-
generated emitter
-
base current (neglected
in further analysis)







B
C
E
i
B
i
C
n
p
p
i
E
h
e



The emitter injection efficiency
γ
= i
Ep
/(i
En
+ i
Ep
)


The base transport factor
α
F
= i
Cp
/i
Ep



Then, the current transfer ratio




α
o
= i
C
/i
E
~ (i
Cp
/i
E
) = (i
Cp
/i
Ep
) [i
Ep
/(i
En
+ i
Ep
)] =
α
F

γ



Kirchhoff’s Current Law for the transistor gives




+ i
C
+ i
B


i
E
= 0 or + i
B
=
+ i
E


i
C



Hence, the gain is




β
= i
C
/i
B
= i
C
/(i
E


i
C
) = (i
C
/i
E
)/[1

(i
C
/i
E
)] = (
α
o
)/[1

(
α
o
)]



To produce a large gain
β
, the current transfer ratio
α
o
(and the base
transport factor
α
F
and the emitter injection efficiency
γ
) must be near
unity.


Design optimization



Highly doped emitter (p+): i
E
~ i
Ep
and
γ
= i
Ep
/(i
En
+ i
Ep
) is near unity



Narrow base width and light base doping: little recombination in the
base region (i.e.
α
F
is near unity)


Note that the emitter and collector are typicall
y doped differently.


©
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SUMMARY OF BJT BEHAVIOR


The bipolar junction transistor current amplification with gain
β
= i
C
/i
B
.



npn BJT



B
C
E
i
B
i
C
+
v
CE
-



i
B
i
C
v
CE




npn BJT Operating Conditions



Forward Bias of Base
-
Emitter Junction v
BE
> turn
-
on voltage



Reverse Bias of Coll
ector
-
Base Junction v
BC
< 0 or v
CB
> 0



pnp BJT



B
C
E
i
B
i
C
-
v
EC
+



i
B
i
C
v
EC




pnp BJT Operating Conditions



Forward Bias of Base
-
Emitter Junction v
EB
> turn
-
on voltage



Reverse Bias of Collector
-
Base Junction v
CB
< 0 or v
BC
> 0



Regions in the Common
-
Emitter IV Charac
teristic



Saturation

the base
-
collector junction is not reverse biased for low
values of v
CE
(npn) or v
EC
(pnp) and
i
C
is not proportional to i
B
.



Active

the normal operating region in which
i
C
=
β
i
B
.



Breakdown (not shown)

the active region limit for
large values of
v
CE
(npn) or v
EC
(pnp) when breakdown occurs in the collector
-
base
junction


Other secondary effects may be considered for more accurate representations, but
these effects are beyond the scope of this class.


©
Watkins 2008


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COMMON
-
BASE BJT CIRCUIT AND A
NALYSIS


Common
-
Base Biasing Circuit with a pnp BJT



Forward Bias of Base
-
Emitter Junction v
EB
> turn
-
on voltage



Reverse Bias of Collector
-
Base Junction v
CB
< 0 or v
BC
> 0

+
V
o
-
-
V
CC
+
R
e
+
V
EE
+
v
s
-
B
C
E
i
B
i
C
i
E
+
v
EC
-
-
v
BC
+
R
c



Analysis for Operating Point (v
BC
,i
C
) with v
S
= 0.



Kirchhoff’s
-
Voltage
-
Law
on Emitter Side (v
EC
= V
to
):



-
V
EE
+ i
E
R
e
+ V
to
= 0 or i
E
= (1/R
e
)(V
EE

-
V
to
)


and



i
C
=
α
o
i
E
= (
α
o
/R
e
)(V
EE

-
V
to
)



Kirchhoff’s
-
Voltage
-
Law on Collector Side (the Load
-
Line Equation):



-
V
CC
+ i
C
R
c
+ v
BC
= 0 or v
BC
= V
CC

-
i
C
R
c




With no signal v
S
= 0



V
o
= i
C
R
c
= (
α
o
R
c
/R
e
)(V
EE

-
V
to
)


With a signal v
S




V
o
= i
C
R
c
= (
α
o
R
c
/R
e
)(V
EE

-
V
to
) + (
α
o
R
c
/R
e
)(v
S
)



Graphical Analysis




Load
-
Line




-
V
CC
+ i
C
R
c
+ v
BC
= 0




Intercepts




v
BC
= V
CC





i
C
= V
CC
/R
c



i
E
i
C
v
BC


©
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COMMO
N
-
EMITTER BJT
AMPLIFIER
AND ANALYSIS


Common
-
Emitter
Biasing Circuit with an npn BJT



Forward Bias of Base
-
Emitter Junction v
BE
> turn
-
on voltage



Reverse Bias of Collector
-
Base Junction v
BC
< 0 or v
CB
> 0

-
V
o
+
+
V
CC
-
R
b
+
V
BB
+
v
s
-
R
c
i
C
B
C
E
i
B
+
v
CE
-
i
E




Analysis for Operating Point (v
CE
,i
C
) with
v
S
= 0.



Kirchhoff’s
-
Voltage
-
Law on Base Side (v
BE
= V
to
):



-
V
BB
+ i
B
R
b
+ V
to
= 0 or i
B
= (1/R
b
)(V
BB

-
V
to
)


and



i
C
=
β
i
B
= (
β
/R
b
)(V
BB

-
V
to
)



Kirchhoff’s
-
Voltage
-
Law on Collector Side (the Load
-
Line Equation):



-
V
CC
+ i
C
R
c
+ v
CE
= 0
or v
CE
= V
CC

-
i
C
R
c




With no signal v
S
= 0



V
o
= i
C
R
c
= (
β
R
c
/R
b
)(V
BB

-
V
to
)


With a signal v
S




V
o
= i
C
R
c
= (
β
R
c
/R
b
)(V
BB

-
V
to
) + (
β
R
c
/R
b
)(v
S
)



Graphical Analysis




Load
-
Line




-
V
CC
+ i
C
R
c
+ v
CE
= 0




Intercepts




v
CE
= V
CC





i
C
= V
CC
/R
c



i
B
i
C
v
CE


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COMMON
-
EMITTER BJT
AMPLIFIER
AND ANALYSIS


Co
mmon
-
Emitter Biasing Circuit with a
pnp BJT



Forward Bias of Base
-
Emitter Junction v
EB
> turn
-
on voltage



Reverse Bias of Collector
-
Base Junction v
CB
< 0 or v
BC
> 0

+
V
o
-
-
V
CC
+
R
b
-
V
BB
+
v
s
+
R
c
i
C
B
C
E
i
B
-
v
EC
+
i
E




Analysis for Opera
ting Point (v
EC
,i
C
) with v
S
= 0.



Kirchhoff’s
-
Voltage
-
Law on Base Side (v
EB
= V
to
):



-
V
BB
+ i
B
R
b
+ V
to
= 0 or i
B
= (1/R
b
)(V
BB

-
V
to
)


and



i
C
=
β
i
B
= (
β
/R
b
)(V
BB

-
V
to
)



Kirchhoff’s
-
Voltage
-
Law on Collector Side (the Load
-
Line Equation):



-
V
CC
+ i
C
R
c
+ v
EC
= 0 or v
EC
= V
CC

-
i
C
R
c




With no signal v
S
= 0



V
o
= i
C
R
c
= (
β
R
c
/R
b
)(V
BB

-
V
to
)


With a signal v
S




V
o
= i
C
R
c
= (
β
R
c
/R
b
)(V
B
B

-
V
to
) + (
β
R
c
/R
b
)(v
S
)



Graphical Analysis




Load
-
Line




-
V
CC
+ i
C
R
c
+ v
EC
= 0




Intercepts




v
EC
= V
CC





i
C
= V
CC
/R
c



i
B
i
C
v
EC


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DARLINGTON

AMPLIFIER
AND ANALYSIS


Comm
on
-
Emitter Biasing Circuit with dual
-
npn BJT
’s



Forward Bias of Base
-
Emitt
er Junction
s
v
BE
> turn
-
on voltage



Reverse Bias of Collector
-
Base Junction
s
v
BC
< 0 or v
CB
> 0

-
V
o
+
+
V
CC
-
R
b
+
V
BB
+
v
s
-
R
c
i
C1
i
C2
B
C
E
i
B2
+
v
CE2
-
B
C
!
1
i
B1
+
v
CE1
-
E
!
2



Kirchhoff’s
-
Voltage
-
Law on Base Side (v
BE1
=

v
BE2
= V
to
):



-
(V
BB
+ v
S
) + i
B1
R
b
+ 2V
to
= 0 or i
B1
= (1/R
b
)[(V
BB
+ v
S
)
-
2V
to
]


and



i
C1
=
β
1
i
B1
= (
β
1
/R
b
)[

(V
BB
+ v
S
)
-
2V
to
]



Also, noting that
β
1
/
α
o1
= 1 +
β
1




i
C2
=
β
2
i
B2
=
β
2
i
E1
=
β
2
i
C1
/
α
o1
=
β
2
β
1
i
B1
/
α
o1
=
β
2
(1 +
β
1
)i
B1




i
C2
=
β
2
(1 +
β
1
)(1/R
b
)[

(V
BB
+ v
S
)
-
2V
to
]



Then,



i
C1
+

i
C2
= [
β
1
+
β
2
(1 +
β
1
)]{(1/R
b
) [(V
BB
+ v
S
)
-
2V
t
o
]}



i
C1
+

i
C2
= [
β
1
+
β
2
+
β
1
β
2
]{(1/R
b
) [(V
BB
+ v
S
)
-
2V
to
]}



The output voltage is



V
o
= (i
C1
+ i
C2
)R
c
= [
β
1
+
β
2
+
β
1
β
2
]{(R
c
/R
b
) [(V
BB
+ v
S
)
-
2V
to
]}



Note that the overall gain of the dual
-
transistor configuration is



β
Dual
= (i
C1
+ i
C2
)/i
B1
=
(
β
1
+
β
2
+
β
1
β
2
)



If the transistors are identical with a large gain (
β
1
=
β
2
=
β
>>1),



β
Dual
= (i
C1
+ i
C2
)/i
B1
=
β
(2+
β
) ~
β
2




The overall gain can be increased further with additional transistors.



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COMMON
-
EMITTER BJT
AMPLIFIER

VARIATION


Co
mmon
-
Emitter Biasing Circuit with a
pnp BJT



Forward Bias of Base
-
Emitter Junction v
EB
> turn
-
on voltage



Reverse Bias of Collector
-
Base Junction v
CB
< 0 or v
BC
> 0

+
V
o
-
-
V
CC
+
R
b
-
V
BB
+
v
s
+
R
c
i
C
B
C
E
i
B
-
v
EC
+
i
E
R
e



Analysis for Operating Point (v
EC
,i
C
) with v
S
= 0.



Kirchhoff’s
-
Voltage
-
Law on Base Side
(v
EB
= V
to
):



-
V
BB
+ i
B
R
b
+ i
E
R
e
+ V
to
= 0



Since
β
/
α
o
= 1 +
β
and i
C
=
α
o
i
E
=
β
i
B
, then i
E
= (1 +
β
)i
B



and




i
B
= (V
BB

-
V
to
)/[R
e
(1 +
β
) + R
b
] or




i
E
= (V
BB

-
V
to
)/[R
e
+ R
b
/(1 +
β
)]


Also,



i
C
=
β
i
B
= (V
BB

-
V
to
)/[R
e
(1 +
β
)/(
β
) + R
b
/(
β
)]



Kirchhoff’s
-
Voltage
-
Law on Collector Side (the Loa
d
-
Line Equation):



-
V
CC
+ i
C
R
c
+ i
E
R
e
+ v
EC
= 0 or v
EC
= V
CC

-
i
C
R
c

-
i
E
R
e




If
β
>>1, then i
C
~ (V
BB

-
V
to
)/[R
e
+ R
b
/(
β
)]



If R
e
>> R
b
/(
β
), then i
C
~ (V
BB

-
V
to
)/(R
e
)



With no signal v
S
= 0




V
o
= i
C
R
c
= (R
c
/R
e
)(V
BB

-
V
to
)



With a signal v
S





V
o
= i
C
R
c
= (R
c
/R
e
)(V
BB

-
V
to
) + (R
c
/R
e
)(v
S
)



Note that for v
S
= 0, this circuit serves as a constant current source, i.e. the
current does not depend on the load resistance R
c
.


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of
38
B


COMMON
-
EMITTER
CIRCUITS WITH COUPLING CAPACITORS



Coupling Capacit
or in pnp
BJT
s

Common
-
Emitter Circuits




Separating Signal v
S
and Biasing Source V
BB



+
V
o
-
-
V
CC
+
R
b
-
v
s
+
R
c
i
C
B
C
E
i
B
-
v
EC
+
i
E
R
e
-
V
BB
+




Different AC and DC Load Lines


+
V
o
-
-
V
CC
+
R
b
-
v
s
+
R
c
i
C
B
C
E
i
B
-
v
EC
+
R
e
-
V
BB
+




Separating the DC Current from the Load Resistance


+
V
o
-
-
V
CC
+
R
b
-
v
s
+
R
c
i
C
B
C
E
i
B
-
v
EC
+
R
e
-
V
BB
+
R
L



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CONSTANT CURRENT SOURCE WITH
BJT


Constant Current Source (
Comm
on
-
Emitter) Circuit with an
npn BJT



Forward Bias of Base
-
Emitter Junction
s
v
BE
> turn
-
on voltage



Reverse Bias of Collector
-
Base Junction
s
v
BC
< 0 or v
CB
> 0




Consider the voltage source and the
resistors R
1
and R
2
separately.




The Thevenin equivalen
t with
respect to the Base node and the
reference node has




V
BB
= V
TH
= V
CC
[R
2
/(R
1
+ R
2
)]



R
b
= R
TH
= R
1
||R
2
= [R
1
R
2
/(R
1
+ R
2
)]





The equivalent circuit is



-
V
o
+
+
V
CC
-
R
b
+
V
BB
-
i
C
B
C
E
i
B
+
v
CE
-
i
E
R
e
R
c



As before, the operating point (v
CE
,i
C
) is



i
C
=
β
i
B
= (V
BB

-
V
to
)/[R
e
(1 +
β
)/(
β
) + R
b
/(
β
)] from KVL on base side



v
CE
= V
CC

-
i
C
R
c

-
i
E
R
e

from KVL on collector side



If
β
>>1, then i
C
~ (V
BB

-
V
to
)/[R
e
+ R
b
/(
β
)] (no dependence on R
c
)



If R
e
>> R
b
/(
β
), then i
C
~ (V
BB

-
V
to
)/(R
e
)




V
o
= i
C
R
c
= (R
c
/R
e
)(V
BB

-
V
to
)


Only one voltage source is needed.

+
V
o
-
+
V
CC
-
i
C
B
C
E
i
B
+
v
CE
-
i
E
R
e
R
c
R
2
R
1


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EMITTER
-
FOLLOWER BJT CIRCUIT AND
ANALYSIS


Emitter
-
Follower
Biasing Circuit with an npn BJT



Forward Bias of Base
-
Emitter Junction v
BE
> turn
-
on voltage



Reverse Bias of Collector
-
Base Junction v
BC
<
0 or v
CB
> 0



+
V
o
-
+
V
CC
-
R
b
+
V
BB
+
v
s
-
i
C
B
C
E
i
B
+
v
CE
-
i
E
R
e



Analysis for Operating Point (v
CE
,i
C
) with v
S
= 0.



Kirchhoff’s
-
Voltage
-
Law on Base Side (v
BE
= V
to
):



-
V
BB
+ i
B
R
b
+ i
E
R
e
+ V
to
= 0



Since
β
/
α
o
= 1 +
β
and i
C
=
α
o
i
E
=
β
i
B
, then i
E
= (1 +
β
)i
B



and




i
B
= (V
BB

-
V
to
)/[R
e
(1 +
β
) + R
b
] or




i
E
= (V
BB

-
V
to
)/[R
e
+ R
b
/(1 +
β
)]


Also,



i
C
=
β
i
B
= (V
BB

-
V
to
)/[R
e
(1 +
β
)/(
β
) + R
b
/(
β
)]



Kirchhoff’s
-
Voltage
-
Law on Collector Side (the Loa
d
-
Line Equation):



-
V
CC
+ i
E
R
e
+ v
CE
= 0 or v
CE
= V
CC

-
i
E
R
e




If R
e
>> R
b
/(1 +
β
), then i
E
~ (V
BB

-
V
to
)/(R
e
)



With no signal v
S
= 0




V
o
= i
E
R
e
= (V
BB

-
V
to
)



With a signal v
S





V
o
= i
E
R
e
= (V
BB

-
V
to
) + (v
S
)




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B


MULTIPLE
-
TRANSISTOR

CIR
CUITS


Differential Amplifier with npn
BJT
s








V
o2
+
V
CC
-
R
b
+
v
s1
-
i
C1
B
C
E
i
B1
+
v
CE1
-
i
E1
R
e
R
c
-
V
EE
+
i
C2
B
C
E
i
B2
+
v
CE2
-
i
E2
R
e
R
c
+
v
s2
-
R
b
V
o1



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Page
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38
B


FIELD EFFECT TRANSISTOR


Junction Field Effect Transistor (JFET)

device formed by an n
-
type channel
between two p
-
type materials or a p
-
type channel between two n
-
type
material
s.



Terminal Nomenclature

Gate (G), Drain (D), and Source (S)




n
-
Channel JFET: Structure

Circuit Symbol




G
D
S
i
DS
+
v
DS
-
p
n
n
+
v
GS
-
p


G
D
S
i
DS
+
v
DS
-
+
v
GS
-





p
-
Channel JFET: Structure

Circuit Symbol




G
D
S
i
SD
-
v
SD
+
n
p
p
-
v
SG
+
n


G
D
S
i
SD
-
v
SD
+
-
v
SG
+



Equilibrium Energy Band Diagram for n
-
Channel Structure

p
-
type Region

Gate

n
-
type Chan
nel Region

Source / Drain

p
-
type Region

Gate


Junction


Junction











E
F



















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JFET OPERATING CONDITIONS


JFET Operating Conditions for n
-
Channel



Gate
-
Channel Junction

Reverse Bias



Energy Band Diagram for Biased n
-
Channel Stru
cture

p
-
type Region

Gate

n
-
type Channel Region

Source / Drain

p
-
type Region

Gate


Junction


Junction














E
F
















Gate
-
Channel Junction under Reverse Bias



Junction width broadens



Drift current dominates (and is small)


Channel
provides Drain
-
Source current path



Current (mainly electrons) in the n
-
channel is dependent upon
dimensions of undepleted channel



Electrons travel from Source to Drain in the channel


Desired Operation


Current (mainly electrons) travels through the chann
el. The depletion
region of the Gate
-
Channel junction constricts the channel as a
function of Gate
-
Channel reverse bias and limits the current increase.
As the depletion regions close the channel, further current increases
go to zero and the channel is i
n saturation.


The design depends on the dimensions of the channel, the doping
levels of the gate and channel, and breakdown characteristics of the
gate
-
channel junction.



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JFET PARAMETERS


JFET Current and Voltages

a summary of important current and v
oltages in an n
-
channel field
-
effect transistor is shown below. (Some secondary effects are
omitted.)



Drain
-
Source Voltage v
DS
and Current i
DS




Gate
-
Source Voltage v
GS




Reverse
-
bias thermally
-
generated gate
-
channel current (neglected
in further analys
is)

Gate
-
Channel current ~ 0








G
D
S
i
DS
p
n
n
e
+
v
DS
-
+
v
GS
-
p



Note that the Gate regions are electrically connected.



Pinch
-
off Voltage V
po
: Gate
-
Channel Reverse
-
bias Voltage for which the
opposite depletion regions merge



Saturation Current I
DSS
: Drain
-
Source Current for
saturation conditions
(maximum current for v
GS
= 0)



Note that the Gate
-
Channel Voltage varies as a function of position.


Design optimization



Highly doped gate regions (p+): depletion regions extend primarily
into the channel



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JFET CHARACTERISTIC


Phys
ical Operation of the n
-
channel JFET




v
GS
= 0 and v
DS
= 0


v
GS
= 0 and V
po
> v
DS
> 0




G
D
S
i
DS
n
n
+
v
DS
-
+
v
GS
-
p
p


G
D
S
i
DS
n
n
e
+
v
DS
-
+
v
GS
-
p
p





v
GS
= 0 and v
DS
= V
po



v
GS
= 0 and v
DS
> V
po





G
D
S
i
DS
n
n
e
+
v
DS
-
+
v
GS
-
p
p


G
D
S
i
DS
n
n
e
+
v
DS
-
+
v
GS
-
p
p




Un
-
biased (v
GS
= 0 and v
DS
= 0): i
DS
= 0



Unsaturated Region with

v
GS
= 0 and V
po
> v
DS
> 0: i
DS
inc
reases, but
at a decreasing rate due to channel constriction and




i
DS
= I
DSS
[2(v
DS
/V
po
)

(v
DS
/V
po
)
2
]



Saturation Region with

v
GS
= 0 and v
DS
> V
po
> 0: i
DS
= I
DSS
(current
maintains the pinch
-
off condition with no further current increase)



Influence of
Gate
-
Channel bias (
-
V
po
< v
GS
< 0):




Unsaturated: i
DS
= I
DSS
[2(1 + v
GS
/V
po
) (v
DS
/V
po
)

(v
DS
/V
po
)
2
]




Saturation: i
DS
= I
DSS
(1 + v
GS
/V
po
)
2



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JFET OPERATING CONDITIONS


JFET Operating Conditions for p
-
Channel



Gate
-
Channel Junction

Reverse Bias



En
ergy Band Diagram for Biased p
-
Channel Structure

n
-
type Region

Gate

p
-
type Channel Region

Source / Drain

n
-
type Region

Gate


Junction


Junction














E
F
















Gate
-
Channel Junction under Reverse Bias



Junction width broadens



Drif
t current dominates (and is small)


Channel provides Drain
-
Source current path



Current (mainly holes) in the p
-
channel is dependent upon
dimensions of undepleted channel



Holes travel from Source to Drain in the channel


Desired Operation


Current (mainly h
oles) travels through the channel. The depletion
region of the Gate
-
Channel junction constricts the channel as a
function of Gate
-
Channel reverse bias and limits the current increase.
As the depletion regions close the channel, further current increases
go to zero and the channel is in saturation.


The design depends on the dimensions of the channel, the doping
levels of the gate and channel, and breakdown characteristics of the
gate
-
channel junction.



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JFET PARAMETERS


JFET Current and Voltages

a sum
mary of important current and voltages in a p
-
channel field
-
effect transistor is shown below. (Some secondary effects are
omitted.)



Source
-
Drain Voltage v
SD
and Current i
SD




Source
-
Gate Voltage v
SG




Reverse
-
bias thermally
-
generated gate
-
channel curren
t (neglected
in further analysis)

Gate
-
Channel current ~ 0








G
D
S
i
SD
n
p
p
h
-
v
SD
+
-
v
SG
+
n



Note that the Gate regions are electrically connected.



Pinch
-
off Voltage V
po
: Gate
-
Channel Reverse
-
bias Voltage for which the
opposite depletion regions merge



Saturation Current I
SDS
: Source
-
Drain Current for saturation conditions
(maximum current

for v
SG
= 0)



Note that the Gate
-
Channel Voltage varies as a function of position.


Design optimization



Highly doped gate regions (n+): depletion regions extend primarily
into the channe
l




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JFET CHARACTERISTIC


Physical Operation of the p
-
channel JFET




v
SG
= 0 and v
SD
= 0


v
SG
= 0 and V
po
> v
SD
> 0




G
D
S
i
SD
p
p
-
v
SD
+
-
v
SG
+
n
n


G
D
S
i
SD
p
p
h
-
v
SD
+
-
v
SG
+
n
n





v
SG
= 0 and v
SD
= V
po



v
SG
= 0 and v
SD
> V
po





G
D
S
i
SD
p
p
h
-
v
SD
+
-
v
SG
+
n
n


G
D
S
i
SD
p
p
h
-
v
SD
+
-
v
SG
+
n
n




Un
-
biased (v
SG
= 0 and v
SD
= 0): i
SD
= 0



Unsaturated Region with

v
SG
= 0 and V
po
> v
SD
> 0: i
SD
increases, but
at a decreasing rate due to channel constriction and




i
SD
= I
SDS
[2(v
SD
/V
po
)

(v
SD
/V
po
)
2
]



Saturation Region with

v
SG
= 0 and v
SD
> V
po
> 0: i
SD
= I
SDS
(current
maintains the pinch
-
off condition with no further
current increase)



Influence of Gate
-
Channel bias (
-
V
po
< v
SG
< 0):




Unsaturated: i
SD
= I
SDS
[2(1 + v
SG
/V
po
) (v
SD
/V
po
)

(v
SD
/V
po
)
2
]




Saturation: i
SD
= I
SDS
(1 + v
SG
/V
po
)
2




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CONDITIONS FOR
JFET
SATURATION



JFET
Saturation Conditions for n
-
Channel



Gat
e
-
Drain
Junction
at Reverse
-
Bias
pinch
-
off voltage V
po




n
-
Channel JFET



G
D
S
i
DS
+
v
DS
-
+
v
GS
-




v
GS
i
DS
v
GS
= 0



Kirchhoff’s
-
Voltage
-
Law for n
-
channel JFET:



-
v
GS

-
v
DG
+ v
DS
= 0 or v
DG
= v
DS


v
GS



General pinch
-
off condition including influence of Gate
-
Channel bias:




v
DG
= v
DS


v
GS

>
V
po




Unsaturated Region of Operation: V
po
> v
DS


v
GS
> 0




i
DS
= I
DSS
[2(1 + v
GS
/V
po
) (v
DS
/V
po
)

(v
DS
/V
po
)
2
]



Saturation Region of Operation: v
DS


v
GS

>
V
po
> 0




i
DS
= I
DSS
(1 + v
GS
/V
po
)
2
for
-
V
po
< v
GS
< 0



The IV characteristic is
continuous at the threshold of saturation.



Let v
DS


v
GS
= V
po
or v
DS
= V
po
+ v
GS





i
DS
= I
DSS
[2(1 + v
GS
/V
po
) (v
DS
/V
po
)

(v
DS
/V
po
)
2
]



i
DS
= I
DSS
{2(1 + v
GS
/V
po
) [(V
po
+ v
GS
)/V
po
]

[(V
po
+ v
GS
)/V
po
)]
2
}



i
DS
= I
DSS
[(2 + 2v
GS
/V
po
) (1 + v
GS
/V
po
)

(1
+ v
GS
/V
po
)
2
]



i
DS
= I
DSS
[2 + 4v
GS
/V
po
+ 2(v
GS
/V
po
)
2


1

2 v
GS
/V
po


(v
GS
/V
po
)
2
]



i
DS
= I
DSS
[1 + 2v
GS
/V
po
+ (v
GS
/V
po
)
2
]




i
DS
= I
DSS
(1 + v
GS
/V
po
)
2




General pinch
-
off condition for p
-
channel JFET




v
GD
= v
SD


v
SG

>
V
po




Unsaturated Region
of Operation: V
po
> v
SD


v
SG
> 0




i
SD
= I
SDS
[2(1 + v
SG
/V
po
) (v
SD
/V
po
)

(v
SD
/V
po
)
2
]



Saturation Region of Operation: v
SD


v
SG

>
V
po
> 0




i
SD
= I
SDS
(1 + v
SG
/V
po
)
2
for
-
V
po
< v
SG
< 0



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SUMMARY OF JFET BEHAVIOR


The
junction field effect
transistor wit
h
pinch
-
off voltage V
po




n
-
Channel JFET



G
D
S
i
DS
+
v
DS
-
+
v
GS
-




v
GS
i
DS
v
GS
= 0




n
-
Channel JFET Operating Conditions



Reverse Bias
of Gate
-
Channel Junction:
v
DS
>
0
and
-
V
po
< v
GS
< 0


i
DS
= I
DSS
[2(1 + v
GS
/V
po
) (v
DS
/V
po
)

(v
DS
/V
po
)
2
] and i
DS
= I
DSS
(1 + v
GS
/V
po
)
2
.



p
-
Channel JFET



G
D
S
i
SD
-
v
SD
+
-
v
SG
+



v
SG
i
SD
v
SD
v
SG
= 0




p
-
Channel JFET Operating Conditions



Reverse Bias
of Gate
-
Channel Junction:
v
SD
>
0
and
-
V
po
< v
SG
< 0


i
SD
= I
SDS
[2(1 + v
SG
/V
po
) (v
SD
/V
po
)

(v
SD
/V
po
)
2
] and i
SD
= I
SDS
(1 + v
SG
/V
po
)
2
.


Regions in the
JFET
IV Characteristic



Unsaturated Region

the channel is below pinch
-
off and the current
i
DS
varies strongly with v
DS
or v
SD
.



Saturation Region

the channel is above pinch
-
off and the current i
DS

varies strongly with v
GS
or v
SG
.



Breakdown (not shown)

the limit for large values of v
DS
(
n
-
channe
l
)
or v
SD
(
p
-
channel
) when breakdown occurs in the
gate
-
channel

junction


Other secondary effects may be considered for more accurate representations, but
these effects are beyond the scope of this class.


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COMPARISON OF
FET STRUCTURES



Junction Field E
ffect T
ransistor
(
JFET
):
n
-
Channel




G
D
S
i
DS
+
v
DS
-
p
n
n
+
v
GS
-
p


v
GS
i
DS
v
DS
v
GS
= 0



G
D
S
i
DS
+
v
DS
-
+
v
GS
-




i
DS
v
GS
I
DSS
-V
po



Metal
-
Oxide
-
Semiconductor Field Effect T
ransistor
(MOS
FET
):


Depletion
-
Mode
n
-
Channel




G
D
S
i
DS
+
v
DS
-
n
n
+
v
GS
-
p-
B


v
GS
i
DS
v
DS
v
GS
= 0




G
D
S
i
DS
+
v
DS
-
+
v
GS
-
B

G
D
S
i
DS
+
v
DS
-
+
v
GS
-

i
DS
v
GS
I
DSS
-V
po





Base Separate

Base Connected to Source



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29
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COMPARISON OF
FET STRUCTURES



Junction Field Effec
t T
ransistor
(
JFET
):
n
-
Channel




G
D
S
i
DS
+
v
DS
-
p
n
n
+
v
GS
-
p


v
GS
i
DS
v
DS
v
GS
= 0



G
D
S
i
DS
+
v
DS
-
+
v
GS
-




i
DS
v
GS
I
DSS
-V
po



Metal
-
Oxide
-
Semiconductor Field Effect T
ransistor
(MOS
FET
):


Enhancement
-
Mode
n
-
Channel




G
D
S
i
DS
+
v
DS
-
n
n
+
v
GS
-
p-
B


v
GS
i
DS
v
DS
v
GS
= 0




G
D
S
i
DS
+
v
DS
-
+
v
GS
-
B

G
D
S
i
DS
+
v
DS
-
+
v
GS
-

i
DS
v
GS





Base Separate

Base Connected to Source



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SUMMARY OF
FET TYPES



Junction Field Effect T
ransist
or
(
JFET
):
n
-
Channel and p
-
channel


n
-
Channel JFET Equations


i
DS
= I
DSS
[2(1 + v
GS
/V
po
)(v
DS
/V
po
)

(v
DS
/V
po
)
2
] & i
DS
= I
DSS
(1 + v
GS
/V
po
)
2
.



G
D
S
i
DS
+
v
DS
-
+
v
GS
-
i
DS
v
GS
I
DSS
-V
po

G
D
S
i
SD
-
v
SD
+
-
v
SG
+
i
SD
v
SG
I
SDS
-V
po



Metal
-
Oxide
-
Semiconductor Field Effect T
ransistor
s

(MOS
FET
):




Depletion
-
Mode
n
-
Channel and p
-
Channel (Ba
se connected to Source)


Depletion
-
Mode n
-
Channel MOSFET Equations


i
DS
= I
DSS
[2(1 + v
GS
/V
po
)(v
DS
/V
po
)

(v
DS
/V
po
)
2
] & i
DS
= I
DSS
(1 + v
GS
/V
po
)
2
.



G
D
S
i
DS
+
v
DS
-
+
v
GS
-
i
DS
v
GS
I
DSS
-V
po

G
D
S
i
SD
-
v
SD
+
-
v
SG
+
i
SD
v
SG
I
SDS
-V
po



Enhancement
-
Mode
n
-
Channel and p
-
Channel (Base connected to Source)


Enhancement
-
Mode n
-
Channel MOSF
ET Equations


i
DS
= KV
on
2
{2[(v
GS
/V
on
)

1](v
DS
/V
on
)
-
(v
DS
/V
on
)
2
} &



i
DS
= KV
on
2
[(v
GS
/V
on
)

1]
2
.



G
D
S
i
DS
+
v
DS
-
+
v
GS
-
i
DS
v
GS

G
D
S
i
SD
-
v
SD
+
-
v
SG
+
i
SD
v
SG




The Enhancement
-
Mode MOSFET turns on when v
GS/SG
> V
on
> 0.


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v
DS
v
GS
i
DS
v
GS
= 0

COMMON
-
SOURCE JFET CIRCUIT AND ANALYSIS


Common
-
Source Biasing Circuit with an n
-
ch
annel JFET



Reverse Bias of Gate
-
Channel
-
V
po
< v
GS
< 0 and v
DS
> 0



“On” for i
DS
> 0 and “Off” for i
DS
= 0




+
V
o
-
+
V
DD
-
+
V
GG
-
R
d
G
D
S
i
DS
+
v
DS
-
+
v
GS
-




Analysis for Operating Point (v
DS
, i
DS
).



The Gate Voltage determines the Drain
-
Source Current (V
GG
= v
GS
).



For
-
V
po
< v
GS
< 0, then i
DS

= I
DSS
(1 + v
GS
/V
po
)
2
.



Kirchhoff’s
-
Voltage
-
Law on Drain Side (the Load
-
Line Equation):



-
V
DD
+ i
DS
R
d
+ v
DS
= 0 or v
DS
= V
DD


i
DS
R
d





For operation in the saturation region, the Output Voltage is



V
O
= v
DS
= V
DD


i
DS
R
d
= V
DD


[I
DSS
(1 + v
GS
/V
po
)
2
]R
d







Graphical Analysis




Load
-
Line




-
V
DD
+ i
DS
R
d
+ v
DS
= 0




Intercepts




v
DS
= V
DD





i
DS
= V
DD
/R
d




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32
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38
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v
SG
i
SD
v
SD
v
SG
= 0

COMMON
-
SOURCE JFET CIRCUIT AND ANALYSIS


Common
-
Source Biasing Circuit with a p
-
channel JFET



Reverse Bias of Gate
-
Channel
-
V
p
o
< v
SG
< 0 and v
SD
> 0



“On” for i
SD
> 0 and “Off” for i
SD
= 0




-
V
o
+
-
V
DD
+
-
V
GG
+
R
d
G
D
S
i
SD
-
v
SD
+
-
v
SG
+




Analysis for Operating Point (v
SD
, i
SD
).



The Gate Voltage determines the Drain
-
Source Current (V
GG
= v
SG
).



For
-
V
po
< v
SG
< 0, then i
SD
= I
SDS
(1 + v
SG
/V
po
)
2
.



Kirchhoff’s
-
Voltage
-
Law on Drain Side (the Load
-
Line Equation):



-
V
DD
+ i
SD
R
d
+ v
SD
= 0 or v
SD
= V
DD


i
SD
R
d





For operation in the saturation region, the Output Voltage is



V
O
= v
SD
= V
DD


i
SD
R
d
= V
DD


[I
SDS
(1 + v
SG
/V
po
)
2
]R
d







Graphical Analysis




Load
-
Line




-
V
DD
+ i
SD
R
d
+ v
SD
= 0




Intercepts




v
SD
= V
DD





i
SD
= V
DD
/R
d




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i
DS
v
GS
I
DSS
-V
po

SOURCE
-
FOLLOWER JFET CIRCUIT AND ANALYSIS


Source
-
Follower Biasing Circuit with an n
-
channel JFET



Reverse Bias of Gate
-
Channel
-
V
po
< v
GS
< 0 and v
DS
> 0



“On” for i
DS
> 0
and “Off” for i
DS
= 0




+
V
o
-
+
V
DD
-
+
V
GG
-
R
s
G
D
S
i
DS
+
v
DS
-
+
v
GS
-




Analysis for Operating Point (v
DS
, i
DS
).



Kirchhoff’s
-
Voltage
-
Law on Gate
-
Source Side:



-
V
GG
+ i
DS
R
s
+ v
GS
= 0 or v
GS
= V
GG


i
DS
R
s



and for operation in the saturation region



-
V
po
< v
GS
= (V
GG


i
DS
R
s
) < 0 and
i
DS
= I
DSS
(1 + v
GS
/V
po
)
2
.



Kirchhoff’s
-
Voltage
-
Law on Drain Side (the Load
-
Line Equation):



-
V
DD
+ i
DS
R
s
+ v
DS
= 0 or v
DS
= V
DD


i
DS
R
s





For operation in the saturation region, the Output Voltage is



V
O
= i
DS
R
s
= I
DSS
R
s
(1 + v
GS
/V
po
)
2
=
I
DSS
R
s
[1 + (V
GG


i
DS
R
s
)/V
po
]
2
.




Graphical Analysis




Gate
-
Source Equation




-
V
GG
+ i
DS
R
s
+ v
GS
= 0




Intercepts




V
GS
= V
GG





i
DS
= V
GG
/R
s




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Page
34
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38
B


COMMON
-
SOURCE
CIRCUIT WITH COUPLING CAPACITORS



Coupling Capacitor in n
-
Channel JFET

Common
-
Emit
ter Circuits




Coupled Signal v
S
and Different AC and DC Load Lines


+
V
DD
-
R
s
R
d
R
2
R
1
G
D
S
i
DS
+
v
DS
-
+
v
GS
-
+
V
o
-
R
L
+
v
s
-
R
g




Thevenin equivalent Circuit with









V
GG
= V
TH
= V
CC
[R
2
/(R
1
+ R
2
)]





R
TH
= R
1
||R
2
= [R
1
R
2
/(R
1
+ R
2
)]



+
V
DD
-
R
s
R
d
R
TH
G
D
S
i
DS
+
v
DS
-
+
v
GS
-
+
V
o
-
R
L
+
v
s
-
R
g
+
V
GG
-



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G
D
S
i
DS
+
v
DS
-
+
v
GS
-
+
V
o
-
+
V
DD
-
i
G
R
s
R
d
R
g

G
D
S
i
SD
-
v
SD
+
-
v
SG
+
-
V
o
+
-
V
DD
+
i
G
R
s
R
d
R
g

SELF
-
BIASING JFET CIRCUIT


Self
-
Biasing Circuit with an n
-
chan
nel JFET



Reverse Bias of Gate
-
Channel
-
V
po
< v
GS
< 0 and v
DS
> 0





Analysis for Operating Point



(v
DS
, i
DS
).



Kirchhoff’s
-
Voltage
-
Law for Gate
-
Source gives (i
G
= 0).



v
GS
=
-
i
DS
R
s



For
-
V
po
< v
GS
< 0, then




i
DS
= I
DSS
(1 + v
GS
/V
po
)
2





i
DS
=
I
DSS
[1 + (
-
i
DS
R
s
)/V
po
]
2
.



Kirchhoff’s
-
Voltage
-
Law on Drain
Side (the Load
-
Line Equation):



-
V
DD
+ i
DS
(R
d
+R
s
) + v
DS
= 0
or

v
DS
= V
DD


i
DS
(R
d
+R
s
)


Self
-
Biasing Circuit with a p
-
channel JFET



Reverse Bias of Gate
-
Channel
-
V
po
< v
SG
< 0 and v
S
D
> 0





Analysis for Operating Point



(v
SD
, i
SD
).



Kirchhoff’s
-
Voltage
-
Law for Gate
-
Source gives (i
G
= 0).



v
SG
=
-
i
SD
R
s



For
-
V
po
< v
SG
< 0, then




i
SD
= I
SDS
(1 + v
SG
/V
po
)
2





i
SD
= I
SDS
[1 + (
-
i
SD
R
s
)/V
po
]
2
.



Kirchhoff’s
-
Voltage
-
Law on Drain
Side (the Load
-
Line Equation):



-
V
DD
+ i
SD
(R
d
+R
s
) + v
SD
= 0
or

v
SD
= V
DD


i
SD
(R
d
+R
s
)



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Page
36
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38
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v
GS
i
DS
v
DS
v
GS
= 0

ENHANCEMENT
-
MODE MOSFET CIRCUIT


Passive Drain Load on an Enhancement
-
Mode n
-
channel MOSFET



Reverse Bias of Gate
-
Channel 0 < V
on
< v
GS
and v
DS
> 0



“On”
for i
DS
> 0 (V
on
< v
GS
) and “Off” for i
DS
= 0 (V
on
> v
GS
)




+
V
o
-
+
V
DD
-
R
d
i
DS
G
D
S
+
v
DS
-
+
v
GS
-
+
V
i
-




Analysis for Operating Point (v
DS
, i
DS
).



The Gate Voltage determines the Drain
-
Source Current (V
i
= v
GS
).



For 0 < V
on
< v
GS
= V
i
, then i
DS
= KV
on
2
(v
GS
/V
on

-
1)
2
.



Kirchhoff’s
-
Voltage
-
Law on Drain Side (the Load
-
Line Equation):



-
V
DD
+ i
DS
R
d
+ v
DS
= 0 or v
DS
= V
DD


i
DS
R
d








Graphical Analysis




Load
-
Line




-
V
DD
+ i
DS
R
d
+ v
DS
= 0




Intercepts




v
DS
= V
DD





i
DS
= V
DD
/R
d





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Page
37
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38
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v
GS
i
DS
v
DS
v
GS
= 0

DEPLETION
-
MODE MOSFET CIRCUIT


Depl
etion
-
Mode n
-
channel MOSFET as an Active Load



Reverse Bias of Gate
-
Channel v
DS
> 0



Gate connected to the Source v
GS
= 0




+
V
DD
-
i
DS
G
D
S
+
v
DS
-
+
v
GS
-
+
V
SS
-




Analysis for Operating Point (v
DS
, i
DS
).



The Gate Voltage determines the Drain
-
Source Current (v
GS
= 0).



i
DS
= I
DSS
[2(1
+ 0) (v
DS
/V
po
)

(v
DS
/V
po
)
2
] & i
DS
= I
DSS
(1 + 0)
2
.



Kirchhoff’s
-
Voltage
-
Law on Drain Side (the Load
-
Line Equation):



-
V
DD
+ V
SS
+ v
DS
= 0 or v
DS
= V
DD


V
SS








Graphical Analysis




For v
DS
= V
DD


V
SS
> V
po





Then i
DS
= I
DSS





For
v
DS
= V
DD


V
SS
< V
po





Then i
DS
=




I
DSS
[2(v
DS
/V
po
)

(v
DS
/V
po
)
2
]




©
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MISSOURI
S&T

Page
38
of
38
B


ENHANCEMENT
-
MODE MOSFET INVERTER CIRCUIT


Active Drain Load on an Enhancement
-
Mode n
-
channel MOSFET



Enhancement
-
Mode MOSFET with Input V
i
= v
GS1




Depletion
-
Mode MOSFET with
v
GS2
= 0




+
V
o
-
i
DS1
G
D
S
+
v
DS1
-
+
v
GS1
-
+
V
i
-
+
V
DD
-
i
DS2
G
D
S
+
v
DS2
-
+
v
GS2
-




Analysis for V
o
vs. V
i




Kirchhoff’s
-
Voltage
-
Law (the Load
-
Line Equation):



-
V
DD
+ v
DS2
+ v
DS1
= 0 or v
DS1
= V
DD


v
DS2




For V
i
= v
GS1
< V
on
, i
DS1
= i
DS2
= 0; then v
DS2
= 0 and (LL) v
DS1
= V
DD




(MOSFET 1 “Off” and
MOSFET 2 Unsaturated Region)


For V
i
= v
GS1
> V
on
and v
DS2
> V
po
, i
DS1
= i
DS2
= I
DSS2
;




then (LL) v
DS1
< V
DD


V
po
(MOSFET 1 and MOSFET 2 Saturated)


For V
i
= v
GS1
>> V
on
and v
DS2
> V
po
, i
DS1
= i
DS2
= I
DSS2
;




then (LL) v
DS1
<< V
DD


V
po





(MOSFET
1Unsatured Region and MOSFET 2 Saturated)




v
GS1
i
DS1
v
DS1
v
GS1
= 0

V
o
V
i
= v
GS1
=
v
DS1