Sizing and Placement of Charge Sizing and Placement of Charge Recycling Transistors in MTCMOS Circuits Recycling Transistors in MTCMOS Circuits MTCMOS Circuits MTCMOS Circuits

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Nov 2, 2013 (3 years and 9 months ago)

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Sizing and Placement of Charge Sizing and Placement of Charge
Recycling Transistors in
MTCMOS Circuits
Recycling Transistors in
MTCMOS Circuits
MTCMOS Circuits
MTCMOS Circuits
EhsanPakbaznia
EhsanPakbaznia
EhsanPakbaznia
EhsanPakbaznia
Ehsan

PakbazniaEhsan

Pakbaznia
Farzan
FarzanFallahFallah*
*
M
assoud
P
ed
r
a
mM
assoud
P
ed
r
a
m
Ehsan

PakbazniaEhsan

Pakbaznia
Farzan
FarzanFallahFallah*
*
M
assoud
P
ed
r
a
mM
assoud
P
ed
r
a
m
assoudeda
assoudeda
University of Southern California
University of Southern California*
*
FujitsuLaboratoriesofAmerica
FujitsuLaboratoriesofAmerica
assoudeda
assoudeda
University of Southern California
University of Southern California*
*
FujitsuLaboratoriesofAmerica
FujitsuLaboratoriesofAmerica
1
Fujitsu

Laboratories

of

AmericaFujitsu

Laboratories

of

AmericaFujitsu

Laboratories

of

AmericaFujitsu

Laboratories

of

America
OutlineOutline
OutlineOutline

Introduction

Introduction

Charge Recycling (CR) for Multi-Threshold
CMOS (MTCMOS) Circuits
R
Bd
Lt
StlfCR
MTCMOS

Charge Recycling (CR) for Multi-Threshold
CMOS (MTCMOS) Circuits
R
Bd
Lt
StlfCR
MTCMOS

R
ow-
B
ase
d

L
ayou
t

St
y
l
e
f
or
CR
-
MTCMOS

Sizing and Placement of CR Transistors

R
ow-
B
ase
d

L
ayou
t

St
y
l
e
f
or
CR
-
MTCMOS

Sizing and Placement of CR Transistors

Experimental Results

Conclusion

Experimental Results

Conclusion
2
Leakage in CMOS TechnologyLeakage in CMOS Technology
Leakage in CMOS TechnologyLeakage in CMOS Technology

Vdd
is reduced with CMOS technology scaling

Vdd
is reduced with CMOS technology scaling

Vth
must be lowered to recover the transistor switching
speed

Vth
must be lowered to recover the transistor switching
speed

The subthreshold leakage current increases
exponentially with decreasing V
th

The subthreshold leakage current increases
exponentially with decreasing V
th

A highly effective leakage control mechanism has
proven to be the MTCMOS technique

A highly effective leakage control mechanism has
proven to be the MTCMOS technique
3
Overview of MTCMOSOverview of MTCMOS
Overview of MTCMOSOverview of MTCMOS

A high-V
th
transistor is used to disconnect low-Vth
transistorsfromthegroundorthe
supplyrails

A high-V
th
transistor is used to disconnect low-Vth
transistorsfromthegroundorthe
supplyrails
transistors

from

the

ground

or

the

supply

rails
transistors

from

the

ground

or

the

supply

rails
Vdd
Vdd
P
SLEEP
P
Virtual
Su
pp
l
y
High Threshold
P
N
out
in
Low Threshold
N
out
in
P
ppy
N
SLEEP
Virtual
Ground
N
4
High Threshold
Some Drawbacks of MTCMOSSome Drawbacks of MTCMOS
Some Drawbacks of MTCMOSSome Drawbacks of MTCMOS

State of internal nodes is corrupted, that is, with a footer
sleep transistor, all internal nodes and the virtual ground

State of internal nodes is corrupted, that is, with a footer
sleep transistor, all internal nodes and the virtual ground
(VGND) are charged up to a level near V
dd

Energy is wasted when switching from the Sleepmode
to the Activemode or vice versa
(VGND) are charged up to a level near V
dd

Energy is wasted when switching from the Sleepmode
to the Activemode or vice versa

ThismeansenergycannotbesavedbytheMTCMOStechnique
unlessthesleeptimeissufficientlylong

ThismeansenergycannotbesavedbytheMTCMOStechnique
unlessthesleeptimeissufficientlylong
V
dd
V
dd
dddd
ABCD
E
0
VG
V
dd
0
V
dd
0
0
V
dd
V
dd
V
dd
V
dd
Vdd
0
5
SLEEP
Vdd
0
Vdd
Charge Recycling (CR) MTCMOSCharge Recycling (CR) MTCMOS
Charge Recycling (CR) MTCMOSCharge Recycling (CR) MTCMOS

The charge recycling technique uses both nMOSand
pMOS
sleeptransistors

The charge recycling technique uses both nMOSand
pMOS
sleeptransistors
pMOS
sleep

transistors

Circuit C is divided into two sub-circuits:

Sub-circuit C
1
is connected to the nMOSsleep transistor, S
N
pMOS
sleep

transistors

Circuit C is divided into two sub-circuits:

Sub-circuit C
1
is connected to the nMOSsleep transistor, S
N
1
N

Sub-circuit C2
is connected to the pMOSsleep transistor, S
P
1
N

Sub-circuit C2
is connected to the pMOSsleep transistor, S
P
Vdd
Vdd
CC
VS
SP
C1
C1
C
2
C
2
Connections between
C
1
andC
2
VG
S
N
6
C
1
and

C
2
N
Mode Transition in MTCMOSMode Transition in MTCMOS
Mode Transition in MTCMOSMode Transition in MTCMOS
VV
VV
C
1
V
dd
V
dd
V
dd
V
dd
0
V
dd
0
1
C
1
C2
1
0
dd
0
Vdd
Td, Ed
Active
Active
Sleep
7
T’d, E’d
CR
-
MTCMOS
CR
-
MTCMOS
e
-
e
-
CR
MTCMOS
CR
MTCMOS
e
e
VV
VV
Energy Saving Ratio:Energy Saving Ratio:
Energy Saving Ratio:
Energy Saving Ratio:
C
1
V
dd
V
dd
V
dd
V
dd
0
V
dd
0
1
αV
dd
β
V

β
V

C
1
C2
1
0

0
V摤
0
1
αVdd
dd
βVdd
β

β

X
X
:ratiooftheVGNDto
:ratiooftheVGNDto
X
X
:ratiooftheVGNDto
:ratiooftheVGNDto
X
X
:

ratio

of

the

VGND

to

:

ratio

of

the

VGND

to

VVVV
DD
DD
capacitances
capacitances
X
X
:

ratio

of

the

VGND

to

:

ratio

of

the

VGND

to

VVVV
DD
DD
capacitances
capacitances
Active
Active
Sleep’
CR
ON
CR
OFF
Sleep
8
Row
-
Based Layout for CR
-
MTCMOS
Row
Based Layout for CR
MTCMOS

Layoutstyleforasinglecellrow:

Layoutstyleforasinglecellrow:
VDD
CR Transistor
Cavity
VGND
1
2
3
4
Standard Cells

Twoadjacentrowsusedifferenttypesofsleep
transistors
e
g
nMOS
for
row
i
and
pMOS
for
row
i
+
1

Twoadjacentrowsusedifferenttypesofsleep
transistors
e
g
nMOS
for
row
i
and
pMOS
for
row
i
+
1
GND
V
DD
row “i”
VGND
1
2
3
4
to VV
DD
node
transistors
e
.
g
.,
nMOS
for
row
i
,
and
pMOS
for
row
i
+
1
transistors
e
.
g
.,
nMOS
for
row
i
,
and
pMOS
for
row
i
+
1
row “i+1”
VGND

GND
VV
DD
6
5
7
8
CR1
CR2
CR3
CR4
DD
of gate 5
9
VV
DD
Problem Statement
Problem Statement

Objective:

ﵡﵩ響﹧



ﵩ﹩ﵩ響﹧


カ

ﵡﵩ響﹧



ﵩ﹩ﵩ響﹧


カ

Constraint:

Maximumwakeu
p
-timeincreaseislimitedto
γ
%
p
γ

Decisionvariables:

WidthsoftheCRtransistors(whichmayalsobesettozero)
()
CRoverhead
MinE




ttw
w
CRCR:
:wakeupwakeuptimetimeofofthethe
CRCR--MTCMOSMTCMOScircuitcircuit
()
..
1
CR
ww
st
tt
γ




≤+×


γγ
:
:percentagepercentageincreaseincreaseinin
thethewakeupwakeuptimetime
t
t
:
:
wakeup
wakeup
time
time
of
of
the
the
t
t
w
w
:
:
wakeup
wakeup
time
time
of
of
the
the
original
originalMTCMOSMTCMOScircuitcircuit
10
Power Overhead for CR
-
MTCMOS
Power Overhead for CR
MTCMOS

Dynamic power overhead

﹧nfイ





若葉





f





イ

Static power overhead

Due to extra sneak leakage path in CR-MTCMOS [Pakbaznia-
MM
DAC07]

Total power dissipation overhead (dynamic + static):
2
11
ii
MM
CRoverheadgDDleakDD
ii
P
CfVIV

==
=+
∑∑

M: CR transistor count in the row under consideration

f: mode transition frequency

Cg,i
: input gate capacitance of the ith
CR transistor
11

Ileak,i
: sub-threshold leakage current of the i
th
CR transistor
Power Overhead (cont

d)
Power Overhead (contd)

Itcanbeshownthatthepowerdissipationoverhead
is
proportional
to
the
total
width
of
CR
transistors
:
is
proportional
to
the
total
width
of
CR
transistors
:
1
M
CRoverheadi
i
PW
κ

=
=

1
i
V
PH
§∙
where
κ
isaconstantcoefficientwhichiscalculated
as:
221.8
0
exp
oxth
oxDDDDT
oxT
V
LCfVVve
LtSv
με
κ
⎛⎞

=+
⎜⎟
⎝⎠
Th
bjti
fti
i
th
M
i
M
inW
⎛⎞
⎜⎟
⎜⎟


Th
enewo
bj
ec
ti
ve
f
unc
ti
on
i
s
th
us:
1i=
⎜⎟
⎝⎠

12
RC Model for Charge Recycling Operation
RC Model for Charge Recycling Operation

VGND and VV
DD
are replaced by equivalent RC models
P1
PM
rw-P1
rw-P2
P2
rw-PM-1
RC
model

CR transistors are modeled as linear resistors
G
1
GM
rw-G1
rw-G2
G
2
rw-GM-1
CP2
CPM
CP1
R1
R2
RM
RC-model
of VGND
RC
-
model

of VV
DD
G
1
CG1
CG2
CGM
2
Resistive models
of CR transistors
th
i
ii
Gii+1
:ONdrain-source resistanceoftheiCRtransistor,R
,:Diffusion+interconnectcapacitancesatGandP
r:WiringresistancebetweenGandG
ii
ii
GP
RW
CC
η
=
i
w-
Gii+1
ii+1
r:WiringresistancebetweenGandG
:WiringresistancebetweenPandP
i
wP
r

13
Wakeup Time Constraints
Wakeup Time Constraints

Theoriginalwakeup-timeconstraintcanbewrittenas
M
separate
constraints
one
for
each
G
node
:
M
separate
constraints
,
one
for
each
G
i
node
:
(
)
11
i
CR
ww
ttiM
γ
≤+×∀≤≤
t
CR
i
th
ti
f
t
t

t
w,i
CR
i
s
th
esumma
ti
ono
f
t
wo
t
erms:

Charge-recycling delay

Delay due to discharging the remaining charge in the VGND rail
1
i
CRCRrem
wii
tdtiM=+∀≤≤

New
set
of
equivalent
constraints
:
?
?
11
CRrem
iwi
dttiM
γ
≤+×−∀≤≤

New
set
of
equivalent
constraints
:

t
w
and
t
i
rem
are
easily
obtained
from
Hspice
simulations



and
t
i
are
easily
obtained
from
Hspice
simulations

d
i
CR
mustbecalculated
14
Simplified RC Model
Simplified RC Model

A single equivalent transistor with width W
eq,i
(and
r
es
i
sta
n
ce
R
eqi
)
i
s

de
fin
ed
f
o
r
eac
h
G
i
;

P
i
pa
i
r
:
esstace
eq
,
i
)sdeedoeac
G
i
;
i
pa
P1
C
Pi
PM
C
PM
rw-P1
rw-Pi
Pi
rw-PM-1
C
P1
rw-Pi-1
G1 C
G1
C
Gi
GM CGM
rw-G1
rw-Gi
Gi
rw-GM-1
Pi
C
PM
P1
Reqi
rw-Gi-1
G1
Gi
1,
eqi
M
R
ijM
W
η
η
==≤≤
where
where
()
1
d1h
ii
M
wGwP
i
rr
L
−−
=
+
<<∀

(
)
1
1
i
eq
j
j
W
ijW
α
=



()
1
1
an
d1
eac
h
pass
i
M
oxDDth
i
i
CVV
R
η
α
μ
=
=
==
<<∀


15
Replacing Virtual Rails with Their
Effective RC Models
Re
q
i
G
P
Ri
(G)
Ri
(P)
Ci
(G)
Ci
(P)
G
i
P
i

Ri
(G), Ci
(G): RC-lumped model of the VGND rail atGi

R
i
(P)
C
i
(P)
:
RC
-
lumpedmodeloftheVV
DD
railat
P
i

R
i
,
C
i
:

RC
lumped

model

of

the

VV
DD
rail

at
P
i

For example, forGi we have:
,2
()()
and
Gi
GG
Y
CYR
==


Y
G,1i
and YG,2i
are the first and second moments of the total
admittanceat
G
whichmayberecursivelycalculatedasin
,1
2
,1
and
iGii
Gi
CYR
Y
==
admittance

at

G
i
which

may

be

recursively

calculated

as

in

[Kahng-VLSI Design99]
16
Charge
-
Recycling Delay
Charge
Recycling Delay

The 0-
δ
% CR delay for node Gi
is:
()
(
)
(
)
()()()()
()()
1
ln
i
GPGG
ieqiii
CR
i
GP
ii
RRRCC
d
CC
δ
++

+
(
)

Recall that
(
)
1
i
CR
iwrem
dtt
γ
≤+×−

Thesetoftheconstraintscanthusbere
-
writtenas:
(
)
(
)
()
1
()()
()()
()()
1ln1
i
GP
M
ii
GP
ijjwremii
GP
CC
bWttRRiM
CC
ηγ
δ

⎡⎤
+
⎡⎤
⎢⎥
≥+−−−≤≤
⎣⎦
⎢⎥


The

set

of

the

constraints

can

thus

be

re
written

as:
1
ij
bij
α
=−−
(
)
(
)
()()
1
i
ijjwremii
GP
j
ii
CC
ηγ
=
⎣⎦
⎢⎥
⎣⎦

where:where:
17
Modified Problem Statement
Modified Problem Statement
Minimize
M
i
W
⎛⎞
⎜⎟
⎝⎠

()
()()
()
1
1
()()
()()
()()
1
s.t.:11ln,1
i
i
GP
M
ii
GP
jwremii
GP
j
ii
CC
ijWttRRiiM
CC
αηγδ
=

=
⎜⎟
⎝⎠
⎡⎤
+
⎡⎤
⎢⎥
−−≥+−−−∀≤≤
⎣⎦
⎢⎥
⎣⎦


0,1
j
ii
i
WiiM
⎢⎥
⎣⎦
≥∀≤≤

ThisisalinearProgramming(LP)problem,whichcan
besolvedoptimallyinpolynomialtime
18
CR Transistors Placement
CR Transistors Placement

The sizin
g

p
roblem is solved assumin
g
there is one CR
gpg
transistor between each Gi
; Pi
pair

CRtransistorsthathaveawidthlessthanW
min
willbe
remoed
this
is
called
the
ronding
step
(
W
is
the
remo
v
ed
;
this
is
called
the
ro
u
nding
step
(
W
min
is
the
minimumacceptabletransistorwidth)


響﹧
「ﱥ
ﱬ

ﱶ



ﵡ葉葉


響﹧
「ﱥ
ﱬ

ﱶ



ﵡ葉葉
イ

Sizing+roundingoperationswillberepeateduntilthe
it
i
th
ttl
CR
tit
idth
i
liibl
i
mprovemen
t
i
n
th
e
t
o
t
a
l
CR
t
rans
i
s
t
o
r
w
idth
i
sneg
li
g
ibl
e
19
Simulation Approach
Simulation Approach

Theproposedapproachwascomparedwithtwoother
approaches
approaches

SingleCR-MTCMOS:oneCRtransistorplacedattheleftmost
cornerofeachrow
Uif
CR
MTCMOS
3
ifl
ditibtd
CR
tit

U
n
if
orm
CR
-
MTCMOS
:
3
un
if
orm
l
y-
di
s
t
r
ib
u
t
e
d
CR
t
rans
i
s
t
ors
placedoneachrow

CRtransistor(s)inbothapproachesaresizedsuch
thatthemaximumwakeupdelayincreaseis
γ
%

Experimental Results in 90nm
Technology for ISCAS Benchmarks
TotalCRTXwidth(λ)
Total CR TX
widthc
omparison
Total
Total

CR

TX

width

(λ)
width

c
omparison

(%)
Circuit
# of
cells
# of
rows
Total

sleep tx
width
(λ)
SCR UCR DCR
DCR
vs.
SCR
DCR
vs.
UCR
9Sy
m
276 4 715216678334177550
C432 204 2 4600 625 382 208 67 45
C880 432 6 9936 2326 1458 625 73 57
C1355 526 6 11320 2118 1597 625 71 61
C3540
1295
10
30656
6458
4792
1875
71
61
C3540

1295

10

30656
6458
4792
1875
71
61
C5315 1727 10 38992 11042 6458 2292 79 65
average - - - 4039 2587 1007 75 61

MT=MTCMOS
SC
S
C
COS

SC
R=
S
ingle
C
R-MT
C
M
OS

UCR=UniformCR-MTCMOS

DCR=DistributedCR-MTCMOS(proposed)
21
Experimental Results (cont

d)
Experimental Results (contd)
Switching energy in one complete
active
-
sleepcycle(pJ
)
ESR
c
omparison(%)
Total
D
CR
active
sleep

cycle

(pJ
)

c
omparison

(%)
Circuit
# of
cells
# of
rows
Total

sleep tx
width
MT SCR UCR DCR
D
CR

ESR
(%)
DCR
vs.
SCR
DCR
vs.
UCR
9Sym 276 4 7152 14.4 12 9.6 8.4 42 25 8
C432 204 2 46009.66.65.95.444 135
C880 432 6 9936 20.4 16.9 14.4 12 41 24 12
C1355 526 6 11320 25.2 18.7 17.2 14.4 43 17 11
C3540 1295 10 30656 90 63.6 58.8 50.4 44 15 9
C5315
1727
10
38992
1476
1056
924
804
46
17
8
C5315

1727

10

38992
147
.
6
105
.
6
92
.
4
80
.
4
46

17
8
average - - - 51.1 37.2 33 28.4 44.4 18.5 8.8


MT=MTCMOS

SCR=SingleCR-MTCMOS

UCR=UniformCR-MTCMOS

DCR=DistributedCR-MTCMOS(proposed)
22
ConclusionConclusion
ConclusionConclusion

CR-MTCMOSistheonlyknownmethodforreducing
energy
consumed
during
transitions
between
Sleep

CR-MTCMOSistheonlyknownmethodforreducing
energy
consumed
during
transitions
between
Sleep
energy
consumed
during
transitions
between
Sleep
andActivemodes

TheplacementandsizingproblemofCRtransistors
energy
consumed
during
transitions
between
Sleep
andActivemodes

TheplacementandsizingproblemofCRtransistors
canbeformulatedandsolvedasanLPproblem

Theproposedconcurrentsizingandplacement
technique
allows
us
to
employ
CR
MTCMOS
for
row
canbeformulatedandsolvedasanLPproblem

Theproposedconcurrentsizingandplacement
technique
allows
us
to
employ
CR
MTCMOS
for
row
technique
allows
us
to
employ
CR
-
MTCMOS
for
row
-
baseddesigns

ThetechniqueachievesnearlythefullpotentialofCR-
technique
allows
us
to
employ
CR
-
MTCMOS
for
row
-
baseddesigns

ThetechniqueachievesnearlythefullpotentialofCR-
MTCMOSintermsofsavingswitchingenergyduring
modetransitions(ideal50%,inpractice44%)
MTCMOSintermsofsavingswitchingenergyduring
modetransitions(ideal50%,inpractice44%)
23
Backup Slide: Recursive Admittance
C
C
alculation
24