Lecture7.1 Transistor

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Nov 2, 2013 (3 years and 10 months ago)

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Lecture 7.1

Device Physics


Transistor

Integrated Circuit


Transistor


Bipolar Transistor


Discrete device


On Chip


Field Effect
Transistor (FET)


On Chip


Uses


Amplify a signal


Operational
Amplifier


Switch


On/Off


Process and store
binary data


Switch

Bipolar Transistor


Combination of
two back
-
to
-
back
p
-
n junctions


P
-
N
-
P


or


N
-
P
-
N

Bipolar Transistor

Circuit Configurations

Single PN Junction


-
Constant Gate Voltage

Amplify Input Voltage Signal

Gain

Amplifier Gain


Common
-
base configuration current
gain



=1
-
(W
b
/L
p
)2
/2 ~ 1 (slightly less than 1.0)


W
b

= width of base minus depletion regions


L
p
= diffusion length of holes in the base.


Voltage Gain



ce
=

/(1
-


)(valuesro洠400to600)


FET
-

(Field Effect Transistor)


MOSFET


Metal oxide
semiconductor
field effect
transistor


IGFET


Insulated
-
gate FET


NMOS or PMOS


MISFET


Metal
-
insulator
-
semiconductor FET


MOST


Metal
-
oxide
semiconductor
transistor



JFET


Junction FET

MOSFET in Memory Chip

Source


Gate


Drain

Field Effect Transistor (FET)

Voltage Controlled Resistor

Inversion Zone
-

Poisson’s Eq.



2
U =
-





o

)


Metal on


N Zone




P Zone


n
=
-

e N
d



-

p
=+ e N
a


Boundary Conditions


U=U
o

at x=0


U=0 V at x=



Inversion Layer

Electron Tunneling


Electron Transmission, T, through
thickness,
δ.







U=Potential Energy of Barrier


E=Total Energy of Electron

Integrated Circuits


CPU or Memory


First Layer


Transistors


Capacitors


Diode


Resistors


Multi
-
layer


Wiring


Interconnects


Bonding Pads


Dielectric


Capacitors


Heterostructures

Transistor Switching Speed


PNP vs NPN


N channel is Faster
-

NPN


Mobility of n (electron is faster than hole)


Much Lower Switching Power


Complementary
MOS


N channel
connected to P
channel


10
6

less power for
switching


1 pnp acts as
amplifier


2
nd

npn does the
switching



V
T

IS LESS for
Complementary Transistor

Integrated Circuit


(Gordon E.)
Moore’s
Law,

1965


Doubling of transistor
density every year!


Doubling of computer
speed in 18 months


Doubling of computer
size in 18 months


Substantial decrease
in price with time


Price of transistor is
10
-
6
of original price



http://developer.intel.com/update/archive/issue2/focus.htm

Good for the next 20 years!

By 2012


1 Billon Transistors/die


10 Ghz!

Limitations by 2017 (gate Thickness)

Size of Transistor

5 layers of Metalization

$1B/acre

Scaling Parameter = S >1


Linear Dimension L
1

L
1
/S


Reduce all linear dimenstions by 1/S


Reduce voltage by 1/S


Increase doping Concentrations by S


Decrease time for electron to cross gate


t = L
1
/V
drift


t⽓Ⱐ†V
drift
= eE


e

,


=relaxat楯n
time


Power Dissipated per transistor


P = I V


(I⽓)(V⽓)

P⽓
2


Computer Speed


Switching Time


Time to take an
electron across a
gate


t = L/V
drift


V
drift
= eE


e

,


=r敬慸a瑩on瑩me


t

t⽓



RC delay time of
Interconnects


Resistance


R=


䰯L


R=


L*匯A/
2




3


Capacitance


C=

o
A/d


C
=

o
(A/S
2
)/(d/S)


C/S


RC


R䍓
2



Copper Wiring/Low K dielectric


Pentium IV


S < 0.18
μm



Clocks @
>2.0 Ghz

What a Memory Chip Looks Like

DRAM memory Array


Memory Chip


First Layer


Transistors


Multi
-
layer


Wiring


Interconnects


Bonding Pads


Dielectric


Capacitors


Dielectric

Reading and Writing


Think of a memory chip as a grid
or array of capacitors located at
specific rows and columns. If
we choose to
read
the memory
cell located at row 3, column 5,
we will retrieve information from
a specific capacitor. Every time
we go to row 3, column 5, we
will access or address the same
capacitor and obtain the same
result (1) until the capacitive
charge is changed by a write
process.


DRAM Memory Cell

1 Bit

Capacitor

Gate or
Row Line

Column Line

READ

WRITE