Lateral High-Speed Bipolar Transistors on SOI for RF SoC Applications

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1376 IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.52,NO.7,JULY 2005
Lateral High-Speed Bipolar Transistors
on SOI for RF SoC Applications
I-Shan Michael Sun,Student Member,IEEE,Wai Tung Ng,Senior Member,IEEE,Koji Kanekiyo,Takaaki Kobayashi,
Hidenori Mochizuki,Masato Toita,Hisaya Imai,Member,IEEE,Akira Ishikawa,Member,IEEE,Satoru Tamura,and
Kaoru Takasuka,Member,IEEE
Abstract—This paper introduces a novel silicon-on-insulator
(SOI) lateral radio-frequency (RF) bipolar transistor.The fab-
rication process relies on polysilicon side-wall-spacer (PSWS) to
self-align the base contact to the intrinsic base.The self-aligned
base and emitter regions greatly reduce the parasitic components.
In this unique design,the critical dimensions are not limited by
lithography resolution.With the control of the SOI filmthickness
or SWS width,the device can be optimized for higher speed,gain,
breakdown,or current drive capability.Furthermore,with no
additional mask,both common–emitter and common–collector
layout configurations can be realized,providing more flexibility
to the circuit design and more compact layout.The experimental
￿￿ ￿
of the high-speed device are 17/28 GHz,the second
fastest reported
for lateral bipolar junction transistors (LBJT)
so far.As for the high-voltage device,the measured
￿￿￿
of
12/30 GHz and BV
￿￿ ￿
of over 25 V produces a Johnsons product
well above 300 GHz
V.This figure is currently the closest reported
data to the Johnsons limit for lateral BJTs.This technology can
easily be integrated with CMOS on SOI.Therefore,it is feasible to
build fully complimentary bipolar and MOS transistors on a single
SOI substrate to form a true complementary-BiCMOS process.
This silicon-based lateral SOI–BJT technology is a promising
candidate for realizing future RF SoC applications.
Index Terms—BiCMOS integrated circuits,lateral bipolar junc-
tion transistors (LBJTs),microwave transistors,radio-frequency
(RF) system-on-chip (RF SoC),silicon bipolar transistors,silicon-
on-insulator (SOI)technology.
I.I
NTRODUCTION
U
NPRECEDENTED growth in wireless communications
prompted the need for smaller and faster transistors.This
sparks tremendous research effort in the development of better
radio-frequency (RF) IC technologies [1]–[3].In this cost-
competitive industry,its often beneficial to integrate as many
subsystems on silicon as possible.If technology and economics
Manuscript received August 31,2004;revised November 25,2004.This work
was supported in part by Asahi Kasei Microsystems,in part by the Natural Sci-
ences and Engineering Research Council of Canada,and in part by the Univer-
sity of Toronto Fellowship and Ontario Graduate Scholarship for Science and
Technology.The review of this paper was arranged by Editor A.Wang.
I.-S.M.Sun and W.T.Ng are with the Edward S.Rogers,Sr.Department of
Electrical and Computer Engineering,University of Toronto,Toronto,ONM5S
3G4,Canada (e-mail:suni@vrg.utoronto.ca;ngwt@vrg.utoronto.ca).
K.Kanekiyo,T.Kobayashi,H.Mochizuki,M.Toita,H.Imai,A.Ishikawa,
S.Tamura,and K.Takasuka are with Asahi Kasei Microsystems Company,
Ltd.,Tokyo 160-0023,Japan (e-mail:kanekyo.kc@om.asahi-kasei.co.jp;
kobayashi.tcc@om.asahi-kasei.co.jp;mochi@chikyu.asahi-kasei.co.jp;himai
@chikyu.asahi-kasei.co.jp;toita.mb@om.asahi-kasei.co.jp;ishikawa@dc.ag.
asahi-kasei.co.jp;satoru@dc.ag.asahi-kasei.co.jp;takasuka@dc.ag.asahi-kasei.
co.jp).
Digital Object Identifier 10.1109/TED.2005.850676
continue to improve,soon it is possible to integrate the entire
RF systemon a single chip [system-on-chip (SoC)] [4].
For silicon-based technology,both CMOS and bipolar de-
vices have made great progress in high-frequency performance
to stay competitive for high-speed and RF applications.The
state-of-the art n-MOSFETs and SiGe-HBTs can achieve cutoff
frequency
above 100 and 200 GHz,respectively [2]–[6].
To effectively utilize both types of devices,one popular ap-
proach is to develop BiCMOS processes that allow more flex-
ibility and integration of more complex circuits on the same
chip [1],[3],[7].However,such processes are becoming in-
creasingly more expensive,since the lithography resolution is
scaled to make smaller and faster CMOS devices.Furthermore,
the number of masks has increased due to the incorporation of
the SiGe HBT,as well as the additional passive RF components.
The wafer cost increases by approximately 1.3 times for each
generation of lithography advancement.Therefore,the cost for
implementing the state-of the art 0.13-
mSiGe BiCMOS could
easily be more than a fivefold increase when compared to an
older 0.35-
mprocess.Certainly,the cost will be astronomical
for a 90- or 70-nmlithography process.Such a high processing
cost is a major obstacle to overcome for the drive toward RF
SoC [1].
For SoCapplications,silicon-on-insulator (SOI) is the choice
for the substrate since it offers the ultimate isolation,reduced
crosstalk,and substrate noise [8],[9].Also,the use of SOI sub-
strate will improve the performance of passive components such
as inductors and capacitors.CMOStransistors on SOI also enjoy
the added improvement in speed due to the reduction of par-
asitic capacitances [6].However,integrating SiGe HBT with
SOI-CMOS is a difficult task since the vertical bipolar struc-
ture requires the SOI layer to be at least a fewmicrometers [10]
thick.Although IBMhas demonstrated SiGe-HBTs on thin-film
SOI,their performance is not nearly as good as those built on sil-
icon substrate [11],[12].The additional cost of the SOI wafers
makes such BiCMOS process even less attractive.
A more interesting yet economical alternative is to design
lateral bipolar structure,such that the current will flow in the
same horizontal plane as the CMOS transistors [8],[13]–[16].
This configuration will allow the tuning of the SOI layer to op-
timize the CMOS devices,without degradation of bipolar de-
vice performance.In fact,one theoretical study points out that
SOI lateral bipolar transistor can effectively reduce parasitic
and improve
and
.SOI SiGe Lateral HBTs can the-
oretically achieve
of over 500 GHz,exceeding current
0018-9383/$20.00 © 2005 IEEE
SUN et al.:LATERAL HIGH-SPEED BIPOLAR TRANSISTORS ON SOI 1377
Fig.1.Three-dimensional cross section view of the PSWS LBJT.
state-of-the-art vertical HBT [17].Previous work has demon-
strated cost-effective integration of lateral BJT with minimal
number of additional masks.However,there have been only a
few successful demonstrations of lateral bipolar transistors that
are fast enough for most RF applications.
in the range of
4–15 GHz has been reported in [13]–[16],and the maximum
achieved was 67 GHz with the use of cobalt silicide base
contact [15].Comparatively,vertical BJTs in mass production
generally operate with
at around 20/30 GHz.
In this paper,a novel lateral bipolar transistor that exhibits
similar performance when compared to its vertical counterpart
is described.This design uses polysilicon side-wall-spacer
(PSWS) to form the base contact,circumventing the problem
of aligning the contact mask to the thin base region.This side
wall spacer allows self-alignment of the base/emitter region,
which is a norm in vertical bipolar processes.In combination
with greatly reduced base resistance and junction capacitance,
this device exhibits improved
and
.The PSWS-LBJT
is compatible with SOI-CMOS and other novel CMOS devices
such as the FinFET [18].In this paper,the structural concept,
and fabrication sequences of the PSWS-LBJT are presented.
The measured electrical characteristics of the fabricated devices
are compared to previously published LBJTs.
II.D
EVICE
S
TRUCTURE AND
P
ROCESS
The three-dimensional (3-D) view of the proposed PSWS
LBJT is as shown in Fig.1.The emitter,base,and collector re-
gions are laterally formed on a SOI substrate.The emitter area
of the LBJT is defined by the width of emitter
and the
silicon layer that is equivalent to the emitter size
.The pro-
posed PSWS technology enables two important features in our
LBJT design.The first key feature is that the extrinsic and in-
trinsic base is connected via the p-type doped PSWS.Conse-
quently,this makes possible the second feature that the emitter
and base can be laterally self-aligned to dimensions less than
the lithography resolution.
In previously published lateral BJTdesigns,the extrinsic base
(p-type polysilicon or p-type diffusion) comes into contact with
both the intrinsic base and the collector region.This caused
undesirable increase in base-collector capacitance,but cannot
be avoided due to the limitation of mask alignment.In our de-
sign,such capacitance is reduced by the introduction of a thick
layer of isolating base-oxide.The intrinsic base is contacted via
the low resistive poly-side-wall-spacer (PSWS) and the base-
poly (as shown in Fig.1).Since this PSWS can be controlled
to be within 100-nm wide (comparable to the contact size of
state-of-the-art 90-nm process) and is self-aligned to the in-
trinsic base,the parasitic capacitance at the base can be mini-
mized.For all LBJTs,the base width is defined by the lateral
width of the p-base region.In conventional design,the base
width is often limited by the minimum tolerance of the mask
alignment.It is difficult to produce a well-controlled base width
that is small enough to yield high operating frequency.The
advantage of our design is that the base and emitter implants
are self-aligned with the formation of the PSWS and nitride
side-wall-spacer (NSWS).With this technique,it is possible to
self-align base/emitter to less than 0.15
m,and produce a base
width that is ideal for RF BJTs.
Another variation of this design is the fact that the base can be
implanted prior to or after the PSWS formation to make high-
voltage (HV) or high-speed (HS) versions of the LBJT.Both
devices are implemented on the same wafer to demonstrate the
tailoring of more specific device performance.This lateral BJT
technology is fabricated with AKMs standard 0.35-
m CMOS
lithography process.The process starts with a unibond SOI sub-
strate,as shown in Fig.2(a).The thicknesess of the SOI/box
oxide are 190/400 nm,respectively.The SOI filmis p-type and
is lightly doped to
cm
.The process flow is described in
detail below.
A.Extrinsic Base Stack
After depositing the initial field oxide (IFO),the entire wafer
is implanted with phosphorus at an energy of 120 keV.The en-
ergy is selected such that phosphorus can fully penetrate the SOI
film and with no p-type region remains at the SOI/Box-Oxide
interface.This implantation forms the lightly doped collector
(LDC) region.A dose level of 2
cm
is used to pro-
duce a LDC concentration of roughly
cm
.Following
the removal of the IFO,200 nm of oxide (refer hereafter as
base–oxide) and 350 nmof undoped polysilicon (refer hereafter
as base–poly) are deposited.This is followed by a boron im-
plant (dose of 5
cm
) to forma highly doped base–poly
to minimize the extrinsic base resistance.Thermal annealing at
950
C for 30 s is applied to drive-in dopant in both the LDC
and base–poly regions.
An additional 200 nm of oxide (refer hereafter as top-oxide)
is deposited on top of the base–poly.The first lithography mask,
poly–base mask (PBS),defines the lateral base–emitter regions,
by etching away all three pre-deposited layer and exposing the
SOI film.The structure after the PBS photolithography and the
pursuing etching steps is as shown in Fig.2(b).Note that the left
side of structure is truncated for simplicity,but in fact,it has the
exact mirrored structure to the drawn schematic.
B.HV/HS Base Implant and PSWS Formation
The second mask is applied to expose the active regions for
the HV device.The first base implant is used to form the base
region for the HV device.Double implant of BF
(120 keV,
7
cm
) and Boron (50 keV,5
cm
) are used
to produce a uniform doping profile across the entire depth of
1378 IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.52,NO.7,JULY 2005
Fig.2.(a) PSWS LBJT process started on SOI substrate.(b)–(f) Mirrored
cross sections (divide at collector) are as shown.(b) The structure undergoes
n-LDC implantation,base–stack forming with first mask.(c) HV implant to
define HV p-base.Polysilicon deposition and 45
tilt implantation.(d) Etch-
back to form PSWS,and HS implant to define HS p-base.(e) COP mask to
open collector SOI region.NSWS is formed with etch-back technique followed
by collector/emitter implant (f).(g) The completed full structure,including
salicidation process,BPSG deposition,contacts,and metal processing.
the SOI,thus insuring that the base region has a relatively con-
stant lateral doping profile.Unlike the default 7
tilt for con-
ventional implantation,this implant uses 0
tilt to minimize any
shadowing effect [19].This is necessary since 7
tilt implant
will offset the equal amount of dose intended for all four vertical
base regions,and produce inconsistent base widths.However,in
the actual fabrication its difficult to achieve perfect 0
implanta-
tion.Small nonzero angle implantations can be used to fine-tune
the process for better process yield.The SIMS data for the HV
implant is as shown in Fig.3.Note that the dopant concentra-
tion remains constant over the entire junction depth.Essentially,
the HV base region is aligned to the base–poly stack.After re-
moving the photoresist,100 nmof undoped polysilicon are de-
posited across the entire wafer.The polysilicon is doped with a
45
tilted shallow implant of boron (
cm
,20 keV) and
BF
(
cm
,80 keV),in order for sufficient dopant to pen-
etrate into the sidewalls attached to the base–poly stack.Since
Fig.3.SIMS impurity profile for HS/HV boron implantation.
all four side-planes are encircled with polysilicon sidewalls,the
implantation is done at four incidence angels (0
,90
,180
,
270
) to dope every sidewall.At this stage,the planar part of
the polysilicon film,both on top of the top-oxide and SOI,are
still connected as shown in Fig.2(c).
RTA is applied to activate the implanted dopant in the
polysilicon,as well as allowing p
out-diffusion into the SOI
layer to reduce poly-Si contact resistance.After PSWS an-
nealing,anisotropic etch-back is used to remove 100 nm (with
10% overetching) of polysilicon covering any oxide or silicon
region.This leaves only the vertical part of the filmuntouched,
and thus forming the final shape of PSWS.This is a similar
technique used to make Nitride SWS in CMOS devices [20].
The second base implant is used to formthe base region for the
HS device.Double implant of BF
(120 keV,1.5
cm
)
and Boron (50 keV,
cm
) with 0
tilt are used.The HS
region is self-aligned to the PSWS,which is different from the
case for HV device.The SIMS data for the HS implant is as
shown in Fig.3.The cross-sectional diagram is as shown in
Fig.2(d).Although the physical structure is the same for both
HV/HS devices,the location of the base region is different.The
HV implant is aligned to the edge of PBS mask,while the HS
implant is aligned to the PSWS.
C.Open Collector Region and NSWS Formation
The third mask [collector open (COP) mask] defines the
highly doped collector.After this photolithography step,
etching through the base–poly stack exposes the designated
collector region of the SOI.It is important to note that this mask
defines the final width of the base–poly as well as the width of
LDC region.This width is chosen specifically to tradeoff speed
with breakdown voltage.During the etching of the base–poly,
the SOI layers that are not cover by either this mask or the
base–poly will be simultaneously removed.Note that PBS and
COP masks are designed so that the collector/emitter regions
have sufficient area to accommodate at least one contact hole.
The redundant areas outside of collector/emitter are purposely
moved by this technique for device isolation.The removal of
the unmasked SOI layers isolates all devices without the use
of any additional mask or process techniques,such as deep or
SUN et al.:LATERAL HIGH-SPEED BIPOLAR TRANSISTORS ON SOI 1379
shallow trench isolation for vertical BJT.After removing the
photoresist,150 nm of nitride is deposited.This is then etched
back with 10%overetching to form the NSWS (130 nm wide).
This NSWS exists adjacent to the PSWS (emitter side) and
the base–poly (collector side).Fig.2(e) illustrates the structure
after NSWS formation.
D.Collector/Emitter Formation
The collector and emitter are formed simultaneously by
double implantations of arsenic (40 keV,
cm
) and Phos-
phorus (90 keV,5
cm
).The arsenic implant reduces
the contact resistance fromthe metal to the SOI layer.The phos-
phorus implant defines the active concentration of the collector
and emitter.The emitter region is self-aligned to the NSWS,
which in turn is aligned to PSWS and to the base–poly stack.
Therefore,the emitter region is self-aligned to the p-base of
both the HV and HS devices.For vertical BJTs,the depth of
the emitter and base regions are defined by implant energy and
vertical diffusion.In this device structure,the base profile is
precisely tailored by the thickness of the PSWS and NSWS.
After the n-type implantation,30 s of RTAis applied at 950
Cto
activate all the dopants,while keeping all lateral diffusions to a
minimumin order toachieve more abrupt profile for the base and
emitter junction.A more box-like or abrupt junction is the key
to minimize the base width and improve transistor speed.The
cross-sectional diagramat this stage is as shown in Fig.2(f).
E.TiSi
Formation and Contacts
Prior to salicidation,the base–poly need to be exposed by
removing the top-oxide.However,etching the top oxide also
remove the same thickness on the BOXoxide.It is important to
choose a thin top-oxide such that the BOX oxide is not totally
etched away and exposing the silicon substrate.Titanium is
sputtered and annealed to form self-aligned titanium silicide
TiSi
across all exposed silicon and polysilicon areas,any
unreacted titanium is subsequently removed.Note that due
to the trench etching in step C,no TiSi
is formed above the
trench region and thus all devices are isolated.A thick layer of
borophosphosilicate glass (BPSG) is then deposited.Contact
holes are opened with the contact (CNT) mask.Note that the
lateral lengths of the base–poly,emitter and collector regions
are limited by the lithography resolution to accommodate at
least one contact hole.A thick layer of aluminum is sputtered
and the metal mask is used to define the metal pattern.The
final completed structure is as shown in Fig.2(g),including
the mirrored side of the device that is not shown previously.In
Section III,a novel 3-dimensional design concept that is unique
for the PSWS LBJT will be discussed.
III.L
AYOUT
D
ESIGN
The proposed PSWS LBJT can be realized in two distinc-
tive configurations.For common-emitter (C–E) configuration,
the emitter encircles the base,and the base encircles the col-
lector.The emitter is accessible fromeveryplanar direction,thus
two transistors can be connected together by sharing the outer
emitter regions (thus common–emitter).The common–collector
(C–C) configuration is the reversal of the collector and emitter
Fig.4.Layout of device with both C–E and C–C configurations using PBS
and COP mask,with the corresponding 3-D structures of the PSWS LBJT.
regions in the C–E layout,where the collector en-circles the
base,and the base encircles the emitter.The layout schematic
and the 3-Dcross-sectional vieware as shown in Fig.4.The ver-
tical cross-sectional area of the SOI underneath the inner/outer
edge of the base–poly stack for the C–C/C–E type device is the
equivalent of the active area as in the conventional BJTs.
This proposed layout design has two notable features.Since
the base–poly and the PSWS in both vertical planes (
-
,
-
plane) are physically made identical,the horizontal cross sec-
tion in any direction is almost identical.Only at the corners,the
PSWS may be slightly thicker.Consequently,since there are no
dead-zones (areas that are not used for conduction of current),
this significantly reduces the three dimensional parasitic junc-
tions existed in traditional vertical or other lateral designs.Also,
the ratio of
is almost equals to unity.In vertical designs,
the ratio is anywhere between 0.5–0.8.
The second feature is that since the current flows horizon-
tally,the length and width of the poly-base controls the amount
of conduction current as in CMOS transistors.In CMOS,the
current multiplication factor is defined as
,but in the
case of the PSWS LBJT,it is simply the circumference of the
emitter area,which is
.Since all four planes are
used for current conduction,more current can flow through the
device per chip area.In fact,this is the first bipolar transistor
that allows current flow in more than one-plane.Similar mul-
tiple-plane concepts for current conduction are being realized
in FinFET and other cutting-edge CMOS devices [19],[21].
All these translate into several advantages;higher current
drive,smaller chip area,more design flexibility and compact-
ness.For comparison purposes,we use a conventional 0.35-
m
BJT process as an example.A typical RF BJT transistor in
such process has
of 2
m
(4
0.5),and the active area
needed for such BJT is around 80
m
.For an equivalent
,the PSWS BJT only requires an active area of 40 with
0.19
m of SOI thickness.Naturally,as the thickness of the
SOI layer decreases,this advantage will disappear,but thin-film
SOI are generally used for low power applications,and the
current drive can be designed accordingly to fit the needs of
lowpower.For circuit designers,there is more flexibility to size
transistors similar to CMOS.Also,with the availability of both
C–E/C–C type configurations,its possible to connect devices
through sharing of collector or emitter areas.This enables more
compact designs with less interconnect parasitic.
1380 IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.52,NO.7,JULY 2005
Fig.5.SEMmicrograph of a PSWS LBJT in C–C configuration.
IV.PSWS LBJT S
TRUCTURE AND
I
NTEGRABILITY
An SEMmicrograph of the fabricated PSWS LBJT structure
in C–Cconfiguration is as shown in Fig.5.The PSWS is formed
vertically against the poly-base stack,and is sandwiched by the
NSWS on both sides.The PSWS connects the base–poly and
the p-base regions.The emitter,collector,and base diffusion
regions are as indicated in the figure.Due to the over etching
process required to formboth the PSWS and NSWS,slight over
etching of the SOI is observed.Also,the salicidation process
that forms TiSi
(as shown in the black area in Fig.5) consumes
some additional silicon.Therefore,the SOI layer thickness at
the collector/emitter area is much thinner.
The advantage of this process is the elimination of trench iso-
lation,epitaxy and the
buried layer in common vertical BJT.
Only five masks are required to make the LBJT structures,in-
cluding one to separate HS and HV devices.This is the lowest
of all vertical or lateral BJTs.One additional mask can be saved
if only one type of device (HS or HV) is needed,and both
C–E/C–C layout configurations can be implemented.The de-
vice is self-isolated in this process,therefore no trench isolation
process is needed.
The PNP bipolar and CMOS transistors can also be imple-
mented to create full complimentary BiCMOS process.One ad-
ditional mask is needed to shield the NPN device during the
PNP device processing.As for CMOS integration,one can ob-
serve that the PSWS-BJT as shown in Fig.5 resemble a con-
ventional CMOS structure.Other than the PSWS and a much
thicker gate-oxide,these structures are almost identical,opening
up the possibility of fully compatible CMOS integration.Due
to the similarities in the MOSFET and LBJT fabrication,our
LBJT design has the advantage that base-with-gate topology is
possible.A multigate-oxide process is used to obtain different
thicknesses for both the gate/base–oxides.The same poly can
be subsequently deposited to form the gate/base–poly for the
CMOS/bipolar.An extra blanket mask is needed to make sure
the PSWS only forms on the LBJT,not the CMOS devices.The
rest of processing can be designed effectively to minimize mask
usage and processing steps,as described in our earlier work
[22].
Similar to SiGe HBT BiCMOS technology,the base-after-
gate topology can also be used to integrate both LBJT and
TABLE I
S
UMMARY OF
D
EVICE
P
ERFORMANCE FOR
HS/HV T
RANSISTORS
CMOS.The CMOS gate structures can be first constructed,
followed by a blanket mask that covers the CMOS regions.The
LBJT is then constructed on the unmasked regions,followed
by removal of the blanket mask and thermal annealing for both
bipolar and CMOS devices.Comparatively,the advantage of
base-with-gate topology results in the reduction in cost and pro-
cessing time,but the bipolar/CMOS transistor characteristics
are compromised by this simplify process.The base-after-gate
topology has the advantage of more flexibility for device
optimization at the cost of more mask layers and processing
steps.Nevertheless,both topologies can fulfill the need for full
BiCMOS integration.
V.E
LECTRICAL
C
HARACTERISTICS
The electrical properties of the fabricated PSWS LBJTs,both
HS/HV versions,with both C–C and C–E configuration were
measured.Since C–Cand C–E devices exhibit similar property,
only the active areas are different due to layout,we will mainly
focus on the C–E type devices.The performance of both HV
and HS devices are summarized in Table I.As the results of
PSWS self-aligned base/emitter and reduced parasitic elements,
the
of the HS device reaches 17 GHz,the second highest
for LBJT reported so far.Also,the HV device achieves
and BV
of 12 GHz and 27.5 V.This produces a Johnson’s
product of 330 GHz
V.The value of BV
is the highest for
devices that operate above 10 GHz,and the Johnsons product
matches the theoretical limit of 320–340 GHz
V.Note that the
BV
for HS device is much smaller than HV device,this is
caused by premature punchthrough breakdown due to the thin
base used to push for higher speed.
The Gummel plots for both the HS and HVtransistors in C–E
configuration are as depicted in Fig.6.The active areas for the
HS and HV devices are 2.28 and 2.85
m
,respectively.Fairly
good voltage-current BJT characteristics are observed.A com-
parison of the voltage-current characteristics of C–C and C–E
configuration is as shown in Fig.7.The active areas of the cor-
responding C–C type devices are 3.8 and 5.7
m
,respectively.
It is clear that the Gummel plot for C–C and C–E devices scale
nicely with respect to the size of the active area.The typical
output characteristics
-
of the PSWS LBJT is as shown
in Fig.8.Due to the thin base of the HS device,the
is only
4 Vcompare to 12.6 Vfor the HVdevices.The three breakdown
characteristics of the transistor,BV
,BV
and BV
are as shown in Fig.9.Although the BV
is lower for HS
devices,its sufficient for systems that operate at 2–3 V supply.
Ironically,the BV
of the HV device is too high for most
SUN et al.:LATERAL HIGH-SPEED BIPOLAR TRANSISTORS ON SOI 1381
Fig.6.Gummel plot of the HS and HV NPN transistors at
￿
￿ ￿
V.
Fig.7.Gummel plot comparison of the C–C and C–E type configuration,
showing current scaling due to size of active area.AE of HSCC,HSCE,HVCC,
and HVCE devices are 2.28,3.8,2.85,and 5.7
￿
m
,respectively.
Fig.8.Output characteristics of HS and HV transistors
￿￿ ￿
￿ ￿ ￿
A
￿
.
RF applications.With adequate base optimization,such as re-
ducing PSWS thickness for thinner base width or reducing base
implant dose for lower base doping,BV
can effectively be
tradeoff for increasing
and
,while maintaining similar
Fig.9.Breakdown voltage characteristics of the HS and HV transistors.
Current is limited at 1
￿
A.
Fig.10.Cutoff frequency
￿ ￿
￿
and maximum oscillation frequency
￿ ￿
￿
versus collector current
￿ ￿
￿
at
￿
￿ ￿
V for HV and HS transistors.
Johnsons product.The S-parameters of the transistors were eval-
uated from200 MHz to 15 GHz.The
is calculated fromthe
extracted
parameter.The
is calculated from the uni-
lateral power gain.The
-
and
-
characteristics for
both transistors are as plotted in Fig.10.Peak
and
of
17 and 28 GHz are reached at
of 0.4 mA for the HS device.
At similar current level,peak
and
of 12 and 30 GHz
are achieved for the HV device.
VI.C
ONCLUSION
A novel concept for fabricating CMOS-compatible lateral
BJT on SOI is developed.This technology requires simple
PSWS structure and only five lithography masks to realize
high-performance lateral BJTs.A novel layout methodology is
used to form area efficient devices in both C–E and C–C con-
figurations,thus increasing design compactness and flexibility.
This is the first functional bipolar transistor that has emitter
current injection in multiple planes,an idea that is currently
being explored by cutting-edge CMOS devices.
The electrical characteristics are measured and summarized
in Table II,with comparison data from previously published
1382 IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.52,NO.7,JULY 2005
TABLE II
S
UMMARY OF
P
ROCESS AND
P
ERFORMANCE OF
PSWS LBJT C
OMPARED
W
ITH
P
REVIOUSLY
P
UBLISHED
LBJT
S
Fig.11.BV
versus
￿
tradeoff for RF bipolar transistors.Johnsons limit
(dashed line) corresponds to BV
￿ ￿
product of 340 GHz
￿
V.
LBJTs.Notably,the external base width
WB
is not lim-
ited by photolithography,and a minimum width of 0.1
m is
achieved.This novel PSWS design greatly reduces parasitic ca-
pacitance that translates into higher frequencyperformance.The
measured
of 17 GHz is the second highest reported and
of around 30 GHz is fairly high considering the fact that no ex-
otic base material is used [15].The Johnsons product for the
HV device is the highest reported for silicon BJT (depicted in
Fig.11),exceeding not only lateral BJTs but vertical BJTs that
incorporate smaller lithography and epitaxial base process as
well.Only the most advanced SiGe-HBT processes can achieve
Johnsons product of above 400 GHz
V.By improving the base
resistance and optimize the base doping,even higher
can be obtained.This lowcost bipolar is suitable for SOI-CMOS
integration,and an ideal BiCMOSprocess for future RFSoCap-
plication.
A
CKNOWLEDGMENT
The authors wish to thank all the engineers at the Process
Development Group of AKM,Nobeoka,Japan for their support
in the device fabrication,as well as AK Fuji Analytical Lab for
SIMSand SEManalysis.I.S.M.Sun would like to thank D.Lee
and E.Xu at the VLSI Research Group,University of Toronto,
for their support in device design and simulation.
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SUN et al.:LATERAL HIGH-SPEED BIPOLAR TRANSISTORS ON SOI 1383
I-Shan Michael Sun (S’99) was born in Taiwan,
R.O.C.,in 1976.He received the B.ASc.and M.ASc.
degrees in electrical and computer engineering from
the University of Toronto,Toronto,ON,Canada,in
1999 and 2002,respectively,where he is currently
pursuing the Ph.D.degree.
In the summer of 1998,he worked at Philips
Semiconductors,Caen,France,as an Undergraduate
Intern.Since 2000,he has been collaborating with
Asahi Kasei Microsystems Company,Ltd,Tokyo,
Japan,working on the development of CMOS-com-
patible Si/SiGe homo/heterojunction bipolar transistors.His current research
interests are in radio-frequency semiconductor devices and integrated circuits,
SOI-compatible BiCMOS technologies,and novel bipolar transistor structures
and design concepts.
Mr.Sun is the recipient of the Charitat Award (Best Young Researcher) at
the 17th International Symposium on Power Semiconductor Devices and ICs
(ISPSD’05).
Wai Tung Ng (M’90–SM’04) was born in Hong
Kong in 1961.He received the B.A.Sc.,M.A.Sc.,
and Ph.D.degrees in electrical engineering from
the University of Toronto,Toronto,ON,Canada,in
1983,1985,and 1990,respectively.
In 1990,he joined the Semiconductor Process and
Development Center of Texas Instruments,Dallas,
TX,to work on LDMOS power transistors for auto-
motive applications.His academic career started in
1992 when he joined the University of Hong Kong.
In 1993,he joined the University of Toronto and was
promoted to Associate Professor in 1998.He has collaborated with Asahi Kasei
Microsystems Company,Ltd,Tokyo,Japan since 2000 on various CMOS-
compatible process development.His current work covers a wide spectrum,
ranging from advanced MOS and RF BJT device designs,VLSI power man-
agement circuits,smart power-integrated circuits,and fabrication processes.
Koji Kanekiyo was born in Osaka,Japan,in 1969.
He received the B.E.and M.E.degrees in inorganic
materials engineering from Tokyo Institute of Tech-
nology,Tokyo,Japan,in 1991 and 1993,respectively.
In 1993,he joined Asahi Kasei Microsystems
Company,Ltd.,Kawasaki,Japan,where he engaged
in the research and development of lithium-ion
secondary batteries.In 2001,he joined the Process
Technology and Development Department,Tokyo,
where he has been working on the development of
bipolar transistor.
Takaaki Kobayashi was born in Tokyo,Japan,in
1957.He received the B.E.and M.E.degrees in mate-
rial synthesis engineering from Tsukuba University,
Tsukuba,Japan,in 1981 and 1983,respectively.
In1983,hejoinedAsahi Kasei Microsystems Com-
pany,Ltd.,Kawasaki,Japan,where he engaged in the
researchanddevelopment of organic semiconductors.
In 1985,he joined the Process Technology and Devel-
opment Department,where he has been working on
the development of an analog CMOS transistor.
Hidenori Mochizuki was born in Shizuoka,Japan,
in 1971.He received the B.E.and M.E degrees in ap-
plied chemistry fromthe University of Tokyo,Tokyo,
Japan,in 1993 and 1995,respectively.
In 1995,he joined the Process Technology and
Development Department,Asahi Kasei Microsys-
tems Company,Ltd.,Tokyo,where he engaged in
EEPROM research.He has been working on device
physics and process technology of bipolar transistor
by methods of electrical measurement and physical
analysis.
Masato Toita received the B.S.and M.S.degrees in
industrial chemistry from Chiba University,Chiba,
Japan,and the Ph.D.degree in engineering from To-
hoku University,Sendai,Japan,in 1987,1989,and
2004,respectively.
He joined Asahi Kasei Microsystems Company,
Ltd.,Tokyo,Japan,in 1989.From 1997 to 1999,he
was a Visiting Scholar with the Department of Elec-
trical Engineering,Stanford University,Stanford,
CA.He is currently working on the development of
BiCMOS front-end processes for high-speed wire-
less communication devices.His research interests also include mechanisms
that cause low-frequency noise in MOS transistors and reduction of that noise
by optimizing the wafer process for precision mixed-signal integrated circuits.
Dr.Toita is a member of the Electrochemical Society.
Hisaya Imai (M’92) was born in Tokyo,Japan,in
1955.He received the M.S.degree in chemistry from
Hokkaido University,Sapporo,Japan,in 1980.
In 1980,he joined the Central R&D Laboratory,
Asahi Kasei Microsystems Company,Ltd,Fuji,
Japan and was concerned with mixed-metal–oxide
chemistry and characterization.Since 1986,he
has engaged in CMOS process development for
precision analog circuits.He is currently with the
Process Technology Development Division,Tokyo,
where he is now directing development programs
for advanced analog CMOS technologies including EEPROM,high-voltage
MOSFETs,RF bipolar,and other precise analog components.
Akira Ishikawa (M’96) was born in Saitama,Japan,
in 1960.He received the B.S.and M.S.degrees
in electronic engineering from Tohoku University,
Miyagi,Japan,in 1984 and 1986,respectively.
He joined the LSI Design and Development
Center,Asahi Kasei Microsystems Company,Ltd.,
Tokyo,Japan,in 1986,working on communication
and data storage read/write channel analog LSI
design.He is currently with the Design Technology
Group and working on the research and develop-
ment of circuit simulation models for CMOS and
BiCMOS process.
Satoru Tamura was born in Yokohama,Japan,in
1958.He received the B.S.and M.S.degrees in elec-
tronic engineering fromKeio University,Yokohama,
in 1982 and 1984,respectively.
He joined the LSI Design and Development
Center,Asahi Kasei Microsystems Company,Ltd.,
Tokyo,Japan,in 1984,working on the mixed-signal
LSI design and development including process,de-
vice,and CADtools.He is currently with the Design
Technology Group and working on the research and
development of the advanced CMOS technology
including SiGe HBT-BiCMOS,high-voltage CMOS,and RF passive devices
for the mixed-signal LSI design.
Kaoru Takasuka (M’99) was born in Hiroshima,
Japan,in 1947.He received the B.S.and M.S.
degrees in instrumentation engineering from the
Kyushu Institute of Technology,Kitakyushu,Japan,
in 1970 and 1972,respectively.
He joined Asahi Kasei Microsystems,Ltd.,Tokyo,
Japan,in 1972.Since 1983,he has been engaged in
the design of customCMOS LSIs.He is currently the
Vice President-CTO.
Mr.Takasuka was a corecipient of the Award for
Technical Excellence fromthe Society of Instrument
and Control Engineers of Japan in 1986 and received the Institute of Electrical
Engineers of Japan Millennium Best Paper Award in 2001.