Lab 1 Transistors

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EECS150 Spring 2002 Lab 1 Transistors
UNIVERSITY OF CALIFORNIA AT BERKELEY
COLLEGE OF ENGINEERING
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
Lab 1
Transistors
1 Motivation
In this lab you will get to build a logic gate and a latch fromactual transistors.Additionally lab exercise will reorient
you with respect to the lab instruments.We assume that you have had basic electronics lab experience in the past,and
that in particular you have used power supplies,meters,and done simple wiring with protoboards.If not,see you TA
for extra assistance.
2 Introduction
Nearly all digital logic circuits these days are built from CMOS transistors.However,this is easy to forget,given
that most designers work at a at the gate level or higher.But the transistors themselves have a strong effect on the
performance,cost,and power consumption of these circuits.Likewise in EECS150,although the main emphasis of
this course is not transistor level design,it is important to have a rm grasp of at least the basics of transistor circuits
to be a better digital designer.
Nearly all digital logic circuits these days are built from CMOS transistors.However,this is easy to forget,given
that most designers work at a at the gate level or higher.But the transistors themselves have a strong effect on the
performance,cost,and power consumption of these circuits.Likewise in EECS150,although the main emphasis of
this course is not transistor level design,it is important to have a rm grasp of at least the basics of transistor circuits
to be a better digital designer.
The transistors we will be using come in small plastic packages with three wire leads (see gure 4).The actual
transistor is enclosed in plastic to protect it from the environment (and your hands).The leads make connection to
the source (S),gate (G),and drain (D) terminals of the transistor.The body (or bulk) of the transistor is internally
connected to the source terminal.This built-in connection is convenient for most logic circuits.However,as we shall
see later,it limits their use.The illustration below shows you the transistor pinout.It is the same for both the nFET
and pFET.Remember that the source and drain terminals are different from one another with these devices and you
need to wire themup correctly for your circuits to function.
The rst part of the lab exercise uses the standard nand gate congur ation using 2 nFETS and 2 pFETS.The second
part uses a data latch circuit similar to the one presented in class.It is modied somewhat to eliminate the"transmission
gates",since these are not possible to implement with transistors with built-in body to the source connections.For
transmission gate implementation we would need to connect the body to ground in the nFETs and to V
dd
in the pFETs.
This latch,shown in gure 2,uses two tri-state inverters and a normal inverter.The tri-state inverter used here is the
functional equivalent to an inverter followed by a transmission gate.The latch works as follows.When the clock
signal is high,the rst tri-state acts as an inverter and the input D is passed to the output Q,simultaneously the second
tri-state oats it output and thus has no effect on the state of the internal node X.When the clock is low,the input is
disconnected fromthe internal node.Meanwhile,the state of the internal node X is inverted and passed to the output
and another level of inversion through the second tri-state and back to X.Therefore the latch holds Qat whatever value
was last seen at D while the clock was high.
The transistors that we will be using operate over a wide range of voltages.For this lab,let V
dd
be 3 volts.By
keeping the supply voltage down to this low level,we will limit the currents in the circuits,letting them stay cooler,
UCB 1 2002
EECS150 Spring 2002 Lab 1 Transistors
a
b
s s
s
s
d
d
d d
out
Figure 1:NAND gate - Transistor-level
clkclk
Q
D
Figure 2:D-type transparent latch
slower,and consequently easier to measure.
3 Prelab
1.Read and understand the entire lab handout.
2.Reviewthe circuits involved in this lab.Make sure that you understand howthey are supposed to work.Drawing
the circuits out for yourself will help.
3.Make sure that you understand (remember) howprotoboards are internally connected.If you don't ask you TA.
Plan out how you will wire up your circuits on the board.With careful planning you can minimize the amount
of wiring that you will have to do in the lab,saving time and eliminating some chances for mistakes.Draw a
little sketch with the transistors in the proper places to use as a guide in the lab.
4.Think through the experiments and what you will expect to see at each step.
4 Procedure
Part I - NAND Gate
1.Wire it up.Using the standard 4 transistor nand-gate circuit discussed in class (gur e 1) as a model and your
planned layout fromthe prelab,wire up a two-input nand-gate with the discrete transistors on your protoboard.
UCB 2 2002
EECS150 Spring 2002 Lab 1 Transistors
out
en
en
in
in out
en
(a)
(b)
s
d
s
d
s
d
s
d
G
G
G
G
Figure 3:Tri-state Inverting Buffer (a) Transistor-level (b) Symbol
P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2  MARCH 94
FEATURES
* 60 Volt V
DS
* R
DS(on)
=5
ABSOLUTE MAXIMUM RATINGS.
PARAMETER SYMBOL VALUE UNIT
Drain-Source Voltage V
DS

-60 V
Continuous Drain Current at T
am

b
=25°C I
D
-280 mA
Pulsed Drain Current I
DM
-4 A
Gate Source Voltage V
GS

± 20 V
Power Dissipation at T
am

b
=25°C P
to

t
700 mW
Operating and Storage Temperature Range T
j

:T
stg

-55 to +150 °C
ELECTRICAL CHARACTERISTICS (at T
amb
= 25°C unless otherwise stated).
PARAMETER SYMBOL MIN.MAX.UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BV
DSS
-60 V I
D
=-1mA, V
GS

=0V
Gate-Source Threshold
Voltage
V
G

S(th)
-1.5 -3.5 V ID=-1mA, V
DS

= V
GS

Gate-Body Leakage I
GS

S
20 nA V
GS

=± 20V, V
DS
=0V
Zero Gate Voltage Drain
Current
I
DS

S
-0.5
-100
 A

 A
V
DS

=-60 V, V
GS

=0
V
DS

=-48 V, V
GS

=0V, T=125°C(2)
On-State Drain Current(1) I
D(

on)
-1 A V
DS

=-18 V, V
GS

=-10V
Static Drain-Source On-State
Resistance (1)
R
DS(on)
5  V
GS

=-10V,I
D
=-500mA
Forward Transconductance
(1)(2)
g
fs

150 mS V
DS

=-18V,I
D

=-500mA
Input Capacitance (2) C
iss
100 pF
Common Source Output
Capacitance (2)
C
os

s
60 pF V
DS

=-18V, V
GS

=0V, f=1MHz
Reverse Transfer
Capacitance (2)
C
rss
20 pF
Turn-On Delay Time (2)(3) t
d(

on)
7 ns
V
DD

 -18V, I
D

=-500mA
Rise Time (2)(3) t
r

15 ns
Turn-Off Delay Time (2)(3) t
d(

off)
12 ns
Fall Time (2)(3) t
f
15 ns
(1) Measured under pulsed conditions. Width=300  s. Duty cycle  2%
(2) Sample test.
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E-Line
TO92 Compatible
ZVP2106A
3-417
D
G
S
TY

PICAL CHARACTERISTICS
Output Characteristics
VDS - Drain Source Voltage (Volts)
I
D(On)

-
On-
State

Dr
ain Curr
ent (

Amps)
T

ransfer Characteristics
Normalised R
DS(on)
and V
G

S(th)
vs Temperature
Normalised R
DS(o
n)
and
V
GS(th)

-40 -20 0 20 40 60 80 120100 140 160
2.

4
2.

2
2.

0
1.

8
1.6
1.4
1.

2
1.0
0.

6
0.

8
Drain-Source Resistanc
e RDS(on)


G

ate

T

h

res

h

o

l

d

Vo

l

t

ag

e

VGS

(

t

h)


I

D=-0.

5A
0 -

2 -4 -6 -8 -100

-10 -20 -30 -40 -50
Saturation Characteristics
VDS-Drain Source Voltage (Volts)
Voltage Saturation Characteristics
V

GS-Gat

e Source Voltage (Volts)
-10V
I
D(On)
-
On-State Drain Current (Amps)
VGS-Gat

e Source Voltage (Volts)
VGS=-10V
I

D=-1mA
VGS=VDS
-3.5
-3.0
-2.0
-0.5
0
-1.0
-2.5
-1.5
2.

6
180
V

GS=
-20V
-14V
-5V
-6V
-7V
-4V
-3.5V
-8V
V

GS=
-18V
I
D(On)
-On-State Drain Current (Amps)
VDS - Drain Source Voltage (Volts)
On-resistance v drain current
ID-Drain Current (Amps)
RDS(ON) -Drain Source Resistance
()
-0.1 -1.0
10

5

-2.0
-12V
-6V
-4V
0

-2 -4 -6 -8 -10
1

-10V
-9V
-8V
-7V
-5V
-9V
0
-0.6
-0.4
-0.2
-0.8
-1.6
-1.4
-1.2
-1.0
-1.8
-2.0
0
-10
-6
-2
-4
-8
0 -

2 -4 -6 -8 -10
ID=
-1A
-0.5A
-0.25A
-0.8
-0.6
-0.2
-0.4
V

DS=-10V
-1.6
-1.4
-1.0
-1.2
-6V
-7V
VGS=-5V
-8V
-10V
-9V
T

j

-Junction Temperature (°C)
ZVP2106A
3-418
Figure 4:Pin out for pFET and nFET transistors
UCB 3 2002
EECS150 Spring 2002 Lab 1 Transistors
2.Static test of logic function.Connecting the inputs to either V
dd
for logic ONE or ground for logic ZERO,
verify that your circuit correctly implements the nand function by observing its output voltage with a voltmeter
or an oscilloscope.
3.Measure V
in
versus V
out
.Holding one input at a constant logic HIGH,measure and plot the V
in
versus V
out
relationship for the other input,with input values covering the range fromground to V
dd
.Take at least 15 data
points,focussing your effort at the region of high slope.Plot your results with MS excel.
4.Repeat for the other input.
Part II - Latch Circuit
1.Wire it up.Based on the circuit diagram shown above,and your planned layout from the prelab,wire up the
transparent data-latch.Implement one extra inverter to use to generate clock-bar.
2.Verify tri-state action and measure D-Q delay.
(a) Set the pulse generate to output a square wave with a frequency of around 100KHz and a maximumvoltage
close to V
dd
when driving the Dinput to your latch.Set the clock signal to put the latch into"transparent"
mode and verify the presence of the square wave at its output Q.
(b) Disconnect the feedback wire and verify the signal after the second tri-state,then reconnect the feedback.
(c) Measure and record the"D-to-Q"delay.
(d) Now,invert the clock signal,and verify that D (or its complement) are not present at X and Q.
3.Test latch function with"static"signals.
(a) Put the latch in transparent mode.Deassert the input.Put the latch in latch mode.Check the output while
you change the input.What do you see?
(b) Repeat with a logic ONE at the input.Is everything ok?Is it really a latch?
4.Measure clk-Q delay with high-freq clock signal.This test uses two square waves of the same frequency,one
delayed relative to the other.Our signal generators only have one output,but we can use"trigger out"as one
output and the normal output delayed as the other.The rst square wave we will use as the D signal to our
circuit,and the other delayed by 1/4 cycle as the clock.(Perhaps you should sketch this arrangement,to be
sure that you understand it).Using the oscilloscope to monitor the signals,set up the signal generator with to
generate two square waves then connect themto your circuit (one to Dand the other to clock).You will not have
control over the level of the trigger out signal,but as long as it is around 3 volts (plus or minus 1 or so),things
should be ne.Adjust the level of the other to close to 3 volts.This arrangement is what you need to measure
the clock-to-Q delay for latching a logic ONE.Use the oscilloscope to make this measurement.Now repeat for
latching a logic ZERO.You can arrange this by inverting one of the normal signal generator output.
5 Acknowledgement
Original lab by J.Wawryznek.
UCB 4 2002
EECS150 Spring 2002 Lab 1 Transistors
6 Checkoff
Name:
Name:
Section:
Part I - NAND Gate
1.Your NAND circuit.TA:
(10%)
2.Your plots of V
in
versus V
out
.One for V
in
=ONE and another for V
in
=ZERO.TA:
(10%)
Part II - Latch Circuit
1.Your latch circuit.TA:
(30%)
2.The measured D-to-Q delay
TA:
(10%)
3.The clock-to-Q delay for logic ONE
TA:
(10%)
4.The clock-to-Q delay for logic ZERO
TA:
(10%)
5.Your setup (including scope waveforms) for measuring the clock-to-Q delay.TA:
(20%)
Total
50%off if the lab is handed in 1 week late TA:
(-50%)
Total Score TA:
(100%)
UCB 5 2002