Encountering Gate Oxide Breakdown with Shadow Transistors to Increase Reliability

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Nov 2, 2013 (4 years and 5 days ago)

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1

Encountering
Gate Oxide Breakdown
with

Shadow Transistors
to
Increase Reliability


Claas Cornelius
1
,
Frank Sill
2
, Hagen Sämrow
1
, Jakob Salzmann
1
,
Dirk Timmermann
1
,
Diógenes Cecílio da Silva Jr.
2



1
University of Rostock, Germany

2

Federal University of Minas Gerais (UFMG), Brazil



Gramado, 3
rd

September 2008

2

Cornelius et. al: Shadow Transistors

Focus / Main ideas


1.
Reliability regarding oxide breakdown

2.
Transistor / Gate level approach

3.
Selective insertion / thick oxide devices



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Cornelius et. al: Shadow Transistors

Outline


Motivation


Technology development


Error classification


Time
-
Dependent Dielectric Breakdown (TDDB)


Shadow Transistors


Used model


Main Ideas


Algorithm


Results


Conclusion

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Cornelius et. al: Shadow Transistors

Probability for failures increases due to:


Increasing transistor count


Shrinking technology

0
100
200
300
400
500
2002
2004
2006
2008
Transistors [Mill.]

Year

130 nm

90 nm

65 nm

45 nm

0 nm
50 nm
100 nm
150 nm
0
100
200
300
400
500
2002
2004
2006
2008
Technology

Transistors [Mill.]

Year

Motivation

Technology development

Northwood

55 Mill.

Prescott

125 Mill.

Yonah,

151 Mill.

Wolfdale

410 Mill.

Yonah

151 Mill.

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Cornelius et. al: Shadow Transistors

Motivation

Error classification

Error

Permanent

Temporary

Soft errors, Voltage
drop, Coupling, …


Reduced Performance

Process variations, Electro
-
migration, Oxide wearout ...

Malfunction

Electromigration,
Oxide breakdown ...

Oxide
wearout

Oxide
breakdown

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Cornelius et. al: Shadow Transistors

Motivation

Time
-
Dependent Dielectric Breakdown (TDDB)


Tunneling currents




Wear out of gate oxide


Creation of conducting path
between Gate and Substrate,
Drain, Source


Depending on
electrical field

over
gate oxide,
temperature

(exp.)
,
and
gate oxide thickness (exp.)


Also: abrupt damage due to
extreme overvoltage (e.g. Electro
-
Static Discharge)

Source: Pey&Tung

Source: Pey&Tung

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Cornelius et. al: Shadow Transistors

Motivation

TDDB

Trends

Source: Borkar, Intel

Increasing probability for Gate
-
Oxide
-
Breakdown

Source: Kauerauf, EDL, 2002

high
-
k?

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Cornelius et. al: Shadow Transistors

TDDB between gate and channel

Shadow Transistors

Applied

m
odel

V
out
/V
DD

rel. delay

R
GC

[k
Ω
] →

For an Inverter, 65nm
-
BPTM:

Model:

Based on: Segura et. al., “A Detailed Analysis of GOS Defects
in MOS Transistors: Testing Implications at Circuit Level” 1995.

W= W
1
+W
2

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Cornelius et. al: Shadow Transistors

TDDB between gate and source/drain

Shadow Transistors

Applied

model

For an Inverter, 65nm
-
BPTM:



Model:

V
out
/V
DD

R
GC

[k
Ω
] →

Based on: Segura et. al., “A Detailed Analysis of GOS Defects
in MOS Transistors: Testing Implications at Circuit Level” 1995.

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Cornelius et. al: Shadow Transistors

Shadow Transistors

1.

Insertion of additional transistors in
parallel to vulnerable transistors




Shadow transistors
(ST)

Main idea (1)


Parallel transistors

R
GC

[k
Ω
] →

wo/ ST

w/ ST

R
GC

[k
Ω
] →

w/ ST

wo/ ST

For an Inverter, 65nm
-
BPTM

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Cornelius et. al: Shadow Transistors

Shadow Transistors

Main idea (2)


Thick gate oxides

2.

Application of H
-
Vt/To transistors with:


Higher threshold voltage


Thicker gate oxide




Less vulnerable to TDDB

Source:


Srinivasan
, “RAMP: A Model for Reliability Aware Microprocessor Design”


Stathis
, J., “Reliability Limits for the Gate Insulator in CMOS Technology”

MTTF


Mean Time To Failure

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Cornelius et. al: Shadow Transistors

Shadow Transistors

Main idea (3)


Selective insertion

3.

Selective insertion of shadow transistors in parallel to vulnerable
transistors:


Component reliability depends on



Activity, state, temperature, size, fabrication …




Most vulnerable can be identified

Shadow transistors
only added in parallel
to most vulnerable
devices.

Netlist
modification

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Cornelius et. al: Shadow Transistors

Shadow Transistors

Main idea (3)


Selective insertion

3.

Selective insertion of shadow transistors in parallel to vulnerable
transistors:


Component reliability depends on



Activity, state, temperature, size, fabrication …




Most vulnerable can be identified

Shadow transistors
only added in parallel
to most vulnerable
devices.

Netlist
modification




Estimation of stress factors


Determination of components reliability


Adding redundancy only at most vulnerable components



Advantage:
Lower

area, power and delay

penalty compared to
complete redundancy or random insertion [Sri04]


Our Approach

Source: [Sri04] Sirisantana, D&T, 2004

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Cornelius et. al: Shadow Transistors

Shadow Transistors

Main ideas

Discussion




Increased reliability in respect to TDDB


H
-
Vt/To: Reliability increases by ~5x (for
Δt
ox

= 0.15 nm)


Remarkable increase of system life time

Advantages




Higher input capacity → higher delay and dynamic power dissipation


Area increase

Drawbacks




Only slight improvements for Gate
-
Drain/Source breakdown


H
-
Vt/To has to be supported by technology

Remarks

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Cornelius et. al: Shadow Transistors

Shadow Transistors

Algorithm

Estimation of logical Signal
Probabilities (SP)

Insertion of Shadow transistors
where SP is
lower
(PMOS) than
threshold value
SP
th

or
higher

(NMOS) than
1
-

SP
th

Estimation of delay increase
Δ
t
d

and new
Mean Time To Failure
(MTTF)

Modification of
SP
th

depending on
Δ
t
d

/ MTTF

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Cornelius et. al: Shadow Transistors

Results

Improvement MTTF (L
-
Vt/To)


≈ 23 % additional transistors

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Cornelius et. al: Shadow Transistors

Results

Performance Reduction (L
-
Vt/To)

≈ 23 % additional transistors

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Cornelius et. al: Shadow Transistors

Results

Application of H
-
Vt/To
-
ST

≈ 23 % additional transistors

19

Cornelius et. al: Shadow Transistors

Results

Modification of C
crit

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Cornelius et. al: Shadow Transistors

Conclusion


System reliability decreases with shrinking technologies and rising
transistor count


Increasing probability of Time
-
Dependent Dielectric Breakdown
(TDDB)


Insertion of Shadow Transistors (ST) increases system lifetime


Remarkable improvements by application of transistors with thick
gate
-
oxide


Selective insertion of ST improves trade
-
off between reliability and
performance


Impact and amount of redundant transistors can be adapted by the
threshold value SP
th

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Cornelius et. al: Shadow Transistors

Thank you!

claas.cornelius@uni
-
rostock.de

franksill@ufmg.br