ECE484 VLSI Digital Circuits Fall 2010

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CSE477 L04 CMOS Inverter.
1

Irwin&Vijay, PSU, 2002

ECE484

VLSI Digital Circuits

Fall 2010



Lecture 04: CMOS Inverter (static view)

Mary Jane Irwin (
www.cse.psu.edu/~mji

)
www.cse.psu.edu/~cg477


Modified by Dr. George Engel (SIUE)


[Adapted from Rabaey’s
Digital Integrated Circuits
,
©
2002, J. Rabaey et al.]

CSE477 L04 CMOS Inverter.
2

Irwin&Vijay, PSU, 2002

CMOS Inverter:

A First Look

V
DD

V
out

C
L

V
in

CSE477 L04 CMOS Inverter.
3

Irwin&Vijay, PSU, 2002

CMOS Inverter:

Steady State Response

V
DD

R
n

V
out
= 0

V
in
= V

DD

V
DD

R
p

V
out
= 1

V
in
= 0

V
OL

= 0

V
OH

= V
DD

V
M

= f(R
n
, R
p
)

CSE477 L04 CMOS Inverter.
4

Irwin&Vijay, PSU, 2002

CMOS Properties


Full rail
-
to
-
rail swing


high noise margins


Logic levels not dependent upon the relative device sizes


transistors can be minimum size


ratioless


Always a path to V
dd

or GND in steady state


low
output impedance (output resistance in k


range)


large fan
-
out (albeit with degraded performance)


Extremely high input resistance (gate of MOS transistor
is near perfect insulator)


nearly zero steady
-
state
input current


No direct path steady
-
state between power and ground


no static power dissipation


Propagation delay function of load capacitance and
resistance of transistors

CSE477 L04 CMOS Inverter.
5

Irwin&Vijay, PSU, 2002

Review: Short Channel I
-
V Plot (NMOS)

V
DS

(V)

X 10
-
4

V
GS

= 1.0V

V
GS

= 1.5V

V
GS

= 2.0V

V
GS

= 2.5V

NMOS transistor, 0.25um,
L
d

= 0.25um
, W/L = 1.5, V
DD

= 2.5V, V
T

= 0.4V

CSE477 L04 CMOS Inverter.
6

Irwin&Vijay, PSU, 2002

Review: Short Channel I
-
V Plot (PMOS)

V
DS

(V)

X 10
-
4

V
GS

=
-
1.0V

V
GS

=
-
1.5V

V
GS

=
-
2.0V

V
GS

=
-
2.5V

PMOS transistor, 0.25um,
L
d

= 0.25um
, W/L = 1.5, V
DD

= 2.5V, V
T

=
-
0.4V



All polarities of all voltages and currents are reversed

CSE477 L04 CMOS Inverter.
7

Irwin&Vijay, PSU, 2002

Transforming PMOS I
-
V Lines

I
DSp

=
-
I
DSn

V
GSn
= V
in
; V
GSp

= V
in

-

V
DD

V
DSn
= V
out
; V
DSp

= V
out

-

V
DD

V
out

I
Dn

V
GSp
=
-
2.5

V
GSp
=
-
1

Mirror around x
-
axis

V
in

= V
DD

+ V
GSp

I
Dn
=
-
I
Dp

V
in
= 1.5

V
in
= 0

V
in
= 1.5

V
in
= 0

Horiz. shift over V
DD

V
out

= V
DD

+ V
DSp



Want common coordinate set V
in
, V
out
, and I
Dn

CSE477 L04 CMOS Inverter.
8

Irwin&Vijay, PSU, 2002

CMOS Inverter Load Lines

V
out

(V)

X 10
-
4

V
in

= 1.0V

V
in

= 1.5V

V
in

= 2.0V

V
in

= 2.5V

0.25um, W/L
n

= 1.5,
W/L
p

= 4.5
, V
DD

= 2.5V, V
Tn

= 0.4V, V
Tp

=
-
0.4V

V
in

= 0V

V
in

= 0.5V

V
in

= 1.0V

V
in

= 1.5V

V
in

= 0.5V

V
in

= 2.0V

V
in

= 2.5V

V
in

= 2V

V
in

= 1.5V

V
in

= 1V

V
in

= 0.5V

V
in

= 0V

PMOS

NMOS

CSE477 L04 CMOS Inverter.
10

Irwin&Vijay, PSU, 2002

CMOS Inverter VTC

V
in

(V)

V
out

(V)

NMOS off

PMOS res

NMOS sat

PMOS res

NMOS sat

PMOS sat

NMOS res

PMOS sat

NMOS res

PMOS off

CSE477 L04 CMOS Inverter.
12

Irwin&Vijay, PSU, 2002

CMOS Inverter:

Switch Model of Dynamic Behavior

V
DD

R
n

V
out

C
L

V
in
= V

DD

V
DD

R
p

V
out

C
L

V
in
= 0



Gate response time is determined by the time to charge C
L

through R
p

(discharge C
L

through R
n
)


CSE477 L04 CMOS Inverter.
13

Irwin&Vijay, PSU, 2002

Relative Transistor Sizing


When designing static CMOS circuits,
balance the driving strengths of the
transistors by making the PMOS section
wider than the NMOS section to


maximize the noise margins and


obtain symmetrical characteristics

CSE477 L04 CMOS Inverter.
14

Irwin&Vijay, PSU, 2002

Switching Threshold


V
M

where V
in

= V
out

(both PMOS and NMOS in saturation
since V
DS

= V
GS
)

V
M



rV
DD
/(1 + r) where r = k
p
V
DSATp
/k
n
V
DSATn


Switching threshold set by the ratio r, which compares
the
relative driving strengths

of the PMOS and NMOS
transistors



Want

V
M

= V
DD
/2 (to have comparable high and low
noise margins), so want r


1


(W/L)
p

k
n
’V
DSATn
(V
M
-
V
Tn
-
V
DSATn
/2)


(W/L)
n

k
p
’V
DSATp
(V
DD
-
V
M
+V
Tp
+V
DSATp
/2)

=

CSE477 L04 CMOS Inverter.
16

Irwin&Vijay, PSU, 2002

Switch Threshold Example


In our generic 0.25 micron CMOS process, using the
process parameters from slide L03.25, a V
DD

= 2.5V, and
a minimum size NMOS device ((W/L)
n

of 1.5)

V
T0
(V)


(V
0.5
)

V
DSAT
(V)

k’(A/V
2
)


(V
-
1
)

NMOS

0.43

0.4

0.63

115 x 10
-
6

0.06

PMOS

-
0.4

-
0.4

-
1

-
30 x 10
-
6

-
0.1


(W/L)
p

115 x 10
-
6

0.63 (1.25


0.43


0.63/2)


(W/L)
n
-
30 x 10
-
6
-
1.0 (1.25


0.4


1.0/2)

=

x

x

=
3.5


(W/L)
p
= 3.5 x 1.5 = 5.25 for a V
M

of 1.25V

CSE477 L04 CMOS Inverter.
17

Irwin&Vijay, PSU, 2002

Simulated Inverter V
M

(W/L)
p
/(W/L)
n



V
M

is relatively
insensitive to variations in
device ratio



setting the ratio to 3, 2.5
and 2 gives V
M
’s of 1.22V,
1.18V, and 1.13V




Increasing the width of
the PMOS moves V
M

towards V
DD




Increasing the width of
the NMOS moves V
M

toward GND

.1

Note: x
-
axis is semilog

~3.4

CSE477 L04 CMOS Inverter.
18

Irwin&Vijay, PSU, 2002

Noise Margins Determining V
IH

and V
IL

V
in

V
OH

= V
DD

V
M

By definition, V
IH

and V
IL

are
where dV
out
/dV
in

=
-
1 (= gain)


V
OL

= GND

A piece
-
wise linear
approximation of VTC



NM
H
= V
DD
-

V
IH


NM
L
= V
IL
-

GND


Approximating:


V
IH
= V
M
-

V
M
/g


V
IL
= V
M
+ (V
DD
-

V
M
)/g


So high gain in the transition
region is very desirable

CSE477 L04 CMOS Inverter.
19

Irwin&Vijay, PSU, 2002

CMOS Inverter VTC from Simulation

V
in

(V)

V
out

(V)

0.25um, (W/L)
p
/(W/L)
n

= 3.4

(W/L)
n

= 1.5 (min size)

V
DD

= 2.5V


V
M



1.25V, g =
-
27.5


V
IL

= 1.2V, V
IH

= 1.3V

NM
L

= NM
H

= 1.2

(actual values are
V
IL

= 1.03V, V
IH

= 1.45V

NM
L

= 1.03V & NM
H

= 1.05V)


Output resistance
low
-
output = 2.4k


high
-
output = 3.3k


CSE477 L04 CMOS Inverter.
20

Irwin&Vijay, PSU, 2002

Gain Determinates

V
in

Gain is a strong function of the
slopes of the currents in the
saturation region, for V
in

= V
M



(1+r)

g


----------------------------------


(V
M
-
V
Tn
-
V
DSATn
/2)(

n
-


p
)



Determined by technology
parameters, especially channel
length modulation (

). Only
designer influence through
supply voltage

and V
M

(
transistor
sizing
).


CSE477 L04 CMOS Inverter.
21

Irwin&Vijay, PSU, 2002

Impact of Process Variation on VTC Curve

V
in

(V)

V
out

(V)

Nominal

Good PMOS

Bad NMOS

Bad PMOS

Good NMOS


Process variations (mostly) cause a shift in the switching threshold

CSE477 L04 CMOS Inverter.
22

Irwin&Vijay, PSU, 2002

Scaling the Supply Voltage

V
in

(V)

V
out

(V)

Device threshold voltages are
kept (virtually) constant

V
in

(V)

V
out

(V)

Gain=
-
1

Device threshold voltages are
kept (virtually) constant