Lecture # 07

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Nov 1, 2013 (3 years and 9 months ago)

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SEMICONDUCTOR MATERIALS &
TECHNOLOGY



BY

FARIDA MEMON





Text Book : Semiconductor Physics
and Devices ,
Basic Principles,

Donald A. Neamen.

Solid State Electronic Devices,

Ben G. Streetman.


Spring 2007



IC Technology Advancement


Spring 2007

Early History of IC Devices and Technology

Spring 2007

Discrete Electronic Circuits

Spring 2007

The Integrated Circuit (IC)


Spring 2007

The Birth of the Integrated Circuit



Jack Kilby (1923
-
2005), who retired from Texas
Instruments in 1983, is credited with being the
original inventor of the integrated circuit.


In 1958
-
1959, Jean Hoerni developed the planar
process, using diffusion of impurities to create
semiconductor layers, and oxidation to make silicon
dioxide insulation layers, to embed insulated layers of
transistors and other circuit elements in a silicon chip.


In 1959, Noyce developed his first IC using planar
transistors, incorporating an isolation technique using
back
-
to
-
back pn junctions.

Spring 2007

The First Planar IC

Spring 2007

Field
-
Effect Transistors

Spring 2007

The IC Market


The semiconductor industry is
approaching $300B/yr in sales

Transportation

8%

Consumer Electronics

16%

Communications

24%

Computers

42%

Industrial

8%

Military

2%

Spring 2007

IC Technology Advancement

Improvements in IC performance and cost have been
enabled by the steady miniaturization of the transistor

Better Performance/Cost

Market Growth

International Technology

Roadmap for Semiconductors

Transistor Scaling

Investment


SMIC’s Fab 4 (Beijing, China)

Photo by L.R. Huang, DigiTimes

PITCH

YEAR:

2004

2007

2010

2013

2016

HALF
-
PITCH:

90nm

65nm

45nm

32nm

22nm

Spring 2007

The Nanometer Size Scale

Carbon nanotube

MOSFET

Spring 2007

IC Fabrication

Spring 2007


Physical
Fabrication of Transistors,
from Point Contact to Planar
structure


Spring 2007

Transistors


Two main categories of transistors:


bipolar junction transistors

(BJTs)

and


field effect transistors (FETs).



Transistors have 3 terminals where the application of
current (BJT)

or
voltage (FET)

to the input terminal
increases the amount of charge in the active region.


The physics of "
transistor action
" is quite different for
the BJT and FET.


In analog circuits, transistors are used in
amplifiers
and linear regulated power supplies
.


In digital circuits they function as electrical
switches
,
including
logic gates, random access memory (RAM),
and microprocessors
.

Spring 2007

The First Transistor:
Point
-
contact transistor

A point
-
contact transistor was
the first type of
solid state
electronic transistor

ever
constructed.

It was made by researchers
John Bardeen & Walter Houser
Brattain at Bell Laboratories in
December 1947.

The point
-
contact transistor was
commercialized and sold by Western
Electric and others but was rather quickly
superseded by the junction transistor.

Spring 2007

The Junction Transistor


First
BJT

was invented early in 1948, only
weeks after the point contact transistor.


Initially known simply as the
junction
transistor
.


It did not become practical until the early 1950s.


The term “
bipolar
” was tagged onto the name to
distinguish the fact that
both carrier types play
important roles in the operation
.


Field Effect Transistors
(
FET
s) are “
unipolar

transistors since their operation depends
primarily on a single carrier type.

Spring 2007

Bipolar Junction Transistors (BJT)


A bipolar transistor
essentially consists of a pair of
PN Junction diodes

that are
joined back
-
to
-
back.


There are therefore two kinds
of BJT, the
NPN

and
PNP

varieties.


The three layers of the
sandwich are conventionally
called the
Collector
,
Base
, and
Emitter
.

Spring 2007

The First BJT

Transistor Size (3/8”L X 5/32”W X 7/32”H)

No Date Codes. No Packaging.

Spring 2007

Modern Transistors

Spring 2007

BJT Fabrication


BJT can be made either as
discrete
devices

or in
planar integrated

form.


In discrete, the
substrate can be used for
one connection
, typically the collector.


In integrated version, all
3 contacts
appear on the top surface
.


The E
-
B diode is closer to the surface than the
B
-
C junction because it is easier make the
haviear

doping at the top.

Spring 2007

The point contact transistor



William Shockley's original transistor was fabricated
by creating two gold contact points, very close
together (about .002 inches).


From gold foil on a plastic wedge (the closely
-
separated contacts being made by cutting the foil
with a razor blade).


These contacts were made to a slab of germanium,
which rested on a metal base
-

hence the name
"base" for the control electrode of the transistor.


It doesn't really have the three layers of the
conventional junction transistor
-

it was a pioneering
stage in transistor development, leading to the
junction transistor.


Spring 2007

The point contact transistor


The gold contacts were in the form of parallel lines.


Later commercially manufactured point
-
contact
transistors were based on similar principles, but the
contacts were made using pointed wires fused close
together on a semiconductor wafer.


Shockley, Brattain and Bardeen received the Nobel
Prize for their work in 1956.


Spring 2007

The Grown Junction Transistor



The first junction transistors were grown
-
junction types, made by growing a crystal
pulled slowly from molten semiconductor,
which starts out containing impurities for the
P
-
type, then changed to N
-
type, then back to
P
-
type.


This created a PNP sandwich which could be
cut into individual transistors.



However, it was difficult to make contact with
the base layer.

Spring 2007

BJT Structure
-

Discrete


Early BJTs were fabricated using
alloying

-

an complicated
and unreliable process.


The structure contains
two p
-
n diodes
, one between the
base and the emitter, and one between the base and the
collector.

Spring 2007

The Alloy Junction Transistor



The first alloy junction transistors were made at General Electric
under R. N. Hall.


These created a PNP (or NPN) junction in a single wafer of one
type of doped semiconductor by allowing a small pellet of
doping material, such as Indium which dopes to P
-
type, to alloy
with the semiconductor wafer on each side of it.


As the Indium atoms diffused in to the semiconductor, they
created a region of P
-
type semiconductor on either side of the
wafer, and between them, the remaining N
-
type material formed
the base of a PNP transistor.


The base layer could be made thinner than for the grown
-
junction transistor and this improved the high
-
frequency
performance available from the transistors.

Spring 2007

The Alloy Junction Transistor

Spring 2007

The Alloy Junction Transistor


These were manufactured by slicing up zone
-
refined and
antimony
-
doped monocrystalline germanium ingots (N
-
type) into
wafers of about 0.5 mm thickness, which were then further
polished and diced into chips of about 2.4 mm square.


After dicing, the pieces were further thinned by chemical etching
down to 0.1 mm.


Small indium pellets were fused to the germanium chips in a
furnace, with temperature and exposure time closely controlled
to determine the depth to which the indium alloys with the
germanium chip.


Each transistor chip was mounted to its lead wires by a person
working with a microscope to bond the lead wires to the
collector, base and emitter, and the transistors were sealed in a
glass capsule about 15mm long and 6mm in diameter, which
had to be filled with a silicone compound to conduct heat from
the chip to the case, and painted to prevent light exposure, as
the devices were quite photosensitive
.

Spring 2007

BJT Structure
-

Planar


In the planar process, all steps are performed
from the surface of the wafer

The “
Planar Structure
” developed by Fairchild in
the late 50s shaped the basic structure of the BJT,
even up to the present day.

Spring 2007

BJT Structure
-

Planar



BJTs are usually constructed vertically


Controlling
depth of the emitter’s n doping sets
the base width

Spring 2007

Advanced BJT Structures



The original BJT structure survived, practically
unchanged, since the mid 60’s.


As the advances in MOS development appears, some
of the fabrication technology are also applied to the
BJT.


Low defect epitaxy


Ion implant


Plasma etching (dry etch)


LOCOS (local oxidation of Si)


Polysilicon layers


Improved lithography


Spring 2007

Isolation Methods


The most significant advances in reducing overall device
size and packing density have come from improved
isolation methods.


The traditional
junction isolation
technique requires the
p+ deep diffusion to be aligned to the n+ buried layer that
is covered by a thick epitaxial layer.


Epitaxy is growing a crystal layer of one mineral on the
crystal base of another mineral in such a manner that its
crystalline orientation is the same as that of the substrate.


The area (and hence junction capacitance) is determined
by alignment tolerance, area for side diffusion, and
allowance for the spread of the depletion region.


Modern isolation techniques:
oxide isolation
, and
trench
isolation
.

Spring 2007

Oxide & Trench Isolation


Oxide isolation processes were introduced in the late 70’s. They
utilize wet anisotropic etch (KOH) of the <100> Si wafer with Si
3
N
4

as mask.


The KOH etch will erode the <111> plane. Oxide is either deposited
or grown to fill the V
-
grooves.


To further reduce the area between adjacent mesa, trench isolation
can be used, making use of trench etching.


The trench is typically 2µm wide and 5µm deep. The trench walls
are oxidized and the remaining volume is filled with
polysilicon
.

Spring 2007

The Planar Fabrication Process



The planar fabrication process by using
photographic masking and surface
oxidation in a series of stages, could
make discrete transistors in planar (flat)
form without having to etch a mesa, as
well as making integrated circuits.


The basic process for planar fabrication
of a bipolar junction transistor is
illustrated below:


Spring 2007

The Planar Fabrication Process


Spring 2007

The Planar Fabrication Process



Stage 1: A chip of N
-
type semiconductor with a surface
layer of silicon oxide (grown by heating the silicon in pure
oxygen) has a window of oxide etched out
photolithographically
.


This
requires a layer of light
-
sensitive material to be
coated on the silicon, then exposed by projecting an
image of a mask on to it, such that the material can be
selectively washed away depending on whether the
material was exposed to light or not.


This
creates a photo
-
resist mask, which allows an etchant
solution to be used to etch out the areas that are
unmasked.


The
N
-
type semiconductor can be a layer diffused into an
intrinsic semiconductor chip, which is known as an
epitaxial layer.


Spring 2007

The Planar Fabrication Process


Spring 2007

The Planar Fabrication Process



Stage 2: A diffusion process is used to create a region under the window that is
P
-
type, where the impurity atoms have diffused into the silicon. The window is
then covered with a new layer of oxide.


Spring 2007

The Planar Fabrication Process



Stage 3: Another photolithographic window is etched within the
area of the previous one.



Spring 2007

The Planar Fabrication Process



Stage 4: Then another diffusion process is used, this time creating a
layer of N
-
type semiconductor entirely within the previously created P
-
type layer. This new layer will be the emitter, and what remains of the
P
-
type layer forms the base. The emitter
-
forming window is then
covered with a new layer of oxide.


Spring 2007

The Planar Fabrication Process



Stage 5: Photolithographic windows are etched over the base P
-
type and emitter N
-
type regions.



Spring 2007

The Planar Fabrication Process



Stage 6: A layer of
aluminium

is diffused on to the windowed base P
-
type and
emitter N
-
type regions. A similar method is used to make contact with the
epitaxial collector layer (not shown), and then very fine wires may be bonded by
various techniques to provide connections between the chip and the wires or
pins of the package that contains and protects it.


A silicon wafer is shown below, containing a number of repeated
aluminium

metallisation

test patterns, which were used to develop a manufacturing
process.