Special applications of VLSI design

stingymilitaryElectronics - Devices

Nov 27, 2013 (3 years and 7 months ago)

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Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Slide
1

Spezielle Anwendungen des VLSI


Entwurfs

Applied VLSI design

Course

and

contest


Results

of

Phase 4


Andy
Schellin

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Slide
2

Tasks/Workflow

-
Optimization of Synopsys results


-
Layout


-
Floorplanning
, Placement, Routing


-
Improvements

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Slide
3

Floorplanning

0.00E+00
2.00E+27
4.00E+27
6.00E+27
8.00E+27
1.00E+28
1.20E+28
0
0.5
1
1.5
2
2.5
3
3.5
4
Metrik [1/J²]

Aspect Ratio

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Slide
4

Best Metric

0.00E+00
2.00E+27
4.00E+27
6.00E+27
8.00E+27
1.00E+28
1.20E+28
1.40E+28
0
100
200
300
400
500
600
700
800
Metrik [1/J²]

Frequenz [MHz]

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Slide
5

Cadence Layout

-
Aspect
-
Ratio: 3


-
Timing Driven: high effort


-
Optimize Design:

-
Leakage Power Effort: high

-
Dynamic

Power Effort
: high


-
Possible improvements

-
New order of output pins

-
Placement by hand in critical areas


Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Results

Mandatory

infos

for

layout

Timing (
f
max

/
T
min
)

409MHz / 2,44ns

Power (
P
dyn

/
P
leak
)

952µW/13,4nW

Core
size

[µm²]

2720

Core
utilization

73,7%

# Pipeline
stages

2

Metric

[1/J²]

1,31*10
28

Slide
6

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Slide
7

Layout with pads

-
Total Dynamic Power:

44,46mW


-
Cell Leakage Power:

6,27mW


-
99,73% power loss

through pads

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering
, University of Rostock

Thank you for your attention

Slide
8