Literary Survey
CprE583
Adam
Pfab
25Sept2011
Literary Survey Subject
•
The topic selected was “True Random Number
Generation in FPGAs”
•
Used IEEE website:
http://ieeexplore.ieee.org/Xplore/dynhome.jsp
•
Modified search criteria:
–
“FPGA” and “Random”, 2007

2010, Journals
–
“FPGA” and “Random”
–
The second search was required to find additional
applicable research papers
True Random Number Generation in FPGAs
P
1
:
Source of
Randomness
P
2
:
Entropy
Creation
P
3
:
Resource Utilization and
Speed
/
Throughput
(
BPS
)
P
1
.
A
1
:
DCM
/
DLL
/
PLL
P
1
.
A
2
:
Inversion
Method
P
1
.
A
3
:
Gaussian Variate
Generator
P
1
.
A
1
.
I
1
:
“
FPGA

based High

speed True Random
Number Generator for
Cryptographic
Applications”
P
1
.
A
1
.
I
2
:
“High performance
physical random
number
generator”
P
1
.
A
1
.
I
3
:
“Software PLL Based
on Random Sampling
”
P
1
.
A
2
.
I
1
:
“
Hardware Generation
of Arbitrary Random
Number Distributions
From Uniform
Distributions Via the
Inversion Method”
P
1
.
A
3
.
I
1
:
“A Compact and
Accurate Gaussian
Variate Generator
”
P
2
.
A
1
:
Applying
Probability
P
2
.
A
2
:
Data
Manipulation
P
2
.
A
1
.
I
1
:
“
FPGA

based High

speed True Random
Number Generator for
Cryptographic
Applications”
P
2
.
A
1
.
I
2
:
“High performance
physical random
number
generator”
P
2
.
A
2
.
I
1
:
“A Compact and
Accurate Gaussian
Variate Generator
”
P
2
.
A
2
.
I
2
:
“Mersenne Twister
Random Number
Generation on FPGA
,
CPU and GPU
”
P
3
.
A
1
:
Note
1
Summary
•
The subject matter was somewhat difficult to distill
–
In hindsight, it would have been quite reasonable to break the subject in half: “Sources of
Randomness” and “Entropy Creation”
–
The difficulty in breaking the subject in half is that there was substantial coupling between the
source of randomness and the post

processing of that information
–
Also, I was surprised to find a lack of public research in the area in the last 5 years and had to
extend my sources of information out beyond the timeframe identified in the assignment
•
The third problem area, Resource Utilization and Speed/Throughput (BPS) was
identified, but not specified in the research papers (thus the “*Note 1” depiction)
–
Many papers touched on how their implementation resulted in better/faster than previous
work
–
But, the papers themselves did not ascertain this cause

effect relationship
•
W
as the implementation needed to reduce resources or increase throughput [cause]?
•
O
r was it an unintended benefit [effect]?
•
I was surprised that I did not uncover one area of great importance with true
random number generation: repeatability
–
In some situations, it would be greatly desired to have repeatability (test vectors for instance)
–
In some situations, it would be greatly desired to have non

repeatability (cryptographic
applications for instance)
Background Information
•
Tsoi
, K.H.; Leung, K.H.; Leong, P.H.W.; , "High performance physical random number generator," Computers & Digital Techniques, IE
T ,
vol.1, no.4, pp.349

352, July 2007doi: 10.1049/iet

cdt:20050173
–
Abstract: A field programmable gate array (FPGA)

based implementation of a physical random number generator (PRNG) is presented.
The PRNG uses an alternating step generator construction to
decorrelate
an oscillator

phase

noise

based physical random source. The resulting design can be implemented completely in digital technolog
y, requires no external components, is very small in area,
achieves very high throughput and has good statistical properties. The PRNG was implemented on an FPGA device and tested usin
g t
he NIST, Diehard and TestU01 random number test suites.URL:
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4271377&isnumber=4271368
•
Sonnaillon
, M.O.;
Urteaga
, R.;
Bonetto
, F.J.; , "Software PLL Based on Random Sampling," Instrumentation and Measurement, IEEE Transactions on , vol.59, no.10, pp.
262
1

2629, Oct.
2010doi: 10.1109/TIM.2009.2036459
–
Abstract: This paper presents and analyzes a phase

locked loop (PLL) based on digital signal processing (DSP) and random samplin
g (RS). Traditional DSP techniques based on uniform sampling require
sampling at more than twice the PLL frequency to avoid spectrum aliasing. This requirement makes difficult the implementation
of
high

frequency software

based PLLs. RS techniques allow significantly
reducing the sampling speed requirements without aliasing effects. Lower speed requirements in the analog

to

digital converter (
ADC) and the processing device enable the implementation of software
PLLs for much higher frequencies than traditional techniques. The proposed PLL is mathematically analyzed to describe its ope
rat
ion and characterize its performance. A field

programmable gate array
(FPGA)

based PLL prototype is presented to validate the theoretical analysis.URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=
&arnumber=5546971&isnumber=5571852
•
Cheung, R.C.C.; Dong

U Lee;
Luk
, W.;
Villasenor
, J.D.; , "Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method,"
Ve
ry
Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.15, no.8, pp.952

962, Aug. 2007doi: 10.1109/TVLSI.2007.900748
–
Abstract: We present an automated methodology for producing hardware

based random number generator (RNG) designs for arbitrary d
istributions using the inverse cumulative distribution function
(ICDF). The ICDF is evaluated via piecewise polynomial approximation with a hierarchical segmentation scheme that involves un
ifo
rm segments and segments with size varying by powers of two which
can adapt to local function nonlinearities. Analytical error analysis is used to guarantee accuracy to one unit in the last p
lac
e (
ulp
). Compact and efficient RNGs that can reach arbitrary multiples of the
standard deviation sigma can be generated. For instance, a Gaussian RNG based on our approach for a Xilinx Virtex

4 XC4VLX100

12
field

programmable gate array produces 16

bit random samples up
to 8.2 sigma. It occupies 487 slices, 2 block

RAMs, and 2 DSP

blocks. The design is capable of running at 371 MHz and generates
one sample every clock cycle.URL:
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4276772&isnumber=4276770
•
Alimohammad
, A.;
Fard
, S.F.; Cockburn, B.F.; Schlegel, C.; , "A Compact and Accurate Gaussian
Variate
Generator,“ Very Large Scale Integration (VLSI) Systems, IEEE Transactions on ,
vol.16, no.5, pp.517

527, May 2008doi: 10.1109/TVLSI.2008.917552
–
Abstract: A compact, fast, and accurate realization of a digital Gaussian
variate
generator (GVG) based on the Box

Muller algorithm is presented. The proposed GVG has a faster Gaussian sample
generation rate and higher tail accuracy with a lower hardware cost than published designs. The GVG design can be readily con
fig
ured to achieve arbitrary tail accuracy (i.e., with a proposed 16

bit
datapath
up to plusmn15 times the standard deviation sigma) with only small variations in hardware utilization, and without degrading
th
e output sample rate. Polynomial curve fitting is utilized along
with a hybrid (i.e., combination of logarithmic and uniform) segmentation and a scaling scheme to maintain accuracy. A typica
l i
nstantiation of the proposed GVG occupies only 534 configurable slices,
two on

chip block memories, and three dedicated multipliers of the Xilinx
Virtex

II XC2V4000

6 field

programmable gate array (FPGA) and operates at 248 MHz, generating 496 million Gaussian
variates
(GVs) per second within a range of plusmn6.66sigma. To accurately achieve a range of plusmn9.4sigma, the GVG uses 852 configu
rab
le slices, three block memories, and three on

chip dedicated
multipliers of the same FPGA while still operating at 248 MHz, generating 496 million GVs per second. The core area and perfo
rma
nce of a GVG implemented in a 90

nm CMOS technology are also
given. The statistical characteristics of the GVG are evaluated and confirmed using multiple standard statistical goodness

of

fi
t tests.URL:
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4476028&isnumber=4490005
•
Kwok, S.H.M.; Lam, E.Y.; , "FPGA

based High

speed True Random Number Generator for Cryptographic Applications,“ TENCON 2006. 200
6 IEEE Region 10 Conference , vol., no., pp.1

4,
14

17 Nov. 2006doi: 10.1109/TENCON.2006.344013
–
Abstract: Random number generator is a key primitive in cryptographic algorithms and applications. In this paper, we propose
an
architecture to implement a high

speed and high

quality true random
number generator, which can be used as FPGA

based cryptographic hardware cores. By implementing the proposed generator in Xilinx
Vertex II Pro FPGA and testing the output random bit stream
using NIST and Diehard random number test suites, we prove that the proposed generator can be implemented effectively in FPGA
wi
th very high output rate and strong randomness URL:
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4142319&isnumber=4142121
•
Xiang
Tian
;
Benkrid
, K.; , "
Mersenne
Twister Random Number Generation on FPGA, CPU and GPU," Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on
,
vol., no.,
pp.460

464, July 29 2009

Aug. 1 2009doi: 10.1109/AHS.2009.11
–
Abstract: Random number generation is a very important operation in computational science e.g. in Monte Carlo simulations met
hod
s. It is also a computationally intensive operation especially for high
quality random number generation. In this paper, we present the design and implementation of a parallel implementation of one
of
the most widely used random number generators, namely the
Mersenne
Twister. The latter is very widely used in high performance computing applications such as financial computing. Implementatio
ns
of our parallel
Mersenne
Twister number generator core on
Xilinx Virtex4 FPGAs achieve a throughput of 26.13 billion random samples per second. The paper also reports equivalent paral
lel
software implementations running on an Intel Core 2 Quad Q9300 CPU
with 8 GB RAM, using multi

threading technology and the
Intelreg
Math Kernel Library (MKL), as well as on an NVIDIA 8800 GTX GPU. Comparative results show that our FPGA

based implementation
outperforms equivalent CPU and GPU implementations by ~25times and ~9times respectively. Moreover, when using the same amount
of
energy, the FPGA can generate 37times and 35times more
Mersenne
Twister random samples than the CPU and the GPU, respectively. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=
53
25420&isnumber=5325404
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