Power Aware BDD-based Logic Synthesis Using Adiabatic Multiplexers

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Nov 27, 2013 (3 years and 4 months ago)

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1

Power Aware BDD
-
based Logic Synthesis Using Adiabatic Multiplexers



Sambhu N. Pradhan


Gopal Paul


Ajit Pal



Bhargab B. Bhattacharya



Dept. of Computer Sc. & Engg., IIT
-
K
haragpur
ACMU,
Indian Statistical Institute


WB
-

721302, India


Kolkata
-

700108, India

sambhu.pradhan@gmail.com

gpaulcal@yahoo.com

apal@cse.iitkgp.ernet.in

bhargab@isical.ac.in





ABSTRACT
Binary Decision Diagrams (BDDs) play an important
role in the synthesis, verification, and testing of VLSI
circuits. In this paper, we have proposed a new BDD
-
based approach for the synthesis of dual
-
rail adiabatic
MUX circuits. The method yields around 22%
reduction in the number of MUX blocks for severa
l
benchmark circuits compared to the conventional
approach. Simulation result using SPICE on 180 nm
technology shows, on an average, 50% reduction in
power consumption for frequency ranging up to 300
MHz compared to implementation with static CMOS
MUX circ
uits. At 600 MHz, power saving is observed
to be nearly 35%. It is envisaged that the proposed
approach will be useful in realizing low
-
power circuits.


1 INTRODUCTION

A Binary Decision Diagram (BDD) [1] is a directed
acyclic graph (DAG) that represents
a Boolean
function (or multiple functions) as a sum
-
of
-
disjoint
-
products (sodp) form. Not only BDDs provide an
efficient data structure to represent Boolean functions,
there is one
-
to
-
one correspondence between a BDD
and a MUX
-
based realization of the func
tion. So, the
number of MUXs required to realize a function
depends of the number of nodes in the BDD, which in
turn depends on the ordering of variables. One popular
package, known as CUDD [3], can be used to obtain
an optimal
-
size BDD for a given functio
n. However, in
recent times, power consumption has been recognized
as an important issue in implementing battery
-
operated
portable devices. One of the techniques for designing
low
-
power circuits and memory is to employ adiabatic
logic that has received lot

of attention recently [7,11,
13]. Design of an adiabatic ripple carry adder has been
reported recently [10]. In this paper, we have presented
a synthesis procedure for multi
-
output logic functions
where, given its ROBDD, a pair of nodes with a
certain pro
perty (called
complementary pair
) can be
replaced by a single adiabatic MUX block. Hence, it
not only helps in reducing the number of MUX blocks
(by utilizing the dual
-
rail output of the adiabatic
MUX), but also reduces power dissipation significantly
by a
llowing recycling of energy to the power supply, a
property intrinsic to adiabatic operations. The proposed
technique will be useful in designing low
-
power
portable devices [14] or biomedical implants that
operate under a frequency of 600 MHz.



2 PRELI
MINERIES

The BDD corresponding to the full
-
adder function is
shown in Fig. 1. The nodes of a BDD denote the
variables of the function(s). Except for the two
terminal nodes (labeled as 0 and 1), every node has
exactly two outgoing edges drawn as solid and d
ashed
lines corresponding to the decision value true or false
of the node variable, respectively. The number of
incoming edges on each node may be one or more. A
BDD is called
ordered

(OBDD) if each variable
appears at most once on each path from the root
node
to a terminal node, and if the variables appear in the
same order in all other paths [2]. CUDD package [3]
can be used to obtain an optimized ROBDD that can
be directly mapped to adiabatic MUX
-
based logic
circuits. Reduction of power dissipation in a
system
has become a very important issue with the
proliferation of battery operated portable devices.
Parameters like battery life, weight and size are used in
an embedded/portable system are directly affected by
power dissipation. The energy advantage can

be
readily understood by assuming a constant current
source that delivers the charge CV over a time period
T. The dissipation through the channel resistance R
[12] is given by:

E
diss
=PT = I
2
R T =

2






T
CV
R.T

=
2
.
.
V
C
T
RC








(1)

Equation (1) shows that it is possible to charge and
oppositely labeled incoming edges and 1(0)
-
successor
discharge a capacitance through a resistance while
dissipating less than
CV
2

of energy. It also suggests
that it is possible to reduce the diss
ipation to an


2



















arbitrary degree by increasing the switching time to
ever
-
larger values. This principle is referred as the
adiabatic charging. Several adiabatic logic families
have been proposed so far. For better power
management, logic f
amilies employing MOSFETs are
preferred over diodes. The following three families are
generally used: the Efficient Charge Recovery Logic
(ECRL) [7], the 2N
-
2N2P [8], and the Positive
Feedback Adiabatic Logic (PFAL) [9, 10]. It has been
observed that the P
FAL shows satisfactory
performance in terms of energy consumption, useful
frequency range, and robustness against technology
parameter variations [11]. The energy dissipation of
the adiabatic circuits is proportional to the square of
the threshold voltage
[12], given by:

|Vtp|
:
E
diss
= ½ C |Vtp|
2

(2)

Where Vtp is the threshold voltage of the transistor.
Figure 2 shows the MUX circuit implemented with
CMOS PFAL adiabatic logic. The logic output of both
conventional and adiabat
ic MUX circuits is
Vout
,
whereas in the adiabatic circuit an extra
complementary output

Vout

is also present. In the
case of conventional BDD, a complementary pair of
nodes is synthesized by two MUX blocks as shown in
Fig. 3. But the same can be implement
ed with single
adiabatic MUX. Figure 4a shows a schematic dual
-
rail
adiabatic MUX in contrast to a conventional MUX
shown is Fig. 4b.


3

BDD
-
BASED SYNTHESIS USING
ADIABATIC MUX

We will illustrate the procedure with a simple example.
Consider the sum and carr
y functions of a 1
-
bit full
adder, which are given by:

SUM =

X

Y

Z +

X

Y Z +

XY

Z +

XYZ +


X

Y

Z + X

YZ + XY

Z + XYZ;

CARRY = XY + YZ + ZX.

The two
-
output ROBDD graph for the variable
ordering {X, Y, Z} is shown in Fig. 1.
The solid edge
(denoting label ‘1’) represents the true value of the
corresponding variable, whereas, the dashed edge
(denoting label ‘0’) represents the false value of the
same. The leaf nodes denote the output value of the
function. A
complementary

pair
of nodes must
correspond to the same variable; they should also have
of a node should be 0(1) successor of the other. For
example, {Y
1
, Y
2
} is a complementary pair and so is
{Z
1
, Z
2
}. It is easy to map a BDD to a circuit using
MUX [4]. MUX
-
based synthesis
also offers many
advantages from testability perspective. Figure 3



















Fig. 3
: Full adder synthesis by single
-
rail MUX blocks






Fig. 4
: a) Adiabatic MUX, b) Conventional MUX




F




F




F


1 0


1 0 0 1


b

a

a

b




b a

s


s

s


F = a

s + bs

F
=

a

s +

bs

F = a

s + bs

b a

SUM

CARRY


1


0

X
2

X
1

Y
4

Y
3

Y
1

Y
2

Z
1

Z
2



Fig. 1
: BDD representation of a full adder



a


s

b

s


b

s

V
PWR

F


F


a


s


Fig. 2
: S
chematic of an adiabatic MUX
-
block


3

shows how the BDD

of the full adder of Fig. 1 can be
mapped to a conventional MUX
-
based circuit.
Dreschsler et al. [5, 6] observed that a slight
modification of a BDD
-
based MUX circuit could be
made fully testable for all single stuck
-
at and path
-
delay faults. The testabil
ity properties of a
conventional MUX
-
based circuit will be preserved for
an adiabatic MUX
-
based circuit too.

Fig. 5 illustrates how the original BDD can be
redrawn by collapsing complementary pairs. Each of
these pairs can be replaced by a single adiabatic

MUX
block for technology mapping. Each of the remaining
nodes will also need an adiabatic MUX, though not
fully utilized. The final full adder circuit can be
synthesized using adiabatic MUX blocks as shown in
Fig. 6. This can be directly obtained from the

BDD of
Fig. 5. The dotted edges of Fig. 5 correspond to the
complementary edges. Comparing Fig. 3 with Fig. 6, it
may be observed that that number of MUX blocks is
reduced from 8 to 6 in the case of adiabatic MUX
-
based realization. For large and complex c
ircuits, this
reduction can be significant.


4 RESULTS

We have run the proposed algorithm on MCNC
benchmark circuits [15] and observed considerable
reduction in the number of BDD nodes after collapsing
the complementary pairs. The reduced BDD is then
ma
pped to PFAL
-
based adiabatic MUX blocks. Each
adiabatic MUX is simulated using CADENCE
SPECTRE SPICE on 180 nm technologies. With
supply voltage of 1.8V and 500 random input patterns,
the dissipated energy per cycle (in fJ) is calculated for
both a convent
ional MUX and adiabatic MUX
-
based
realizations. Figure 7 indicates a sample of input
patterns applied to adiabatic MUX. The variation of

































energy dissipated with operating frequency is shown in
Fig.

8. For an adiabatic MUX, energy dissipation
remains smaller compared to a conventional CMOS
MUX until the crossover frequency is reached, which
is observed to occur around 650 MHz. Next, for each
benchmark circuit listed in Table 1, we compute the
number

of nodes in the modified BDD, and average
power savings up to 300 MHz. Result shows, on an
average, 22%

reduction in number of MUX blocks and
over 50% power consumption in the reduced BDD
-
based adiabatic circuit. Power consumption

on
interconnects is not
considered here. Table
-
1
summarizes the results. For frequency up to 600 MHz,
then power saving will reduce to nearly 35%.


5 CONCLUSION

A novel approach for the synthesis of MUX
-
based
adiabatic circuits has been presented in this paper. In
contrast to t
he existing approach of mapping each node
of a (RO)BDD to one 2
-
to
-
1 MUX block, the inherent
dual
-
rail feature of the adiabatic MUX circuits has
been exploited to reduce the number of MUX blocks
required in the implementation and increasingly larger
reduct
ion for lower frequency of operation.


REFERENCES

[1]

S. B. Akers, Binary decision diagrams,
IEEE Trans.
Computers,
Vol. C
-
27(6) 1978, pp. 509

516.

[2]

R. E. Bryant, Graph
-
based algorithms for Boolean
function manipulation,
IEEE Trans. On Computers,
Vol. C
-
35(8)
1986, pp. 677
-
691.

[3]

F. Somenzi,
CUDD: CU Decision Diagram Package
;
http://bessie.colorado.edu/~fabio/CUDD.

[4]

W. Gunther and R. Drechsler, ACTion: Combining
logic synthesis and technology mapping for MUX
-
based FPGAs,
J. Systems Architecture,
Vol. 46(14)
2000,

pp. 1321
-
1334.

[5]

R. Drechsler, J. Shi, and G. Fey,
Synthesis of fully
testable circuits from BDDs,
IEEE Transaction on


1 0 0 1 1 0


F


F


F’




F


F

F’







F

F



F


F



1 0

0 1


1 0 0 1


1 0 0 1

X

Z

Y

Y

X


SUM


CARRY


F

F

F’


1 0 0 1



1 0 0 1


1 0 0 1


F

F

F’

Y


Fig. 6
: Full adder synthesis using adiabatic MUX

1

0

X
1

Y
4

Y
3

Y
1

Z
1


Fig. 5
: BDD representation of a full adder


X
2

CARRY

SUM


4

Computer
-
Aided Design
, Vol. 23, No. 3, pp. 440
-
443,
March 2004.

[6]

R. Drechsler, “BiTeS: A BDD
-
based test pattern
generator for strong rob
ust path delay faults,” in
Proc.
Eur. Design Automation Conf.
, 1994, pp. 322

327.

[7]

Y. Moon and D.K. Jeong
,
An efficient charge recovery
logic circuit,

IEEE Journal of Solid
-
State Circuits,

Vol.
31, 1996, pp. 514
-
522.

[8]

A. Kramer, J.S. Denker et al.,
2
nd

order

adiabatic
computing with 2N
-
2N and 2N
-
2N2P logic circuits,

Proc. Intern. Symp. Low Power Design,

1995, pp. 191
-
196.

[9]


A. Vetuli, S. Di Pascoli and L. M. Reyneri,
Positive
feedback in adiabatic logic
,
Electronics Letters,

Vol. 32,
No. 20, Sep. 1996, pp. 186
7.

[10]


A. Blotti, S. Di Pascoli and R. Saletti,
Simple model
for positive feedback adiabatic logic power
consumption estimation,
Electronics Letters
, Vol. 36,
No. 2, Jan. 2000, pp. 116
-
118.

[11]


A. Amirante., A. Bargagli
-
Stoffi, J. Fischer, G.
Iannaccone and D. S
chmitt
-
Landsiedel,
Adiabtic 4
-
bit
adders: Comparisons of performance and robustness
against technology parameter variations
,
Proc. 45
th

IEEE Intern. Midwest Symposium on Circuits and
Systems,

MWSCAS’02, Tulsa, OK,USA, Vol. III, Aug.
2002, pp. 644
-
647.

[12]


J.

Fisher, P. Teichmann, and D.S
-
Landsiedel, Scaling
Trends in Adiabatic


Logic,
Proc. of 2nd Conference on
Computing Frontiers
, pp. 427
-
434, 2005.

[13]


D. Somasekhar, Y. Ye, and K.Roy, An energy recovery
static RAM memory core,
Proc. IEEE Symp, Low
Power Elect
ronics and Design
, pp. 62
-
63, 1995.

[14]


R. H. Dennand and D.J. Frank, Memory with
adiabatically switched bit lines,
U.S. Patent 5526319
,
1996.

[15]

S. Yang,
Logic Synthesis and Optimization Benchmarks
User Guide
. Tech. Rep., Microelectron. Center of North
Carol
ina, 1991
.
























Table
-
1:
Comparative results for the conventional and adiabatic synthesis averaged up to 300 MHz


Circuit
name


No.
of
inputs

No. of
outputs

No. of
nodes
in the

BDD

No. of
comple
-
mentary

pairs

No. of
nodes in
the
modified
BDD

Reduction
in nodes in
the
modified
BDD

Avg. power
consump
-
sion using
CMOS
MUX (nw)

Avg. power
consump
-
sion
using
adiabatic
MUX (nw)

Reduction
in power
in
adiabatic
MUX

count


35

16

98

32

66

32.65%

79206.54

33885.72

57.22%

1908


33

25

7560

1256

6304

16.61%

6110218.8

3236599.7

47.02%

f51m


8

8

56

16

40

28.57%

45260.88

20536.8

54.62%

k2


45

45

1002

191

811

19.06%

809846.46

416383.62

48.58%

pcle


19

9

43

8

35

18.60%

34753.89

17969.7

48.29%

t481


16

1

26

7

19

26.92%

21013.98

9754.98

53.57%

ttt2


24

21

124

24

100

19.35%

100220.52

51342

48.77%

vda


17

39

528

94

434

17.80%

426745.44

222824.28

47.78%

x2


10

7

40

7

33

17.50%

32329.2

16942.86

40.59%

Fig
. 8
: Dissipated energy for adiabatic MUX and static CMOS
MUX


Evaluate

Hold

Recovery

Wait


s



s



a



b



a



b



V
pwr


Fig. 7
: Input signal patterns for adiabatic MUX