Goshtasbi

G. & Alexander
Paper P20
1
On the Implementation of Finite State Machines of Moderate Complexity
Jamshid Goshtasbi

G
Arthur Alexander
Department of Electrical and Computer Engineering
College of Engineering, Architecture and, Computer Sciences
Howard University
Washington, DC 2005
9
Abstract
This paper describes an innovative and viable method for
the design and implementation of Finite State Machines
(FSM) of moderate complexity. A method developed for the
design and implementation of Finite State Machines (FSM) of
moderate comp
lexity is introduced in this paper. As a paper
and pencil alternative to using the Hardware Description
Languages (HDL), the presented method makes the design
and implementation of an FSM with a moderate number of
external inputs, transitions, and states
possible in a
considerably shorter process time. Recognizing the
incompleteness of the state transition space, the next

state
excitation functions logic is partitioned into two blocks: the
"transition conditions logic" and the "present state code logic."
The method provides a systematic approach for the
development of the aforementioned logic blocks and the
implementation of next

state excitation input equation simple,
two

level Boolean expressions in terms of the outputs of the
former. The method has bee
n introduced in a course in
advanced digital systems design; and has been used to design
a number of moderately complex FSMs. An example of such
design project is presented and discussed.
Key Words:
FSM Design, FSM Implementation, FSM
Synthesis
1.
I
NTRODU
CTION
Hardware Description Languages such as VHDL and
Verilog are routinely used in industry for design, simulation
and synthesis of large Finite State Machines (FSM). For less
complex systems, however, paper and pencil methods that are
based on classical
basic design process [1, 2] are used; but
such methods become impractical for more practical, typically
moderately complex systems that have four or more state
variables and several inputs. The hardware implementation of
such moderately complex state machi
nes becomes quite a
challenge. This is particularly true for the next

state

excitation
function logic where each equation is a function of a large
number of (state) variables and inputs. The Set OR Hold
Method, the Set OR Clear Method, and the Set

Clear Me
thod
[3] provide ways to write the excitation equations for flip

flops by inspection of the timing diagram, the state diagram,
and the ASM chart of the state machine. However, they do not
address the complexity (i.e., dependency on large number of
variable
s) of the next

state excitation equations. In fact, no
textbook could be found addressing this issue of the design
and implementation of finite state machines.
An innovative and viable method is introduced and
described in this paper that addresses the af
orementioned
issues in the design and implementation of Finite State
Machines of moderate complexity. The developed method is
based on the realization that the state transition space of such
FSMs is incomplete. Thus, the traditional definition of the
fini
te state machine is revised and reformulated using a set of
“transitions” rather than “external inputs.” This reformulation
of the FSM provides for the partitioning of the next

state
excitation functions logic into two blocks: the “transition
conditions” a
nd the “present state” logic. A systematic
approach results in the implementation of each next

state
excitation input equation as simple, two

level Boolean
expressions, with regular patterns of logic components that are
suitable for realization in VLSI. Se
ction 2 provides the theory
and develops the formulation of the methodology. The design
and implementation method is discussed in Section 3 and an
example is presented in Section 4. Conclusion remarks are
provided in Section 5.
2.
T
HEORY AND
F
ORMULATION
I
n a traditional definition of a finite state machine (FSM)
[4], M = (
I
,
O
,
S
,
,
), the state transition function
: (
S
I
S
) produces a set of transitions for
all
possible binary
combinations of the set of “external inputs”
I
and states
S
.
However, in
a moderately complex FSM (with moderately
large number of external inputs), typically, the “transition set”
is incomplete; i.e., the behavior of the FSM does not depend
on
all
(but a small subset of) possible binary combinations of
the external input vari
ables. Furthermore, transitions from
each state would make a small subset of the set of all
distinct
transition conditions. Thus, to exploit the aforementioned
incompleteness, we modify the formal definition of the state
machine such that the set of extern
al "inputs,
I
" is replaced
with the set of “transition conditions,
C
." The following
definitions further facilitate the modified formulation of an
FSM.
2.1. Definitions
1.
Transition Conditions:
A "transition condition,"
C
k
, is
a Boolean expression in te
rms of a subset of external "inputs"
of the FSM that
explicitly
describes the condition for a state to
undergo a transition. The set of transition conditions,
C
, is K

element complete. Each transition of the FSM is
explicitly
defined by an element from
C
.
The simplest distinct transition
condition is an AND of a subset of
external input literals
.
Goshtasbi

G. & Alexander
Paper P20
2
)
2
(
1
2
0
l
i
i
i
l
N
S
2.
Hold Condition:
A subset of distinct transition
conditions
explicitly
describes transitions that a state
S
i
undergoes. State
S
i
remains in hold for all o
ther possible
transition conditions. Such unused transition conditions are
called
hold
conditions.
2.2. Revised Finite State Machine Definition
By using the set of transition conditions (instead of set of
external inputs), the FSM is redefined as M = (
C
,
O
,
S
,
,
),
where
C
,
O
, and
S
are finite sets of
transition conditions
,
outputs, and states, respectively.
is the state transition
function: (
S
C
S
) and
is the output function: (S
C
O) in a Mealy FSM, or (
S
O
) in a Moore FSM. The FSM is
also
specified by its
J
inputs,
K
explicitly specified transition
conditions
,
L
outputs, and
N
state variables.
2.2. Formulation
Next

state excitation functions:
For the FSM to undergo
a state transition, the product of the condition
C
k
AND the
current state
S
i
must assert the
excitation inputs
of the
state
flip

flops
to either “0” or “1” according to the flip

flop’s
excitation table. Thus, the next

state transition function for the
state flip

flop
n
can be formulated in Equation (1).
Note that
C
n,i
is a set o
f all transition conditions that cause
state
S
i
to undergo transition by asserting the
excitation input
value of the state flip

flop
n
to “1.” Furthermore,
n
enumerate
all
N
state variables.
Output Functions:
In a
Moore Machine
, each
synchronous is simpl
y the sum of all states for which the
output
l
must be asserted “1,” as defined in Equation (2).
Note
that
l
i
is a coefficient ("1"/"0") indicating the assertion of
output
l
in state
i
.
For a
Mealy Machine
, the asynchronous outputs are
formulated similar
to
next

state excitation equations, as shown
in Equation (3).
Note that
C
l,i
is a set of all transition conditions that cause
state
S
i
to undergo transition and asynchronously asserting
output
l
to “1.”
3.
D
ESIGN
AND
I
MPLEMENTATION
M
ETHOD
As in other m
ethods, the design starts with the construction
of a state transition table from state diagram that is typically
derived from the behavioral description of the state machine.
Note that in the presented method all transitions are explicitly
described by tra
nsition conditions and identified as such on
the state diagram. The state transition table
—
the format of
which is shown in Figure1
—
is then constructed by inspection
from the state diagram. The entries of the rightmost column
(
n,k
i
) are the next

state exc
itation input values that will be
computed from state transitions and for the flip

flop type used
for the state register. This column is added for the design
purpose and is not part of the state transition table.
The underlying motivation in this meth
od is to take the full
advantage of the incompleteness of the state transition space
by listing only the
K explicitly
specified subset of transition
conditions for each state in the state transition diagram/table
and not to worry about the transition coeff
icients of
not

explicitly

specified
transition by setting them all to “0.” In
fact, Definition 2 and Equation (1) in parallel imply that next

state excitation inputs of all state flip

flops must be set to "0"
for not

explicitly used transition conditions
and cause "hold
conditions." The
toggle (T) flip

flop
, readily providing for this
"hold" condition, therefore, is chosen for the state register.
3.1. Implementation
The next

state

excitation functions logic is usually the
block that the implementation e
ffort is mostly focused on
[2][4][5]. Note that in the classical design methods, including
the newer design methods discussed in [3], each next

state
excitation input function is a combinational logic of (
J+N
)
variable. The main objective in the existing
methods is
twofold: (a) to simplify the next

state excitation input
functions and, (b) to use the PLD logic to reduce the hardware
complexity. Simplification by hand of these functions is
limited. Therefore, computer software such as
espresso
should
typi
cally be used for state machines with (J+N) larger than six
(6). Furthermore, the incompleteness of the state transition
space usually results in inefficient utilization of programmable
components (gates) when PLD devices (PROM, PAL, PLA)
are used. The d
eveloped implementation method presented
below provides improvement with respect to the
aforementioned issues.
Next

State Input
Functions:
Equation (1) allows us to
partition the next

state

excitation function logic into two
blocks: the "
transition conditi
on logic"
and the
"present state
code logic."
This partitioning is the fundamental difference
between the introduced method and the existing
implementation techniques. In the presented method, the
Figure 1. The State Transition Table
Present
State
Transition
Condition
NS Excit
ation
Input
Next State
Output
S
i
C
k
n,k
i
)
1
2
,
of
elements
(all
1
2
(3)
)
,
of
elements
(all
)
0
,
of
elements
(all
0
N
l
C
N
S
i
l
C
i
S
l
C
S
l
)
1
2
,
of
elements
(all
1
2
(1)
)
,
of
elements
(all
)
0
,
of
elements
(all
0
N
n
C
N
S
i
n
C
i
S
n
C
S
n
Goshtasbi

G. & Alexander
Paper P20
3
"external inputs" are thus omitted from the next

state
ex
citation input functions.
The needed state codes (
S
i
) are easily implemented with an
N:(2
N
) DECODER. The "
transition condition logic"
is a
multiple

output combinational logic, where output,
C
k
, is
typically a very simple function of a
subset
of the exter
nal
input variables. Each transition condition is then implemented
exactly
as its very simple Boolean expression. As such, this
partitioning
eliminates the need for any simplification
of the
(J+N)

variable next

state excitation input functions and/or
using
logic minimization software tools such as
espresso
.
Each next

state excitation input function can be
implemented with an AND/OR array logic: AND gates
provide the product terms of
S
i
and
C
k
, while the OR gates
combine them to implement the next

state ex
citation input
functions. All product terms are 2

input AND gates.
Output Functions:
The output functions are
implemented from the already available outputs of the above
two blocks, according to Equation (2) for Moore machines and
Equation (3) for Meal
y machines.
3.2. Design Time and Hardware Complexity
Existing classical design methods use logic simplification
on the next

state excitation input functions to reduce hardware
complexity. This process adds to the design time and the
required resources ev
en when computer

aided design tools
and PLD devices are utilized [5]. The developed method
provides improvements as follows:
The use of the K explicitly specified transition
conditions and the notion of "hold conditions"
eliminates the inclusion of all not

explicitly specified
transition conditions (external input combinations)
and makes the construction of the state transition table
significantly faster and straightforward.
No logic simplification is required for any of the logic
blocks of the partitioned
next

state excitation
functions logic.
As such, the developed method improves the design
time and results in a regular pattern of the
(component) structure of the next

state excitation
inputs blocks that make them suitable for realization
in VLSI
.
4.
E
XAMPLE
Several class projects in a digital systems design course
have been used to study and test the developed method.
Students were required to design and implement their
moderately complex FSMs by applying the introduced
methodology. One such example
FSM is a Timed

Light
Switch that turns a lamp on and off at preset times [2]. The
system has six inputs: RESET, Set Time, Set LiteOn, Set
LiteOff, RUN, and ADVANCE. A five position rotary switch
controls the first five inputs. These inputs cannot be ass
erted
simultaneously and the switch advances through RESET, Set
Time, Set LiteOn, Set LiteOff, and RUN in that order. The
ADVANCE input is generated using a push button switch.
When this input is asserted continuously, the displayed time
rapidly advances
through 24 hours. The system diagram of
this controller is illustrated in Figure 2.
The timed light switch typically operates in the RUN
mode. The light is turned on whenever the internal clock of
the system matches the internal register designated to th
e Set
LiteOn value (Lite On). The light is turned off whenever the
internal clock of the system matches the internal register
designated to the Set LiteOff value (LiteOff).
4.1. Operation
To operate the Times Light Switch, one must set the
current time,
then the on time for the light, and finally the off
time for the light. To accomplish this, the mode switch is
turned from RUN to RESET. This records the value 08:00
into the internal timer register. Next, the rotary switch is
turned to the set time pos
ition. At this time the ADVANCE
input can be asserted, this causes the timer register to rapidly
cycle through its possible values. When the switch is moved
to Set LiteOn, the value presently in the timer register replaces
the value in the internal clock
register. As this occurs, the
internal timer register is reset to 08:00. This
p
rocess is
repeated to set a time for the light to come on. In this case,
moving the switch to Set LiteOff causes the value in the timer
register to overwrite the LiteOn regis
ter. The process is again
repeated to set a time for the light to come off. In this case,
moving the switch to RUN causes the value in the timer
register to overwrite the LiteOff register.
4.2. Design and Implementation
The Timed Light Switch FSM was imp
lemented as a
Moore machine, with T flip

flops. A state diagram of the FSM
was first developed from the described operation of the Timed
Light Switch. There are a total of eleven (11) states and ten
(10) distinct transition conditions. The state transitio
n table
was developed and the
next

state excitation input equations
and
output functions
were derived. Tables 1 and 2 list the
transition conditions
and the
next

state excitation input
equations
, respectively.
TIMED LIGHT
SWITCH
FSM
RESET
SetTime
SetLightOn
SetLightOff
RUN
ADVANCE
LdClock
LdLiteOff
LdLiteOn
Count
LdTimer
Figure 2. The System Diagram of the Timed Light Switch
FSM
Goshtasbi

G. & Alexander
Paper P20
4
Equations in Table 2 where then implemented
by using the
developed partitioning method. Figure 3 shows the system
block diagram of the FSM. The partitioned next

state
excitation functions logic, Figure 4, consisted of a 4:16
DECODER (present

state code generator), the transition
conditions logic (C
ON_Log, a collection of ten (10) two

input
AND gates, shown in Figure 5), and four (4) AND/OR
combinational logic blocks for the next

state excitation inputs
of the T flip

flops.
T
1
, the largest of the four next

state
excitation input equations, was impl
emented with thirteen
two

input AND gates and three OR gates as shown i
n
Figure
6.
The regular pattern of the logic components of each sub

block and its easy realization became clear in this
implementation. In fact, while the design teams were not able
to
design/implement the assigned FSMs by using the
traditional methods, most teams did complet the design by
using the developed methodology in a short time. The
simulation of the designed FSM implemented in Electronics
Workbench verified the functionally c
orrectness of the
designed FSM.
5.
C
ONCLUSIONS
A viable method is developed for the design and
implementation of moderately complex finite state machines.
The classical definition of an FSM is modified and
reformulated to replace the set of external inpu
ts with the set
of transition conditions. This allows the reformatting of the
traditional state transition table that leads to portioning of the
next

state excitation functions logic into a "
transition
condition logic"
and
"present state code logic."
Nex
t

state
excitation input equations are then defined and implemented
Figure 3. The System Block Diagram of the Timed
Light Switch FSM
Figure 4. The Next

State Excitation (NS_Logic)
Logic of the Timed Light Switch FSM
Tab
le 1. Transition Conditions of the
Timed Light Switch FSM
Transition
Conditions
Expression
C
0
SetTime
Advance
C
1
SetTime
Advance'
C
2
SetLiteOn
C
3
SetLiteOn
Advance
C
4
SetLiteOn
Advance'
C
5
SetLiteOff
C
6
SetLiteOff
Advance
C
7
SetLiteOff
Advance'
C
8
Run
C
9
Reset
Table 2. Next

State Excitation Input Functions of the Timed
Light Switch FSM
T Input
Excitation Function
T
3
(S,C)=
T
2
(S,C)=
T
1
(S,C)=
T
0
(S,C)=
S
6
C
7
+S
7
C
8
+S
8
C
6
+S
10
C
9
S
3
C
3
+S
3
C
4
+S
6
C
7
+S
7
C
7
+S
7
C
8
+S
8
C
9
S
0
C
1
+S
1
C
1
+S
1
C
2
+S
2
C
0
+S
3
C
3
+S
3
C
4
+S
4
C
5
+
S
5
C
5
+S
6
C
7
+S
7
C
7
+S
7
C
8
+S
8
C
6
+S
9
C
8
+S
10
C
9
S
0
C
0
+S
1
C
1
+S
2
C
0
+S
2
C
2
+S
3
C
3
+S
4
C
4
+S
5
C
3
+
S
5
C
5
+S
6
C
6
+S
7
C
7
+S
8
C
6
+S
8
C
8
+S
8
C
9
Goshtasbi

G. & Alexander
Paper P20
5
as simple S.O.P. expressions of 2

input [(state)
(transition
condition)] product terms. One example where the developed
method has been used to design and implement an FSM is
discussed.
The presented results of the designed FSM,
implemented in the Electronics Workbench software and
simulated for testing its functional correctness, shows that the
method provides improvement with respect to the hardware
complexity, design time, and resource
s. The regular pattern
that emerges for each block in this method makes the
implementation suitable for realization in VLSI. Furthermore,
troubleshooting of the implemented FSM becomes very
simple due to this regularity.
R
EFERENCES
[1] F. J. Hill and G.
R. Peterson,
Introduction to Switching
Theory and Logical Design,
2
nd
edition, Wiley, New
York, 1974.
[2] R. H. Katz,
Contemporary Logic Design,
2
nd
edition,
Benjamin Cummings, New York, 2003.
[3] R. S. Sandige,
Digital Design Essentials,
Prentice Hall,
Ne
w Jersey, 2002.
[4] D. Leeand M. Yannakakis, "Principle and Methods of
Testing Finite State Machines

A Survey", Proceedings of
the IEEE, 1996,
84
, (8) pp. 1090

1123.
[5] C. E. Cummings, “The Fundamentals of Efficiently
Synthesizable Finite State Machine D
esign using NC

Verilog and BuildGates", International Cadence
Usergroup Conference, San Jose, CA, September 16

18,
2002.
Figure 5. Th
e Transition Conditions (Con_Log)
Logic of the Timed Light Switch FSM
Figure 6. A Next

State Excitation input Logic
(T1) of the Timed Light Switch FSM
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