Name: Sec: BN: VLSI Quiz The following figure shows a layout of a ...

stingymilitaryElectronics - Devices

Nov 27, 2013 (3 years and 10 months ago)

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Name:







Sec:



BN:

VLSI Quiz

The following figure shows
a

layout of a
NOR gate

implemented in a
one metal layer N well
CMOS process
. The layout is drawn on a
(
1 λ
)

grid

and it

has
several

errors
.


Identify the errors on the layout

and illustrate it be
low
.

(
Note the DRC table
).
















1)

N Well contact to VDD is missing.

2)

Metal width is less than minimum value (it’s 2λ and the minimum is 3λ)

3)

The contact isn’t connected through metal layer to GND.

4)

Not selected active, and active is outside select bou
ndary.

5)

Active overlap poly wrong dimensions and this causes a non existing transistor.

6)

This is N Select layer while we need P select to make a PMOS.