LESSON PLANLP EC2354 LP Rev. No: 00 Date: 13/12/10 Page 01 of 06 Sub Code/Name: EC2354-VLSI DESIGN Unit : I Branch : EC Semester: VI

stingymilitaryElectronics - Devices

Nov 27, 2013 (3 years and 9 months ago)

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DOC/LP/01/28.02.02



LESSON PLAN

LP


EC2354

LP Rev. No: 0
0

Date:
13
/
12
/
10

Page 01 of 06

Sub Code/Name:
EC
2354
-
VLSI DESIGN

Unit : I Branch : EC
Semester: V
I



UNIT

I
CMOS TECHNOLOGY











9

S
yllabus:


A brief History
-
MOS transistor, Ideal I
-
V characteristics, C
-
V characteristics,
Non ideal I
-
V

effects, DC transfer characteristic
s
-

CMOS technologies, Layout
design Rules, CMOS

process enhancements, Technology related CAD issues,
Manufacturing issues
.


Objective:

To
understand the
MOS transistor theory,

CMOS technologies and
the L
ayout







Session
No.


Topics to be covered

Time

Page
No

Ref

Teaching
Method

1.

Introduction

VL卉⁄敳ign

㔰5

1
-
4

1





N䵏匬S偍P匠Snhan捥
m敮t⁴ 慮sistor

㔰5

5
-
7,40

1

BB

3.

MOS transistor
-
Ideal I
-
V characteristics

50m

42
-
45

1

BB

4.

MOS transistor
-
C
-
V characteristics

50m

45
-
51

1

BB

5.

Nonideal I
-
V characteristics
-

velocity saturation
and mobility degradation,

channel length
modulation
, su
bthreshold conduction

50m

51
-
55

1

BB

6.

Threshold voltage, Body effect
, Junction leakage,

Tunneling, temperature dependence, Geometry
dependence

50m

55
-
60

1

BB

7
.

CMOS inverter DC characteristics
, Beta ratio
effects

100
m

60
-
65

1

BB

9
.

CMOS technology :
nwell, P well

Twin
well,
triple well,

50m

83,

15
-
21

1,
3

BB

10.

Layout design rules
-
NAND,NOR gat

50m

83
-
91

1

BB

11.

CMOS Process enhancement
-
SOI Process
,

Interconnects, circuit elements: Resistors,

50m

91
-
100

1

BB

12.

Circuit element: capacitor, CAD and

manufacturing issues

50m

107
-
109,149

1,2

BB




DOC/LP/01/28.02.02


UNIT II

CIRCUIT CHARACTERIZATION AND SIMULATION




9

Syllabus:

Delay estimation, Logical effort and Tran
sistor sizing, Power dissipation,
Interconnect, Design

margin, Reliability, Scaling
-

SPICE tutorial, Device
models, Device

characterization, Circuit characterization, Interconnect
simulation
.




Objectiv
e:




To
study the circuit characterization and performance estimation of CMOS
technology

.










LESSON PLAN

LP



EC
2354

LP
Rev. No: 0
0

Date:
13
/
12
/
10

Page

02 of 06

Sub Code
/Name:


EC
2354
-
VLSI DESIGN

Unit : II Branch : EC
Semester: V
I


Session
No.

Topics to be covered

Time

Page
No

Ref

Teaching
Method

1
3
.

Delay estimation
-
RC delay model,

Linear
delay model

50m

111
-
117
,245

1
,2

BB

14.

Logical effort

50m

118
,313

1,2

BB

15.

Transistor sizing

50m

118

1

BB

16.

Power dissipation
-
static and dynamic power

50m

129
-
135

1

BB

17.

Interconnect


Estimation o映牥sistan捥c
捡ca捩tan捥Ⱐd敬慹⁡ d⁣ oss⁴ lk


m

135
-
145ⰵ25

1ⰲ



ㄸ1

D敳ign慲ain

㔰5

145
-
148

1

B
B

†††
ㄹ1

剥Ri慢ility

㔰5

148
-
159

1



㈰2

卣慬ing

㔰5

159ⰲ29

1ⰲ



㈱2

卐䥃S⁴畴o物慬
,

D敶ic攠mod敬s


m

181
-
193

1



㈲2

D敶ice
&
Ci牣uit⁣h慲慣a敲i穡tionⰠ䥮t敲捯nn散t
simul慴ion

㔰5

193
-
213

1



㈳2

䍁T
-
1

㜵7

-

-

-


DOC/LP/01/28.02.02



LESSON PLAN

LP


EC
2354

LP Rev. No: 0
0

Date:
13
/
12
/
10

Page 03 of 06

SubCode/Name

EC
2354

-
VLSI DESIGN

Unit : III Branch : EC
Semester: V
I



UNIT III
COMBINATIONAL AN
D SEQUENTIAL CIRCUIT DESIGN

9





9

Syllabus:

Circuit families

Low power logic design


comparison of circuit families


Sequencing

static circuits, circuit design of latches and flip flops, Static
sequencing element

methodology
-

sequencing dyn
amic circuits


synchronizers

Objective:
To Understand the concepts of designing
combinational and sequential circuit
using CMOS logic configuration









Session
No.

Topics to be covered

Time

Page
No

Ref

Teaching
Method

2
4
.

Circuit families
-
static CMOS,ratioe
d circuit

50m

215
-
224,342

1,2

BB

2
5
.

Cascode voltage swing

logic,Dynamic
circuits

50m

225,361,

353

1
,2,3

BB

26
.

Pass
transistor,Differential circuits

50m

233
-
240

1

BB

27
.

BiCMOS,
Low power logic design


捯mp慲ason映 i牣uit⁦ milies

50m

241
-
245

1

BB

2
8
.

Sequencing

static circuits

50m

252
-
265

1

BB

29
.

C
ircuit design of latches and flip flops

50m

265
-
274

1

BB

30
.

Static sequencing element


50m

275
-
283

1

BB

31
.

S
equencing dynamic circuits

50m

284
-
289

1

BB

32
.

S
ynchronizers


50m

289
-
294

1

BB


DOC/LP/01/28.02.02



LESSON PLAN


LP


EC
2354

LP Rev. No: 0
0

Date:

13
/
12
/
10

Page 04 of 06

Sub Code/Name
:
EC2354

-
VLSI DESIGN



Unit : IV Branch : EC
Semester: V
I



UN
IT IV
CMOS TESTIN
G





9

Syllabus:

Need for testing
-

Testers, Text fixtures and test programs
-

Logic verification
-

Silicon

debug principles
-

Manufacturing test


Design for t
estability


Boundary scan
.


Objective:

To understand
the concepts of CMOS testing












Session
No.

Topics to be covered

Time

Page No

Ref

Teaching
Method

33
.

Need for testing

50m

531
-
536

1

BB

34
.

Text fixtures and test programs

50m

537
-
540

1

BB

35
.

Logic ve
rification
-

Silicon

debug principle

50m

541
-
544

1

BB

36
.

Manufacturing test

10
0m

544,621,239

1
,2,4

BB

3
8
.

Design for testability
-
adhoc tesing

50m

548
-
550

1

BB

3
9
.

Scan design

50m

550
-
555

1

BB

40
.

Built in self test,IDDQ testing


50m

555
-
558

1

BB

4
1
.


Boundary scan

50
m

559
-
570

1

BB

4
2
.

CAT
-
2

75m

-

-

-







DOC/LP/01/28.02.02




LESSON PLAN


LP


EC
2354

LP Rev. No: 0
0

Date:

13
/
12
/
10

Page 05 of 06

SubCode/Name:

EC
2354

-

VLSI DESIGN

Unit : V Branch : EC
Semester: V
I



UNIT V
SPECIFICATION USING VERILOG HDL





9

Syllabus:

Basic concepts
-

identifiers
-

gate primitives, gate delays, operato
rs, timing
controls,procedural assignments conditional statements, Data flow and RTL,
structural gate level
,
switch level modeling, Design hierarchies, Behavioral and
RTL modeling, Test benches,Structural gate level description of decoder,
equality detector
, comparator, priorityencoder, half adder, full adder, Ripple
carry adder, D latch and D flip flop
.


Objective:
To understand the concepts of modeling a digital system using Hardware
Description Language.

Session
No.

Topics to be covered

Time

Page No

Ref

T
eaching


Method

43
.

Basic concepts
-

identifiers
-

gate
primitives
,
, Design hierarchies

50m

47
-
48,72,106
,388

8,
2

BB

44
.

G
ate delays

50m

121

8

BB

45

O
perators

50m

138

8

BB

46.

Chip
T
iming controls

50m

171
-
178

8

BB

47.

P
rocedural assignments
,
conditional

statements

50m

166,179

8

BB

48.

Data flow and RTL

50m

131

8

BB

49.

S
tructural gate level

50m

373

8

BB

50.

S
witch level modeling

50m

383

8

BB

51.


Behavioral and RTL modeling, Test
benches

50m

385

8

BB

52.

Gate level verilog code
-
D
ecoder, equality
det
ector, comparator, priorityencoder

50m

136

8

BB

53.

H
alf adder, full adder, Ripple carry adder,
D latch and D flip flop
.


50m

452,414

2,4

BB

54.

CAT
-
3

75m

-

-

-


DOC/LP/01/28.02.02



LESSON PLAN


LP


EC
2354

LP Rev. No: 0
0

Date:

13
/
1
2
/
10

Page 06 of 06

SubCode/Name:

EC
2354
-
VLSI DESIGN

Branch : EC
Semester: V
I



Course Delivery Plan:


TEXT BOOKS:

1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005

2. Uyemura J.P:

Introduction to VLSI circuits and systems, Wiley 2002.


REFERENCES:

3.

D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003

4.

Wayne Wolf, Modern VLSI design, Pearson Education, 2003

5.

M.J.S.Smith: Application specific integrated circu
its, Pearson Education, 1997

6.

J.Bhasker: Verilog HDL primer, BS publication,2001




7.


Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003


8.Samir palnitkar,

Verilog HDL

,

Pearson Education
,second edition






Week

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

I II

I II

I II

I II

I II

I

II

I II

I II

I II

I II

I II

I II

I II

I II

I II

Units

1

1

1

1

1

1

2

2

2

2


2

C
A
T

1

3

3

3

3

3

4

4

4

4

4

5
C
A
T

2

5

5

5

5

5

5

C
A
T
3


-

-

-


Prepared by

Approved by

Name


M.ANUSHYA

Prof.E.G .Govindan

Designation

Asst
-

professor

HOD, Department of EC

Date