EEE-701

stingymilitaryElectronics - Devices

Nov 27, 2013 (3 years and 4 months ago)

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EEE
/
SVIST
/Progress Report/

01
JULY
.’1
3




LESSON PLAN


Name
: ARINDAM MONDAL




Designation
:

H
ead
O
f
D
epartment





Departm
ent


:

E
E
E


Academic
Year:

201
3


Sub:


VLSI & MICROELECTRONICS

(EEE
-


701

)


Stream
:

EEE


Total Number of Classes
:

4
5









S
l
.

No.

Main Topics

No. of
Periods

Tentative
Week/
Month

1.

VLSI Design Concepts, Moor's Law, Scale of Integrat
ion

(SSI, MSI, LSI, VLSI, ULSI


basic idea only)

3

3
RD


WEEK OF
JULY


2.

Types of VLSI Chips (Analog & Digital

VLSI chips, General purpose, ASIC, PLA, FPGA)

2

4
TH


WEEK OF
JULY

3.

Design principles (Digital VLSI

Concept of Regularity, Granularity etc
), Design
Domains (Behavioral, Structural, Physical), Y
-
Chart, Digital VLSI Design Steps.


3

4
TH


WEEK OF
JULY


4.

MOS structure
: E
-
MOS & D
-
MOS, Charge inversion in E
-
MOS

2

1
ST


WEEK OF
AUGUST


5.

Threshold voltage, Flatband voltage, Potential balance &

Charge balance, Inversion,
MOS capacitances.

2

1
ST


WEEK OF
AUGUST


6.

Body effect.

2

2
ND


WEEK OF
AUGUST

7.

Drain current, I
-
V characteristics. Current
-
voltage

equations (simple derivation).

2

2
ND


WEEK OF
AUGUST

8.

Short Channel Effects, General sc
aling,.


2

3
RD


WEEK OF
AUGUST

9.

Constant Voltage & Field scaling.

CMOS inverter

3

3
RD

WEEK OF
AUGUST

10.


Silicon Semiconductor Technology
-

An Overview, Wafer processing, Oxidation

2

4
TH

WEEK OF
AUGUST

11.

Epitaxial deposition, Ion
-
implantation & Diff
usion,

Cleaning, Etching, Photo
-
lithography


Positive & Negative photo
-
resist
.

3

4
TH

WEEK OF
AUGUST

12.

Steps in fabricating CMOS. Basic n
-
well CMOS process, p
-
well CMOS process, Twin
tub process, Silicon on insulator.

4

1
ST

WEEK OF
SEPTEMBER

13.

Stick

diagram with examples, Layout rules.

5

3
RD

WEEK OF
SEPTEMBER

14.

VHDL or Verilog Combinational circuit Design.

3

4
TH

WEEK OF
SEPTEMBER

15.

VHDL or Verilog Sequential Logic circuit Design.

3

3
RD


WEEK OF
OCTOBER

16.

VHDL Programming practices..

2

4
TH


WEEK OF
OCTOBER

17.

Doubt clearing session

2

2
ND


WEEK OF
NOVEMBER




S
ignature of the Faculty & Date


Signature of respective HOD & Date











Reviewed by
Principal

&

Date