CMOS VLSI Design

stingymilitaryElectronics - Devices

Nov 27, 2013 (3 years and 4 months ago)

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SUBJECT SYLLABUS

(
Major:

Electronics
-

Telecommunications
)


1.

Subject name
:

CMOS

VLSI

DESIGN

2.

Credit
: 3

(theory: 45 hours, project: 15 hours)

3.

Instructor
s
:


Dr. Tran Xuan Phuoc, MEng Tong Van On

4.

Department
:

Electronics

Engineering
, Faculty of Electrical
& Electronics

Engineering

5.

Objectives
:

Students will study the
design techniques and manufacturing technologies of
VLSI CMOS chips at present.

6.

Previous courses:

7.

Prerequisite
courses:

8.

Course Description:
This course shows MOS transistors
, CMOS logic cells an
d

logic
circuits, simulating MOS transistors and CMOS logic circuits,
transistor leve
l
combinational and
sequential citcuit design

using CMOS transistors
,
datapath and array
subsystem design.
CMOS process, f
abrication, packaging, testing and verification o
f
CMOS VLSI chip
s

are also included.

9.

Subject content
:


Theory: 45 hours


No

Contents

Hours

Refe
-
rence

1

Introduction


1.1 Basic CMOS logic

1.2
CMOS

Fabrication and Layout
.

1.3
Design Partitioning.

1.4 A simple MIPS microprocessor.

1.5
Logic Design.

1.6 C
ircuit Design.

1.7 Physical Design.

1.8 Design Verification.

1.9

Fabrication,
Packaging and Testing.

2


2

MOS

transistor theory

2.1 Introduction.

2.2
Ideal I
-
V Characteristics.

2.3
C
-
V

Characteristics.

2.4 Non
-
ideal I
-
V effects.

2.5 DC Transfer Characteri
stics.

2.6
Switch
-
level RC Delay Models.

4


3

CMOS

Processing Technology

3.
1 Introduction

3.2 CMOS Technologies.

3


Biểu mẫu 3

3.3 Layout Design Rules.

3.4

CMOS Process Enhancements.

3.5 Technology
-
related CAD Issues.

3.6
Manufacturing Issues.

4

Circuit Characteriz
ation and Performance Estimation

4.1
Introduction.

4.2 Delay Estimation.

4.3

Logic Effort and Trasistor Sizing.

4.4
Power Dissipation.

4.5 Interconnect.

4.6 Wire Engineering.

4.7 Design Margin.

4.8 Reliability.

4.9 Scaling.

3


5

Circuit Simulation

5.1 Int
roduction.

5.2
A SPICE Tutorial.

5.3 Device Models.

5.4 Device Characterization.

5.5
Circuit Characterization.

5.6
Interconnect simulation.

3


6

Transistor level combinational circuit design

6.1 Introduction.

6.2 Circuit Families.

6.3 Circuit Pitfalls

6.4

More Circuit Families.

6.5 Low
-
power Logic Design.

6.6 Comparision of Circuit Families.

6.7
SOI

Circuit Design.

4


7

Transistor level sequential circuit design

7.
1 Introduction.

7.2 Static Sequential Circuits.

7.3

Circuit design of Latches and Flipflops.

7.4 Static Sequential Element Methodology.

7.5 Dynamic Sequential Circuits.

7.6 Synchronizing Issues.

7.7 Pipelining.

7.8
Case Study: Pentium CPU.

4


8

Design Methodology and Tools

8.1 Introduction.

8.2 Structured Design Strategies.

8.3 Design Methods.

8
.4
Design Flows.

8.5 Design Economics.

8.6 ASIC


SoC.

8.7 CMOS Physical Design Styles.

8.8
Interchange Formats.

4


9

Testing and Verification

9.1 Introduction.

9.2 Testers, Test Fixtures and Test Programs.

9.3 Logic Verification Principles.

9.4 Debug Pri
nciples.

9.5 Manufacturing Test Principles.

9.6 Desing for Testability.

9.7 Boundary Scan.

9.8 System
-
on
-
chip (SoC) testing.

9.9 Mixed
-
signal Testing.

9.10
Reliability Testing.

4


10

Datapath Subsystem Design

10.1 Introduction.

10.2
Addition/Subtraction

1
0.3 One/Zero Detectors.

10.4 Comparators.

10.5 Counters.

10.6 Boolean Logical Operations.

10.7 Coding.

10.8 Shifters.

10.9 Multiplication.

10.10
Parallel Computations.

5


11

Array subsystem design

11.1 Introduction

11.2 SRAM.

11.3 DRAM.

11.4 ROM.

11.5 Ser
ial Access Memories.

11.6

Content
-
addressable Memories.

11.7 Programmable Logic Arrays.

11.8
Reliability and Self
-
test.

5


12

Special
-
purpose subsystem design

1
2.1 Introduction.

12.2 Packaging.

12.3 Power Distribution.

12.4 I/O.

12.5 Clock.

12.6
Analog Ci
rcuits.

4


Project
: 15 hours


No

Content

(select one of the following subjects)

Hours

Reference


Thiết kế logic chip VLSI.

Thiết kế vật lý chip VLSI.

Kiểm tra chip VLSI.

15

15

15

[1, 2, 3, 4]

[1, 2, 3, 4]

[1, 2, 3, 4]






10.

Reference Literature
:


11.

Evaluation
:

No

Method

Number of test

Weight
(%)

1

Mid
-
term test

1

20

2

Project

1

40

3

F
inal te
st

1

40




Instructor
s

[1] Nei
l H.E. Weste

and David Harris

CMOS VLSI Design: a circuits and systems perspective

Third Edition


2005.

[2] Magdy A. Bayoumi

VLSI Design Methodologies for Digital Signal Processing
Architectures


1998.

[3] C. Y. Chang and S.
M. Sze

VLSI Technology


19
98.

[4] Naveed A. Sherwani

Algorithms

for VLSI Physical Design Auto
mation

Third Edition


1999.