Digital Processing Element

steamgloomyElectronics - Devices

Nov 15, 2013 (3 years and 8 months ago)

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Digital Processing Element

for

LCLS Timing

Steve Smith

Aug 2012

Motivation

Needs:


flexible processing of analog signals


e.g.


Frequency


Bandwidth


We don’t always know which potential sources of error will
dominate




don’t know how to optimize up front


Stability of analog parts not
spec’d

at level needed


Example:


To get timing stability to 100
fs

when measured at 476 MHz
we need DC stability down at
-
70
dBc


Can use analog mixer


but requires DC stability to 1/3000


Linearity not well
spec’d

for many analog parts


ADCs/DACs well
spec’d



Examples


PLL detector


Quadrature

phase lock





Digital phase detector





Intermediate frequency (IF) Digital
downconversion

(DDC)


Phase difference done digitally



Frequency
-
agile phase detector

Basic Requirements vs. Nice Features

Minimum Requirement

Added

Functionality

Comment

Analog Inputs

Channels

2

4

e.g.

ref

+ 3 RF

signals

ADC bits

12

16

Effective bits

12

Sample Rate

1
Msample
/sec

100
Msample
/sec

Analog Outputs

Channels

2

4

{I,Q} for 1 or 2 channels

DAC bits

16

Update Rate

1 kHz

100 kHz

Misc

Interface

Standalone

UDP?

to control system

Algorithm

Program algorithm in some language.
Matlab
?
Labview
?

Compute

speed

Multiply/add per channel at

sample rate

Implementation


FPGA
Eval

boards


ADC/DAC on
eval

board


Or mezzanine board


Xilinx
eval

board


FMC mezzanine



Digilent

eval

board


FMOD connector





Xilinx System Generator allows algorithm development in
Simulink


Alternative: National Instruments FPGA board


Programmable in
Labview


Issues


Multi
-
vendor interfaces


HDL vs. high
-
level languages


maintainability