November 2, 2013
sawyes@rpi.edu
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1
ECSE

6230
Semiconductor Devices and Models I
Lecture 11
Prof. Shayla Sawyer
Bldg. CII, Rooms 8225
Rensselaer Polytechnic Institute
Troy, NY 12180

3590
Tel. (518)276

2164
Fax. (518)276

2990
e

mail: sawyes@rpi.edu
1
sawyes@rpi.edu
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November 2, 2013
Lecture Outline
•
PN Junction Models
–
Small Signal Model
–
SPICE Model
•
MOS Capacitors
–
Energy Bands
–
Accumulation, Depletion and Inversion
–
Surface Charges
–
Surface Potential
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Diffusion Capacitance
•
When
forward biased
, a significant
contribution to
junction
capacitance
come from the
rearrangement of the minority
carriers density
•
Diffusion capacitance is the
dominant capacitance component
for pn junctions under
moderate to
large forward biases.
•
Typically,
the
pn
junction
is
biased
with
a
large
(
0
.
7
V)
dc
bias
voltage
V
0
and
a
small
(
20

40
mV)
ac
voltage
V
1
.
V(t)
=
V
0
+
V
1
exp
(
j
t
)
J(t)
=
J
0
+
J
1
exp
(
j
t
)
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Small

Signal Model
•
Electron and hole densities at the depletion region can be
obtained from our previous equations (deriving Shockley
equation where:
•
Becomes
1st term

dc component
2nd term

small

signal ac component at depletion boundary
Similar expression for electron density, n
p
, on the p

side.
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Small

Signal Model
•
Substituting p
n1
into the continuity equation,
we have
Eq. (*) is analogous to the dc Diffusion Eq. if the
carrier lifetime is express as
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Small

Signal Model
AC Component
AC Admittance
Y = J
1
/ V
1
= G
d
+ j
C
d
Where G
d
is the diffusion conductance and
C
d
is the diffusion capacitance.
Both can be found and they are frequency dependent
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Small

Signal Model
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Small

Signal Model
•
Also,
C
d
decreases with
increasing frequency and for
large
, C
d

1/2
.
•
C
d
increases with increasing J
0
( or exp( qV
0
/kT )) and hence
is especially
important at low

frequency and under forward
biased conditions
.
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AIM

SPICE Model
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Introduction to MOS (or MIS)
•
Basic structure
•
Thermal Equilibrium
•
Band Alignment
•
Applied Bias
–
Accumulation
–
Depletion
–
Weak Inversion
–
Strong Inversion
•
Surface Charge
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MOS (or MIS), CCD
•
Metal

Oxide

Semiconductor (MOS) or
•
Metal

Insulator

Semiconductor (MIS),
•
The convention is that V is positive when the plate is
positively biased with respect to the semiconductor body
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MOS Capacitors
Vacuum level is a
continuous function of
position
Know electron affinity
of the insulator and
semiconductor
Know work function of
semiconductor and
metal
Separated materials
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MOS under Thermal Equilibrium
D
ox
=
ox
ox
= D
Si
=
Si
Si
ox
=
Si
(
Si
/
ox
)
3
Si
We can assume there is
some path
for transfer
so in thermal
equilibrium the fermi level can
align.
Voltage drop across insulator
A charge imbalance occurs because
of negative charges for equilibrium:
Work functions in metal is 0.8V less
than work function of silicon.
Leaves a sheet of positive charge at
the metal surface near the oxide.
An equal quantity of negative
charge is stored on the silicon side.
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MOS Capacitors
MOS capacitors with an applied bias:
(a)
Accumulation,
(b)
Depletion,
(c)
Inversion.
Ideal MOS capacitors are assumed:
(1)
V = 0, flatband condition.
V
FB
= 0.
ms
=
m

s
= 0.
M
= f(which metal),
s
= f( N
A
or N
D
).
For p

type semicond.,
ms
=
m

(
+ (E
g
/ 2) +
B
) = 0
(2)
No oxide charge.
(3)
No carrier transport across the insulator,
R
insulator
=
.
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Flatband Condition
N

type
P

type
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Accumulation
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Depletion
Inversion
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Surface Potential
Potential is defined as the
potential E
i
(x)/q with
respect to the bulk of the
semiconductor (band
bending)
ψ
p
=
ψ
P

type semiconductor
Electron and hole conc. as
a function of
ψ
p
Relate surface potential to
the width of the depletion
layer
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Q
s
vs.
s
•
Variation of surface
charge density as a
function of the surface
potential
–
Negative
ψ
s
, Q
s
positive,
accumulation, dominated
by first term in F
–
Ψ
s
= 0, Q
s
= 0 flat band
–
Positive
ψ
s
, Q
s
negative
,
depletion and weak
inversion, dominated by
2
nd
term in F
–
Strong inversion, function
F is dominated by fourth
term
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