Implementation of Silicon-on- Insulator Technology on CMOS Devices

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Implementation of Silicon
-
on
-
Insulator Technology on CMOS
Devices


N
OVEMBER
27
,
2007



Author

Dennis Mo

(17222715)




MSE
123
:
Semiconductor Processing

Department of Materials Science and Engineering

University of California

Berkeley, CA 94720




Page
2

of
8


Figure 1: a) Ideal SOI structure
, b) TEM
picture of SOI MOSFET

[1]

Implementation of

Silicon

on
Insulator Technology

on CMOS Devices


Abstract
: In this day and age, the challenges of shrinking microelectronics become more and more
apparent as Moore’s law
appears to slow

down. Silicon on insulator (SOI) technology addresses the
challenges that accompany the shrinkage of microelectronic devices

by providing

a different means of
isolation

using dielectrics instead of conventional p
-
n junctions in reverse bias.

Benefits incl
ude faster
transistor switching speeds, protection from leakage current, as well as lower power consumption
.

SOI
features
a thin layer of silicon on top of an insulator layer (frequently SiO
2
) that acts as a dielectric
separating the film of Si from the bu
lk substrate. Fab
rication is a challenge since
the top film
must be

a
thin single
-
crystal Si film while the SiO
2

dielectric is amorphous, which

poses many problems in
fabrication
.
1

Two industrially important fabrication methods will be discussed in this pa
per

the first
being SIMOX and a second method involving wafer bonding.

These methods of fabrication allow
microelectronics manufacturers to pu
sh Moore’s law to the limit in
the miniaturization of devices.


Introduction

Silicon
-
on
-
insulator (SOI) uses a thin film of
an insulating
dielectric, (typically
SiO
2
)

that separates a thin film of crystalline
silicon from the rest of the bulk silicon substrate.

His
torically, SOI
was developed as a

result of the need

for electronic materials that
could operate under radiation exposure,
but
today’s drive for SOI
development is motivated by the desire for faster performance
complemented with

lower power consumption.
1

The goal of the
SiO
2

in CMOS devic
es
layer is to
act as an insulator to isolate the
source and drain

in order to minimize current leak. Tradition
al bulk
silicon structures suffer from
parasitic capacitance as well as
leakage currents through the substrate between the source
,

drain
,

and gat
e
1
.

Short channel effects also arise from competing electric
fields from the gate as well as the source and drain regions.
SOI
attempts to eliminate these issues

by relying on thin films
.
Thus,
SOI is capable of lowering power consumption from these parasi
tic
effects, improving
device performa
nce, and then ultimately

aid
ing

in the continuing goal of
miniaturization
.

While the structure of an SOI device may sound somewhat
simple, there are many fabrication challenges that complicate this
seemingly simple lay
out.

The ideal SOI structure calls for a thin film of single crystalline silicon on the
surface, followed by a layer of amorphous SiO
2
, and then more single crystalline silicon as mechanical
support.

This can be seen in Figure 1 in both a schematic diagram and a TEM.

Most important
ly

the
difference
in structure
between SiO
2

and Si

make fabrication a challenge

Si is a crystalline material,
while
SiO
2

is amorphous.

This difference

i
n these two materials

makes it extremely difficult to pair them
in layers

because epitaxial growth of silicon requires

some sort of pre
-
existing lattice structure to grow
on
.
1,
2
, 3

Research has progressed in attempting to create templates for silicon to be grown on for SOI
ap
plications, but nothing commercially
feasible

has been produced yet.
As a r
esult, fabrication
of SOI
structures
must rely on a
lternate techniques such as the separation by implantation of oxygen (SIMOX)
or wafer bonding.
2, 3


SIMOX

The first method of fabr
ication of silicon
-
on
-
insulator
wafers and structures

that will be
discussed is known as separation by implantation of oxygen (SIMOX). In short, this method utilizes the
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3

of
8


Figure 2: Wafer structure dependence on ion
dosage at 500 °C implantation
temperature [4]

technique of ion implantation in order to "inject" oxygen atoms into the silicon substrate. High
temperature annealing follows which allows
the
oxide

lay
er to distribute itself evenly as

a thin film
underneath a monocrystalline silicon layer.

SIMOX
has bee
n found to be
very suitable for commercial

purposes and is capable of yielding thin film layers with high quality uniformity and low defect density.
6

SIMOX begins with ion implantation,
which refers to the
injection of atoms into a
specific target.
In the
case of SIMOX, the atoms being injected are oxygen atoms, and the target is the silicon substrate.

Ion implantation has been a technology present since 1952
5

and has been refined greatly so that it can
suit SOI fabrication.
Gas is ionized and then a
ccelera
t
ed

down a tube so that

oxygen ions can strike the
silicon wafe
r.

In general, the

number of atoms implanted

depend
s

on the dosage of incident ions as well as
the energy at which they strike the target.

These incident ions are accelerated through an electri
c field
so that they can strike the wafer surface.
Typical dosages for oxygen ions range from 10
17

cm
-
2

to 10
18

cm
-
2

while typical ion energies range from 50 keV to 200 keV.
1

By varying the ion ener
gy, the projected
range of the oxygen

ions can be controlled
to match the

desired
t
hickness of the surface silicon layer.

Operating temperatures for ion implantation need to remain high as to preserve the
mono
crystallinity of the

silicon
surface layer.

Incoming O
+

ions bombard the Si lattice,

causing recoil
which can then cause higher order displacements within the lattice. The net result can range from either
a defective region or even an amorphous region.
S
ufficiently
high dosages are nec
essary to help
create
an amorphous

buried oxide layer

(BOX)
.
Experiments show that temperatures of 500


600

°
C

are ideal
for the SIMOX manufacturing process.
1


Upon implanting oxygen atoms, the process of nucleation of SiO
2

precipitates begins.

Thermodynamics governs the growth of these precipitates as the
r
adial
size of these pre
cipitates
depends heavily on the temperature under which ion implantation is performed.

These precipitates are
driven to reduce their total free energy and so larger precipitates grow at the expense of smaller ones.

Coalescence may a
lso occur when multiple precipitates
come into contact with each other
. When the
density of precipitates is high enough, the system may seek to lower the total free energy through
coalescence.
6

Coalescence

helps develop the desired BOX in the SOI
structure.


S
ide Effects of SIMOX


One of the consequences of the ion implantation
process is the possibility of sputtering. Sputtering is a form of
physical vapor deposition (PVD) that occurs when incident
atoms strike a target with enough energy to
dislodge the
atoms in the lattice of the target.

In the case of SIMOX, O
+

ions are sometimes capable of dislodging Si atoms or even
SiO
2

molecules.
6

Th
us, controlling the dosage and incident
ion energy is critical to control the amount of sputtering.
Sputt
ering
is a form of erosion that will affect the thickness
of the

thickness of the film of SiO
2

and surface layer silicon.

As a result, the
dosage of incident oxygen ions as well as the
incident energy needs

to be carefully controlled as they have
significa
nt effects upon the film thickness.



While sputtering has a receding effect on the
thickness,
ion
implantation itself has a swelling effect due to
the
added presence of the
new ions
that are implanted
.

Figure
2

demonstrates the effect of varying the dosage

at a
fixed temperature. A high enough dosage is required in order
to
create a buried oxide layer
, and this is indicated by the
Page
4

of
8


Figure
3
:
Temperature dependence of the Si/SiO
2

interface in a high
temperature anneal for SIMOX.

[4]

critical dosage φ
c
.
Dos
ages
below this value are

too small
and
are
only
capable of
form
ing

precipitates
and lattice defects.

However, as the dosage increases, the crystallinity of the surface silicon layer begins
to suffer and
swelling effects become more pronounced. At the same

time, the effects of sputtering
become
increasingly noticeable, resulting in a net thickness somewhat thinner than what
the film
would
have been without the presence of sputtering.
1

Ion implantation also causes significant damage

despite taking place at h
igh temperatures
. This
is due to the collisions that the incident oxygen ions make

with the silicon lattice atoms that create
Frenkel pairs
.
6

Vacancies are also scattered across the structure in addition to
silicon dioxide
precipitates.


As a result
, annea
ling is required to repair the lattice damage.


High Temperature Annealing

The annealing process in
SIMOX is the second crucial step in
the manufacturing process. Following
ion implantation, the
implanted layer
needs
be transformed into a layer of
SiO
2

with an abrupt inte
rface with the
silicon crystal layers.
A
nnealing
helps
to o
b
tain
this

buried oxide layer (BOX)

by capitalizing on the principles of
diffusion and
th
er
modynamics
.
High
temperatures help dissolve small oxide
precipitates
created
from ion
implantation and also help redistribute
the amorphous phase into a BOX.
Thus
, t
he

high temperature anneal

convert
s

the
implanted
oxygen
into
a
SiO
2

layer

and also
give
s

the desired SOI structure

with abrupt interfaces between the silicon and
silicon dioxide
.
This can be shown in Figure
3

which illustrates a high temperature anneal providing a
desired SiO
2
/Si interface.
It can be seen that i
nsufficiently high temperatures will yield
poor quality
interfaces. Experiments have shown that 1350 °C is an optimal anneal
ing

temperature.
6

Additiona
lly,
annealing helps
to repair the damage in the silicon lattice caused by ion implantation
. Ion
Defects in the
silicon lattice such as interstitial or vacancy defects
result from ion implantation

and can hurt device
performance.

Proper annealing at high e
nough temperatures will
repair these lattice defects.

In thermal annealing it is
once again
important to preserve the
mono
crystallinity of the
silicon
surface layer.
The h
i
gh temperature environment

may cause unintentional oxidation of the surface layer
wh
ich results in thinning of that layer. One method that has been developed is to perform the annealing
process in an environment that is not favorable for
oxidation. Another method involves protecting the
surface silicon layer by using a capping layer.

The
implementation of a capping layer also prevents some
oxygen from being implanted into the BOX layer, resulting in a thinner layer than a wafer that does not
feature the capping layer.
6


Variations in SIMOX Process


In order for SIMOX to be us
ed
commercially, it needs to feature cost efficient processes to favor
mass production.

The dosage of oxygen ions is directly related to the operating cost, and

subsequently
much research has been done in the field of lowering the oxygen ion dosage.
Experimen
ts have shown
that

at certain ion energies, doses below the critical

can yield high quality thin SOI films.


T
hin
BOX layers
have their downsides too as there exists the possibility of thin silicon micropipes that can leak current
into the bulk substrate.
Methods such as internal oxidation (ITOX) have been used.
1

Page
5

of
8


Figure
4
: Depiction of the
BESOI

process.
[1]

Another variation in the SIMOX process is the use of patterned buried oxide. Certain CMOS
devices do not require a BOX across the entire wafer, or sometimes a combination of bulk silicon and
SOI is

desired.

A patterned oxygen implantation process can be performed followed by the ITOX process
which helps smooth out the new lateral Si/SiO
2

interfaces from the patterning.
1

Overall, the cost of SIMOX is still high, and cost is one of the main challenges

in helping
proliferate this fabrication method.
5



Wafer Bonding

The second method of fabrication of silicon
-
on
-
insulator chips that will be discussed is known as
wafer bonding. Wafer bonding processes involve bonding two halves of wafers together to form

a final
structure.

In order to create a bond between two surfaces, it would be ideal to create
two flat, clean
surfaces so that the molecules can come sufficiently close enough for bonding. However, this is of
ten
impractica
l as the costs are too high.

It

is much easier to rely on a chemically activated process

which
makes the two bonding

surfaces more reactive
7
.

Hydrogen bonding i
s a phenomenon that can be
suitable as long as hydrogen can be attached to these two surfaces.

Many chemicals can be used for
the

hydration

of the SiO
2

surface, ranging

from water to acids and bases.

Water is a typically used molecule
and is discussed furt
her.

The two surfaces are initially coated with OH groups and then fused together.
Now, the tem
perature is raised in a heating

process that
helps evaporate water

while bonding the two
wafers together
. Approximately 75% of the water

is then lost by diffusing through the SiO
2

layer.
8

During

diffusion
, some more silicon dioxide is formed

as oxygen reacts with the silicon lattice
, fr
eeing up
additional H
2

gas
. As temperatures surpass 800

°
C,
additional water leaves the bond interface, ultimately
allowing

the silicon dioxide layers to fuse together. This process can be described by the equation:

Si


OH + OH


SI


Si


O


Si + H
2
O

Mo
re water is freed up helping add to additional thickness of the BOX as well as free hydrogen atoms
that escape via diffusion.
7

The bonding step is only one crucial step in SOI fabrication by wafer bonding.

Processing still
needs to be performed on these wa
fers to obtain the desired SOI structure with desired characteristics.

This is where several processes come into
play
.
The industry uses several techniques that include bond
-
and
-
etchback SOI (BESOI), the Smart Cut


process, and the ELTRAN


process.
1

These processes, for the
most part, share many similarities, especially in the wafer bonding section of

fabrication, but t
hey differ
in the post
-
processing techniques required to attain a desired film thickness.


BESOI

One of the methods of wafer bonding is known as a
bond
-
and
-
etchback SOI process (BESOI).

The
wafer
can

first
be
grinded in a mecha
nical process and then polished using
chemical mechanical

polishing (CMP)
. However, is limited to
films thicker t
han 5μm as mechanical processes become
somewhat limited in the nano
-
scale regime.
1

Etching can be used
to attain finer detail by including an

etch
-
stop

into the wafer
prior to bonding
.

Since a chemically selective etch can be
performed, the etch
-
stop acts as a stop marker for the etching
process.
Thus, after bonding, a selective etch can be applied to
the wafer that will etch away the undesired portions of the
wafer, leaving a thin monoc
rystalline silicon surface film
.

This is
shown in Figure
4

where the silicon above the etch
-
stop is
eliminated after the BESOI process.

Unfortunately,

while etching
Page
6

of
8


Figure
5
: Depiction of the Smart Cut™ process

[1]

Figure
6
:
XTEM of h
ydrogen platelets from implantation

[1]

is chemically selective and can effectively remote undesired material, contamination of the

etch
-
stop
with the silicon layer will occur.
1

Thus, a more popular process, known as Smart Cut™ is being widely
used in the industry.


Smart Cut™

Process

Smart

Cut


is the
commercial name for a specific
process

of wafer bonding. It
features hydrogen ion implantation
which assists in slicing the silicon
wafer. This process has grown to
become a very popular form of
fabricating SOI wafers. Through ion
implantation, hyd
rogen atoms are
implanted into a silicon wafer
known as the "seed" wafer. This
seed wafer features a layer of
oxidized silicon which forms the
SiO
2
. These hydrogen atoms help
produce cavities within the silicon
lattice. At the same time, a "handle wafer,"
which features Si with a layer of silicon dioxide is prepared.
Both wafers are cleaned to ensure a clean contact surfa
ce in bonding. Next
, the "seed wafer" is flipped
upside down in order to be bonded with the "handle wafer."

2,3

Figure
5

illustrates the s
teps of
the
Smart Cut™
process, from hydrogen implantation
all to the splitting of the seed wafer.

In the hydrogen implantation process, the
hydrogen atoms help produce damage to the
silicon lat
tice structure by forming voids, platelets,
or micro
-
cavities.

Additionally, the hydrogen
atoms
bind themselves

to dangling Si bonds to
prevent the healing of these micro
-
cavities.
These
cavities grow

and build up until enough exist so
that the wafer plane

can be broken off by the
application of force.
7

In the end of Smart

Cut


process, the
"seed wafer" splits down the region of hydrogen
ion implantation. This process of mechanical splitting may feature some roug
h
ness. This can be fixed
through polishing wh
ich produces a
flat,
clean cut surface.
1

The newly bonded wafer is ready for further
processing while the "seed wafer" can be reused to create additional wafers.

A major challenge that exists in the
Smart Cut™
process is to avoid blistering. Blistering occurs
when a small chunk of the silicon wafer breaks off as a result of pressure buildup. Much effort has been
placed to reduce blistering, and one effective method has been to introduce a stiffener. The stiffene
r
helps stiffen the top layer of the wafer and also helps by redirecting pressure across the wafer rather
than upwards. In the case of
Smart Cut™
, the handle wafer serves as the stiffener.
1


There are many advantages of the
Smart Cut™
process, and one majo
r factor is the
differentiation between the seed and handle wafer. The seed wafer is the portion featuring the surface
silicon layer and so it must feature high quality silicon with minimal lattice defects. On the other hand,
the handle wafer acts as mecha
nical support, and can feature lower quality silicon.

Since the silicon film
Page
7

of
8


Figure
7
:
Depiction of the ELTRAN process

using two
layers of porous silicon.

[1]

and buried oxide layer are typically thin relative to the handle wafer layer
, only small amounts of high
quality silicon are needed

per structure whereas in bulk silicon, the enti
re structure will need to be of
high quality materials
. This helps reduce the amount of
high q
uality silicon processing needed, thus
cutting down on processing time and cost.
2,3

Furthermore, the ability

to control the Si film thickness and
the BOX layer th
ickness to the nanometer regime through hydrogen implantation makes the Smart Cut


process very versatile.
1

Finally, the versatility of the Smart Cut™ process as well as wafer bonding gives
rise to
the name “Silicon
-
on
-
Anything,” as this technology allows
wafers to be bonded onto many
different
materials.


ELTRAN Process

The
epitaxial layer transfer or
ELTRAN

process is another commercially used process

used to
create a thin layer of silicon.

This process relies on
the properties of porous silico
n in

aiding the

cutting
of
the silicon wafer. Porous silicon is mechanically
weak, but is capable of retaining the desired
monocrystallinity
.
7

Using an electroch
emical reaction,
porous Si can be created by an etching process.
Crystalline silicon can then be grown on top of this
porous layer and then later oxidized to form the seed
wafer.
Figure
7

shows the use of two layers of porous
silicon. The interface between

the two porous layers
has some interfacial stress which assists in the
cracking and
yields a cleaner cut than if only one
porous layer was used.
1

The seed wafer is then
bonded to the
handle wafer
in a process similar
to
the Smart Cut


process.

A powerful
water jet can then aid in cracking the wafer
around

the
mechanically weak porous silicon region.


Benefits from
SOI in Devices


The mentioned fabrication techniques are just a few out of many other methods.

Devices see
great leaps in improvement no matter which fabrication method is used.

Undesired characteristics such
as parasitic capacitance, latch
-
up, leakage currents, short channel effects, etc are reduced substantially
in SOI chips.
9

Furthermore, complicated
schemes such as forming wells and trenches are not needed
because of the lateral isolation that silicon
-
on
-
insulator technology provides.

Additionally, silicon
-
on
-
insulator is a very versatile technology that can be scaled to

foll
ow the miniaturization of MOS devices

as film thickness can be easily adjusted.


From a device performance standpoint, performance is greatly boosted in devices using SOI
while maintaining equal power consumption. Comparison at equal voltage of SOI devices

and bulk
silicon devices shows a 20%

-

30% lead for SOI devices.
1


Conclusion

Silicon
-
on
-
Insulator technology is critical for the continued development of CMOS devices

especially as fabrication nodes continue to shrink.

SOI will play a vital role as some
estimated 41% of
wafers will feature SOI technology by 2008.
6

Companies such as AMD
, Motorola,

and IBM have already
committed themselves to developing microprocessors that incorporate SOI technology, and many
others are following
suit.
1

Many new technologi
es also feature the use of SOI technology such as
strained silicon
.
SOI will surely see continued growth as nanoelectronics become ever more important.


Page
8

of
8


References


1

G. Celler, S. Cristoloveanu,
Frontiers of Silicon
-
on
-
Insulator

J. Appl. Phys. 93, p. 4955
-

4978 (2003)

2

Hambley, Allan,

Electrical Engineering, Principles and Applications

(Pearson
,
Upper Saddle River,
NJ, 2005
)

3

J
.
Wu
,
verbal communication
(2007)

4

J. Wu,
Lecture Notes, MSE 123

(2007)

5

S. Campbell,
The Science and Engineering of Microelectronic
Fabrication

(Oxford University Press,
New York, NY 2001)

6

P. Hemment et. al,
SIMOX

(MPG Books Limited, Bodmin, Cornwall, 2004)

7

Q.
-
Y. Tong, U. Gosele,
Semiconductor Wafer Bonding: Science and Technology,

(John Wiley &
Sons, New York, NY, 1999)

8

Mahajan, S. &
Harsha, K.S. Sree
,
Principles of Growth and Processing of Semiconductors

(
McGraw
Hill
,
New York, NY, 1999
)

9

Kasap, S.O.
,
Principles of Electronic Materials and Devices

(
McGraw Hill
,

New York, NY, 2005
)