1
ECE 465 Electronics Laboratory
Autumn, 2011
BJT Switching Characteristics
Samir Silbak
John Brady
Lab Start Date:
1
1
/
1
/2011
Submission Date:
11
/
7
/2011
2
OBJECTIVE
:
To identify and measure the
characteristic switching times of a bipolar transistor in the small
signal CE amplifier configuration and as a large signal RTL switch.
ANALYSIS
:
In order to derive expressions for the gain of the circuit, we were required to use Miller’s
Theorem for
Figure 1 as shown bel
ow. Derivation for
mid

band
frequency transfer function
using Miller’s Theorem
(This Derivation will be shown in the
appendices
)
:
Assume rb’b = 0
R
T
= R
S
R
B
1
R
B2
rb’e
R
Leq
= R
C
R
L
V
O
=

gm*R
Leq
*Vb’e
=

[
gm
*
R
Leq
*R
T
*V
i
] /
R
S
∴
k =

[
gm*R
Leq
*R
T
] /
R
S
Then we had to design the circuits for the resistances given in Table 3. When doing this, we had
to calculate the time constant for the circuit with these given values. We know that in order to
find the time constant of the
circuit we use:
τ = RC
Circuit #1

4
(Refer to Table 3 for Resistance values):
k =

gm * (R
L
R
C
R
Sin
)
τ
in
= R
in
*C
in
τ
out
= R
out
* R
in
Note
that these values change as the values of Resistances change as well
DESIGN:
Measured Equipment
:
Equipment
Used
Characteristic
Measured Value
Signal Generator
Output Resistance
50 Ω
Power Supply
Output Resistance
1 mΩ
Oscilloscope
Input Resistance
10 MΩ
Voltmeter
Input Resistance
>10 GΩ
Ammeter
Input Resistance
1 mΩ
Table
1
Circuits:
Characteristic
Given Value at Q

Point
Collector Current
1 mA
Collector

Emitter Voltage
11 V
Base Voltage
2 V
Power Supply Voltage
20 V
3
Table
2
Characteristic
R
S
Ω
=
R
L
Ω
=
V
out
amplitude
Circuit 1
0
15k
1

2 V
Circuit
2
15k
100
160 mV
Circuit 3
15k
560
400 mV
Circuit 4
1k
15k
1

2 V
Table
3
Figure
1
Figure
2
Characteristic
Given Value at Q

Point
Collector Current
1 mA
Collector

Emitter
Voltage
11 V
Base Voltage
2 V
Power Supply Voltage
20 V
Table
4
Once we used the curve tracer and these given values at the Q

point, we were able to retrieve a
base current value of 6 µA. Since, we know the base current is 6 µA, the base voltage to ground
4
has to be 2 volts, and our supply voltage is 20 V, we can then s
olve for R
B2
. Note, because we
want little amount of current going into the base of the transistor, we would say that in general,
about 10 times as much as the base current will flow through R
B1
and R
B2
. Keeping this in mind,
we can now solve for R
B2
.
Als
o because we were able to find our base current using the curve tracer, this made it simple to
find the gain of the transistor, β.
β = I
C
/ I
B
β = 1 mA / 6 µA
β =
156
Using the values given from the table above, R
B2
equals:
R
B2
= V
BB
/ 10*I
B
R
B2
= 2 V / 60 µA
R
B2
= 33.33 kΩ
Now that the value of R
B2
is known, we can solve for R
B1
using Thevenin’s equivalent:
V
BB
= [R
B2
/ (R
B1
+ R
B2
)] * V
CC
Rearranging this equation to solve for R
B
1
:
R
B1
= R
B2
* (1
–
V
BB
/V
CC
) * (V
CC
/ V
BB
)
R
B1
= 33.33 kΩ * (1
–
2 V / 20 V) * (20 V / 2 V)
R
B1
~ 300 kΩ
The next step consists of solving for R
E
:
We know that the voltage at the base is 2V, and because we have a 0.7 V drop across the Base

Emitter junction, this tells us that the Emitter voltage is
1.3V (2 V
–
0.7 V). Therefore doing
nodal analysis we can solve for R
E
:
R
E
= (V
E
–
0) / I
E
R
E
= (1.3 V
–
0) / 1.006 mA
R
E
~ 1.3 kΩ
Applying KVL from V
CC
down across the transistor, we can solve for the voltage across the load
resistance:
V
RL
= V
CC
–
V
CE

V
E
V
RL
= 20 V
–
11 V
–
1.3 V
V
RL
= 7.7 V
We know that the collector current, or the current across the load resistance is 1mA, therefore we
can now solve for R
L
:
R
L
= V
RL
/ I
C
R
L
= 7.7 V / 1 mA
5
R
L
= 7.7 kΩ
The next step consisted of calculating the capacitance values. The design requirement was to
determine the capacitance at low frequencies. In this case we calculated the capacitance at 10 Hz.
In order to solve for the input coupling capacitor, we went ah
ead and used this equation:
X
C
 = 1 / ω
L
C
C
X
C
is the collector resistance, ω
L
is the angular frequency at low frequency, and C
C
is the
coupling capacitance.
Rearranging the above equation, we can solve for the coupling capacitance equation:
C
C
= 1 / ω
L
X
C

Before we can calculate the output capacitance, we need to find the input resistance seen by the
input capacitor. The output resistance is found by:
R
i
= h
ie
// R
B2
// R
B1
where
h
ie
= β * r
e
r
e
= V
th
/ I
E
using
these relationships, we were able to find an input Resistance value of
3.8 kΩ
Now that we have the input resistance that the capacitor “sees”, we can solve for the capacitance
value:
C
C
= 1 / (2π*10*
3
.
8
k)
C
C
= 4
.
18
µF
In practice the output capacitance must equal the input capacitance. This is because in practical
applications, you will typically have two or more stage amplifiers; therefore you do not want the
output voltage or output capacitance to differ from the inpu
t voltage from other stages.
We use the same equation from above in order to solve for the capacitance at the emitter junction
(bypass capacitance).
C
E
=
1 / (2π*10*
1.3
k)
C
E
=
12.2
µF
Summary Table of Resistor and Capacitance values:
Characteristic
Value
R
B2
33.33 kΩ
=
R
B1
300 kΩ
=
R
E
1.3 kΩ
=
R
L
7.7 kΩ
=
C
C
4.18
µF
C
E
12.2
µF
Table
5
6
SIMULATION
:
Figure
3
–
Circuits developed for Resistor values shown in Table 3
Figure
4
–
Circuits
for the RTL BJT switch
7
Figure
5
–
Magnitude response of BJT
Figure
6
–
Magnitude response from large signal RTL BJT
8
Figure
7
–
Transient r
esponse of BJT
Figure
8
–
Collector Current Transient Response of BJT
9
Figure
9
–
Emitter C
urrent
T
ransient Response of BJT
Figure
10
–
Base Current Transient Response of BJT
Voltage
1
2
3
4
5
6
T
d
(µs)
N/A
0.153
0.27
0.29
0.33
0.35
T
r
(µs)
N/A
1.392
1.463
1.468
1.465
1.47
T
s
(µs)
N/A
0.08
0.065
0.056
0.037
0.016
T
f
(µs)
N/A
3.883
0.97
0.545
0.379
110.103
Table
6
10
Note that
1 V does not work since
there is not enough voltage to get across the 15K resistor to
get enough current to turn on the transistor
.
TEST RESULTS
:
Figure
11
–
Rise Time for R
S
= 0
Ω
and R
L
= 15k
Ω
(Circuit #1)
Figure
12

Rise Time for R
S
= 15kΩ and R
L
= 100Ω (Circuit #2)
11
Figure
13

Rise Time for R
S
= 15kΩ and R
L
= 560Ω (Circuit #3)
Figure
14

Rise Time for R
S
= 1kΩ and R
L
= 15kΩ (Circuit #4)
Figure
15
–
Rise Time for a 1V squarewave signal (inverted)
12
Figure
16
–
Fall Time for a 1V squarewave signal (inverted)
Figure
17
–
Delay Time for a 1V squarewave signal (inverted)
Measured Collector

Base, and Base

Emitter junctions of transistor:
Junction Capacitance
Measured Values
Collector

Base
3.25 pF
Base

Emitter
5.32 pF
Table
7
Input
Signal
Frequency
R
S
Ω
R
L
Ω
Delay
Signal
Rise
Time
Output
Signal
20 mV
200 kHz
0
15k
2.42 µs
243 ns
1.61 V
700 mV
200 kHz
15k
100
2.475 µs
90 ns
164.8 mV
180 mV
200 kHz
15k
560
2.31 µs
625 ns
400 mV
20 mV
80 kHz
1k
15k
5.91 µs
1 µs
1.35 V
Table
8
–
Measured Rise time for different R
S
and R
L
values
13
Voltage
1
2
3
4
5
6
T
d
(µs)
0.4
0.2
0.17
0.14
0.13
0.12
T
r
(µs)
1.21
1.26
1.29
1.31
1.33
1.35
T
s
(µs)
0.062
0.086
0.088
0.092
0.116
0.148
T
f
(µs)
5.68
1.1
0.66
0.5
0.4
0.34
Table
9
–
Measured
Delay, Rise, Storage, and
Fall Time for given input voltages
Current

Voltage Characteristics:
Measured
characteristics for the
BJT
:
Characteristics
Values
Early Voltage

262V
Saturation Voltage
12
0 mV
Breakdown Voltage
5
6
V
Table
10
If we take a look at the figures shown in the simulations, we can see what we are supposed to get
experimentally. In fact this is what we have seen in the lab as shown in the oscilloscope plots
shown up above.
We calculated the gains for circuit 1

4 to be

317,

6.16,

32.6, and

317,
respectively.
Now remember that for this lab, we are not trying to amplify our signal, in fact we
are trying to switch form saturation to cutoff mode as fast as possible. The first thing that had to
be done in this lab was to
measure the rise time of the circuit shown in figure 1. If we take a look
at table 8, we can see the measured rise time for this given circuit for given values of R
S
and R
L
.
Looking at table 8, we can see that the BJT is frequency dependent. Since we have different load
resistances, this will also affect how the BJT operates
—
in fact we can see the changes in our
risetimes for the given circuit shown in table 8.
In the second
part of the lab, we were required to see how varying the input voltage would affect
the delay, rise, fall, and storage time of the transistor.
Also figures 15

17 will show the results
that were measured in the lab. If we take a look at table 9, this will
show a complete summary.
Also in table 10, we can see that the saturation voltage was around 120mV. This is fairly well
compared to the ideal value (which is zero). We want our saturation voltage from the collector to
emitter junction to be as small as pos
sible, and 120mV is significantly small.
CONCLUSION:
The main purpose of this lab was to see the response of the BJT in Transistor Transistor Logic
(TTL), and to see how fast the BJT can switch from saturation mode to cutoff mode at a given Q

point.
We c
an take a look at the values measured in table 9. Our delay time decreased a little
once increasing the input signal.
Now one disadvantage we found was that when we increased
the input voltage, the rise time increased as well. Remember we want to be able t
o transition for
the 0 state to the 1 state as fast as possible. We can also see how the rise and fall time will affect
the storage time.
For more data, please refer to the tables shown above in this lab report.
From the measured values shown for the osci
lloscope we can see how the RC time constant
affects our signal tremendously. We can see that the input signal is a square wave; once the
signal passes through the RC network, we can see the delay respect to our input signal. This has
been an issue in the
computer world for many decades now. We want to be able to transition
14
from a logic 0 state to
a logic
1 state as fast as possible with the least amount of power given into
the system.
I learned that these bi

polar junction transistors are not only used f
or amplification purposes but
for TTL purposes as well. In fact we have always solved for the emitter and collector current at
the given Q

point, but this time we needed to worry about having a maximum emitter current
(which means maximum base and collecto
r current), a minimum voltage drop potential at the
base

emitter junction at one point
—
saturation mode of operation. Then at another point, we
needed to have the base and collector current close to 0 as possible, and the voltage potential
across the base

e
mitter junction needed to be reversed biased (<0.7V) so that the transistor would
not turn on. In the saturation mode, we would like to have a voltage across the collector to
emitter ideally to be 0V, but in reality this will not happen, and in fact we fou
nd a value of
120mV for the saturation v
oltage. This is still pretty good for the saturation voltage.
Now
because we want to make sure that the device is fully on, we need to make sure that the transistor
is forward biased (this could mean that the voltage
potential across the base

emitter junction >
0.7V). Now in the cut

off region, we want to make sure that there is no current flowing from the
collector to the emitter junction, therefore we make sure that there is not enough potential across
the base

emit
ter junction to have forward bias, which creates the transistor to operate as an “open
switch”.
Overall, we were able to see how BJT’s operate at a TTL level.
Our objectives were met, and the
data from the simulation, calculated, and measured values comp
ared fairly well. In conclusion,
we can say that this lab was a success.
QUESTION:
A.
Calculate a value of C
LEQ
from the risetime measurement of circuit #1.
Risetime = 24
3
ns. We know that the rise time is proportional to the time constant, giving
us the following equation:
τ = τ
R
/
ln(9)
τ =
24
3E

9
/
ln(9)
τ = 109 ns
We also know that the time constant in an RC network is:
τ = RC
Rearranging the above equation, we can
solve for C:
C =
τ / R
out
C = 109 E

9 / 4.2
k
C = 25.9
pF
B.
Calculate values of C
b’e
and C
b’c
from the risetime measurements of circuits #2 and #3.
Since we have the risetimes and the gains for circuits 2 and 3, we can use these values to solve
for the g
iven equation:
C
Leq
= C
b’e
+
C
b’c
(1
–
k)
15
Therefore, since we have two unknowns in this equation, and two equations, we can solve for
this linear solution, and we get a base emitter capacitance of approximately ~ 15.52 pF and a
base collector
capacitance of approximately ~ 4.21pF
C.
Use the results from parts A and B to predict the risetime of circuit #4.
We know that the gain for circuit 4 is

317
, and we can calculate the risetime by using the
following equation:
ln(9) *
τ = ln(9) * RC = 2.2
* 50E

6 ~ 1.1E

6
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