Packet Header Analysis and Field Extraction for Multigigabit Networks

sanatoriumdrumElectronics - Devices

Nov 25, 2013 (3 years and 11 months ago)

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Libor
Polˇc’ak

CESNET z. s. p. o.

Zikova

4, 160 00,

Prague, Czech Republic

Email:
polcak

l@liberouter.org

Petr

Kobiersk’y

Faculty of Information
Technology

Brno University of Technology

Boˇzetˇechova 2, 612 66,

Brno, Czech Republic

Email: ikobier@fit.vutbr.cz

Jan
Koˇrenek

Faculty of Information
Technology

Brno University of
Technology

Boˇzetˇechova 2, 612 66,

Brno, Czech Republic

Email:
korenek@fit.vutbr.cz

Proceedings of the 2009 12
th

International Symposium on Design and
Diagnostics of Electronic Circuits & Systems

學生

彭士家

1


INTRODUCTION


ARCHITECTURE


HFE GENERATION AND CONFIGURATION


RESULTS


CONCLUSION

2


We propose a new architecture of packet
header analysis and fields extraction
intended for high
-
speed FPGA
-
based network
applications.



Multiple chip solution can not be used in
many embedded devices because of cost,
size or power consumption.

3


A library of layered protocol processing
engines [7] has been introduced by John
Lockwood in FPX platform.


It is possible to achieve a modular design which
can support applications for different protocols
and level of abstraction.



A processing engine [9] in form of a state
machine described in high
-
level abstraction
language (Handel
-
C) was later proposed.


but still cannot be simply used for 10
Gbps

networks.


4


All introduced architectures suffer from
problems with adaptation to new network
protocols.



Another problem of available architectures is
a low throughput which limits their usage to
1
Gbps

networks only.

5


Our solution can balance between network
throughput and consumed hardware
resources.



We can dynamically react to new network
protocols thanks to automatic conversion
from protocol description in XML format.

6

Fig. 1. Block level diagram of HFE

7


The protocol analysis module is realized by a
Mealy machine and several internal registers
with associated combinational logic.



The machine is constructed automatically
from provided XML description of network
protocols.

8


The
header extraction module is controlled
by a microcode
stored in an on
-
chip memory.



The microcode is generated from the XML
description of the output frame.

9

Fig. 2. Extraction Engine

10


The proposed architecture can also deal with
nested protocols (VLANs, MPLS, IP over IP
tunnels).

11


We proposed XML
-
based abstract description,
which is used to specify following
information to custom core generator:


network protocols description


protocol header fields which will be extracted


extracted header fields position in output stream


width of the input packet stream

12


XML files can be modified by any text editor
and most of the current programming
languages have support for parsing
documents in the XML format.

13

Fig. 3. Processing engine generation and
configuration process

14


This schema was designed to be very simple
and intuitive with the ability to
express all
L2

L4 ISO/OSI protocols.

15

16


Definition 1.
A Protocol Analysis FSM is an 8
-
tuple
(
S, V,Σ,Λ,Δ, δ, S0, V0), where:


S is a finite set of states,


V is the finite set of internal variable names,


Σ
is the input alphabet,


Λ
is the output alphabet,


Δ
is the internal alphabet,


S0 is the initial state which is an element of S (S0


S),


V
0
is a finite set of initial values for each variable
from
V (V
0


Δ
|
V |
),


δ : S
×
Δ|V |
×
Σ


S
×
Δ|V |
×
Λ is a transition function

17

18


The
extract attribute enables
to select
whether the first or the last occurrence of
the header field is extracted.



A single control word is generated for each
transition. This word contains command for
each input byte which controls:


byte extraction,


position in the output stream,


overwriting of already extracted value (nested
protocols).

19


The proposed architecture was evaluated on
Xilinx
Virtex

5 FPGA.



We have defined four protocol sets in XML
language and used them for proposed HFE
engine evaluation.

20

21


We have performed the Synthesis and Place
& Route for all generated designs using Xilinx
ISE tool.

22

The results show that the maximum frequency for different
protocol sets is almost the same.

23

Table III also shows that the increase of occupied area with

added support for more protocols is very low.

24

The higher throughput can be achieved not only by increasing

of the input data width but also by flexible packet distribution

between several processing units with lower throughput as

can be seen in Fig. 6.

25

26


Consume only small amount of FPGA
resources.


Enables to optimize architecture for defined
parameters and balance between consumed
hardware resources and network throughput.


Reduces the time required for providing
support to newly issued specifications of
network protocols.



future work will focus on performance
optimizations that enable to reach higher
system frequency.


27