Embedded Systems paper 2003-2004 Answer All questions in Section A, plus 2 questions from Section B. Section A. Answer all questions 60 marks total. The numbers in the following description refer to diagram 1, which is a representation of a data

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Nov 25, 2013 (3 years and 4 months ago)

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Embedded Systems paper

2003
-
2004



Answer All questions in Section A, plus 2 questions from Section B.


Section A. Answer all questions 60 marks total.


The numbers in the following description refer to diagram 1, which is

a representation of a data
trans
fer sessions between two machines.


A character orientated serial communication protocol allows the

transfer of data packets. In order
to transmit data packets the

stations must agree to connect (1). The client can then transmit

messages to the server.
The messages can start with an optional

header (2)

and is then followed by
data packets each terminated by an

ETB character (3). The final packet must be terminated by an
ETX

character (7). Each packet must be either acknowledged (ACK)

(4) or

negatively
acknowledged (NACK) (5).The NACKed data must be

retransmitted

(6). All packets out of
sequence or with faulty checksums

must be negatively acknowledged.


Client











Server






ENQ
-
SYN
-
SYN
-
>







1





<
-
ACK
-
SYN
-
SYN





BCC
-
ETB
-
data1
-
STX
-
h
eader1
-
SOH
-
SYN
-
SYN
-
>


2





<
-
ACK
-
SYN
-
SYN












BCC
-
ETB
-
data2
-
STX
-
SYN
-
SYN
-
>




3





<
-
ACK
-
SYN
-
SYN





BCC
-
ETB
-
data3
-
STX
-
SYN
-
SYN
-
>





<
-
NACK
-
SYN
-
SYN






5





BCC
-
ETB
-
data3
-
STX
-
SYN
-
SYN
-
>




6





<
-
ACK
-
SYN
-
SYN








BCC
-
ETB
-
dataN
-
STX
-
SYN
-
SYN
-
>









............





BCC
-
ETX
-
data3
-
STX
-
SYN
-
SYN
-
>




7





BCC
-
ETB
-
data1
-
STX
-
header2
-
SOH
-
SYN
-
SYN
-
>





<
-
ACK
-
SYN
-
SYN





..........


A
1 For the above protocol draw up a finite state diagram of phases 2

through 7 on
diagram 1 for the
client. This is the phase dealing with

data packet reception and
acknowledgment
. Your FST
should deal with

the optional header.











(10 Marks)

A2

Draw up a state transition table for the finite state machine in

question A1
. Provi
de comments
giving
further

details of states and

transitions.











(10 Marks)

A3

Discuss what ways you would approach coding the design give in

questions A1&A2
. Show
various ways of representing the design in a high

level language. Give code exampl
es in your
answer.











(12 Marks)

A4

Discuss how your design might deal with situations such as repeated

negative acknowledges
(NACK) of packets, or lack of ACKS for correctly transmitted messages.











(13 marks)

A5

If you were called upon to i
mplement such a protocol on a series of

small embedded systems,
describe

how you might approach such a task.

Outline some of the difficulties that cross developing
such a system

may provide.











(8 Marks)

A6

Using the Technical Summary Sheet for the

Motorola 68307

microcontroller (Appendix A),
outline how the resources on such a chip

could be useful in implementing a system, such as that
presented in

questions A1&
A
2
.











(7 Marks)



Section B. Answer 2 questions only. 20 marks per question


B1

Cross developing code from host development systems to target boards with different
processors and operating environments presents the programmer with extra challenges and
problems.


i) In light of some of the special problems embedded systems programm
ing presents, discuss
how you would approach

developing an application that would run on an embedded system.
Consider what factors would influence your selection of tools


compiler, linker and so on.











(10 marks)


ii)
Below is a list of tools th
at would be used by a developer for embedded sy
stems. For 4 of
the tools give

a description of the special features and facilities that the embedded systems
programmer would be looking for
:




gcc/cc


gld/ld


gas/as


objcopy


ar/ranlib


make


gbd
/debug


t
arget











(2.5

marks

each
)


B2

Developing code for a single board application requires the linking of high
-
level language
programs with assembler level code.


i) Discuss the circumstances under which a programmer would code in an assembler rather
th
an a high level language.











(10 marks)


ii) Using code fragments and diagrams in your answer, show how the linkage of high
-
level
language procedures and functions with assembler code is facilitated. Give particular
emphasis to the role of local
variable storage and the passing of parameters.











(10 marks)


B3

C is the main language used in embedded system development.


Using the following code fragments discuss some of the features of C that leads to its popularity in
the cross developmen
t field. In your discussion also highlight some of C’s weaknesses.



char *mem_pointer;



mem_pointer = (char *) UART_1;



while ( *(mem_pointer+2) | RX_RDY )



:/*do nothing*/



volatile const unsigned int time;














(20 marks)


B4

Use the C co
de and register diagrams in appendix B in answering this question.


i Describe the function of the UART registers; Mode Register 1 (UMR1), and Status
Register (USR) given in appendix B.











(4 marks)


ii The CMS FM200 boards run serial data

at 38400 baud using hardware flow control, 1 stop
bit and no parity. Show using diagrams, pseudo code and code fragments, where necessary,
how you would initialise the 68307 UART for such transmissions, paying attention to the
order in which initialisat
ions must take place.











(9 marks)


iii Write get and put functions to input and output byte data for the UART.











(7 marks)


Appendix A

Techni
cal Summary

Integrated Multiple
-
Bus Processor


The MC68307 is an integrated processor combinin
g a static 68EC000 processor with multiple interchip bus
interfaces. The MC68307 is designed to provide optimal integration and performance for applications such
as digital cordless telephones, portable measuring equipment, and point
-
of
-
sale terminals. By
providing 3.3
V, static operation in a small package, the MC68307 delivers cost
-
effective performance to handheld,
batterypowered applications. The MC68307 (shown in Figure 1) contains a static EC000 core processor,
multiple bus interfaces, a serial channe
l, two timers, and common system glue logic. The multiple bus
interfaces include: dynamic 68000 bus, 8051 bus, and Motorola bus (M
-
bus) or I
2
C bus
1
. The dynamically
sized 68000 bus allows 16
-
bit performance out of static random access memory (SRAM) while

still
providing a low
-
cost interface to an 8
-
bit read
-
only memory (ROM). The 8051 bus interfaces gluelessly to
8051
-
type devices and allows the reuse of application specific integrated circuits (ASICs) designed for this
industry standard bus. The M
-
bus is

an industry standard 2
-
wire interface which provides efficient
communications with peripherals such as EEPROM, analog/digital (A/D) converters, and liquid crystal
display (LCD) drivers. Thus, the MC68307 interfaces gluelessly to boot ROM, SRAM, 8051 devic
es, M
-
bus
devices, and memory
-
mapped peripherals. The MC68307 also incorporates a slave mode which allows the
EC000 core to be turned off, providing a 3.3
-
V static, low
-
power multi
-
function peripheral for higher
performance M68000 family processors.




Th
e main features of the MC68307 include:

• Static EC000 Core Processor

Identical to MC68EC000 Microprocessor


Full compatibility with MC68000 and MC68EC000


24
-
bit address bus, for 16
-
Mbyte off
-
chip address space


16
-
bit on
-
chip data bus for MC68000 bus ope
rations


Static design allows processor clock to be stopped providing dramatic power savings


2.4 MIPS performance at 16.67
-
MHz processor clock

• External M68000 Bus Interface with Dynamic Bus Sizing for 8
-
bit and 16
-
bit Data Ports

• External 8
-
Bit Data Bu
s Interface (8051
-
Compatible)

• M
-
Bus Module


Provides interchip bus interface for EEPROMs, LCD controllers, A/D converters, etc.


Compatible with industry
-
standard I
2
C bus


Master or slave operation modes, supports multiple masters


Automatic interrupt ge
neration with programmable level


Software
-
programmable clock frequency


Data rates from 4

100 Kbit/s above 3.0
-
MHz system clock

• Universal Asynchronous Receiver/Transmitter (UART) Module


Flexible baud rate generator


Based on MC68681 Dual Universal Asyn
chronous Receiver/Transmitter (DUART) programming model


5 Mbits/s maximum transfer rate at 16.67
-
MHz system clock


Automatic interrupt generation with programmable level


Modem control signals available (CTS,RTS)

• Timer Module


Dual channel 16
-
bit genera
l purpose counter/timer


Multimode operation, independent capture/compare registers


Automatic interrupt generation with programmable level


Third 16
-
bit timer configured as a software watchdog


60
-
ns resolution at 16.67
-
MHz system clock


Each timer has an

input and an output pin

• System Integration Module (SIM07), Incorporating Many Functions Typically Relegated to External
Programmable

Array Logic (PALs), Transistor
-
Transistor Logic (TTL), and ASICs, such as:


System configuration, programmable address m
apping


System protection by hardware watchdog logic


Power
-
down mode control, programmable processor clock driver


Four programmable chip selects with wait state generation logic


Three simple peripheral chip selects


Parallel input/output ports, some wit
h interrupt capability


Programmed interrupt vector response for on
-
chip peripheral modules


IEEE 1149.1 boundary scan test access port (JTAG)

• Operation from DC to 16.67 MHz (Processor Clock)

• Operating Voltages of 3.3V

0.3V and 5V

0.5V

• Compact 100
-
Lead Quad Flat Pack (QFP) Package



Appendix B

C and assembler code for the 68307 UART module



#include <minos.h>

#include <stdio.h>

#define
MBASE

0x120000

#define
UCR


(MBASE+0x105)

#define
UACR


(MBASE+0x109)

#define
U
CSR


(MBASE+0x103)

#define
USR


(0x103)

#define
URB


(0x107)

#define
UTB


(0x107)


#define RESET_MP


0x10 // reset mode register pointer

#define
RESET_RX


0x20

#define RESET_TX


0x30

#define
RX_TX_DSBL

0xA

#define
BRG_SET1


0x0 // which baud rate settings?

#define
RX_TX_38400

0xCC

#define
RX_TX_2400


0x88

#define RX_TX_9600


0xbb

#define RX_TX_TIMER

0xdd

#define
RX_TX_ENB


0x5 //enable rx and tx

#define
RX_RDY



0x0 //bit masks for RX

#define
TX_RDY



0x4 //and TX


main()

{


char * mp;






printf("starting...
\
n");



mp = (char *) UCR;


*mp = RESET_MP;


*mp = RESET_RX;


*mp = RESET_TX;


mp = (char *) UCSR;


*mp = RX_TX_38400;


mp = (char *) UCR;


*mp = RX_TX_ENB;




/*#asm commented out assembler


move.l

#$100105,A4


move.b

#$20,(A4)


mov
e.b

#$30,(a4)


move.l

#$100103,a4


move.b

#$cc,(a4)


move.l

#$100105,a4


move.b

#$5,(a4)

#endasm

*/

printf("done....
\
n");


}


68307 UART Register diagrams


Mode Register 1
UMR1




MBASE +0x101


7


6

5

4

3

2

1

0

RxRTS RxIRQ ERR PM1

PM0 PT B/C1 B/C0





RxRdy: Set RTS flow control on receive. 1=RTS, 0=no RTS.

RxIRQ: Set interrupts on receive.
1=FIFO generates IRQ, 0=RxRDY generates IRQ.

ERR: Error mode, 1= block mode error control.
0=single character

error control.

PM1
-
0: Parity Mode, selects the type of parity used


see table

PT: Parity type


used in conjunction with PM bits


see table

BC1
-
0: Bits per character. See table.


PM1

PM0

Parity Mode

PT

Parity Type

0

0

With Parity

0

Even Parity

0

0

W
ith Parity

1

Odd Parity

0

1

Force Parity

0

Low Parity

0

1

Force Parity

1

High Parity

1

0

No Parity

X

No Parity

1

1

Multidrop Mode

0

Data Character

1

1

Multidrop Mode

1

Address Character


BC1

BC0

Bits/Character

0

0

Five bits

0

1

Six bits

1

0

Seven bit
s

1

1

Eight bits




Mode Register 2
UMR2




MBASE+0x0101


7


6

5

4

3

2

1

0

CM1 CM0 TxRTS TxCTS SB3 SB2 SB1


SB0



MC1
-
0: Channel mode


select the channel operation these setting are normally used for debugg
ing
software without having to debug the actual connection, see table


CM1

CM2

Mode

0

0

Normal

0

1

Automatic echo

1

0

Local loopback

1

1

Remote Echo


TxRTS: Flow control on transmit.1=RTS on transmit, 0=no flow control.

TxCTS: Flow control on transmit. 1=
CTS on transmit, 0=no flow control.

SB3
-
0:Stop bit length. This is also dependant upon the number of bits per character. The truncated
table below gives the only 2 settings you are likely to need.


SB3

SB2

SB1

SB0

Length 6
-
8 Bits

Length 5 Bits

0

1

1

1

1
.000



1.500

1

1

1

1

2.000



2.000



Status Register
USR






MBASE+0x0103

7

6

5

4

3

2

1

0

RB

FE

PE

OE

TxEMP

TxRDY

FFULL

RxRDY


RB: Received break. 1=break character received, 0=break not
received.

FE: 1=No stop bit received, 0=stop bit received.

PE: 1=parity error occurred,0= no error.

OE: 1=overrun error occurred, 0= no error.

TxEMP: 1= transmitter empty, underrun error,0=no error

TxRDY: 1=transmitter buffer is empty and ready to tran
smit,0=transmit register full.

FFULL: 1=char received and FIFO full,0=FIFO empty.

RxRDY: 1=char waiting in received buffer,0=no char waiting.


Clock Select Register
UCSR




MBASE+0x0103

7

6

5

4

3

2

1

0

RCS3

RCS2

RCS1

RCS0

TCS3

TCS2

TCS1

TCS0


RCS3
-
0: Re
ceiver clock select bits, see table.

TCS3
-
0: Transmit clock select bits, see table. The sets are selected by setting bit 7 of the Auxiliary
Control Register (UACR). 0=set 1, 1= set 2.



R/TCS3

R/TCS2

R/TCS1

R/TCS0

SET 1

SET 2

0

0

0

0

50

75

0

0

0

1

110

1
10

0

0

1

0

134.5

134.5

0

0

1

1

200

150

0

1

0

0

300

300

0

1

0

1

600

600

0

1

1

0

1200

1200

0

1

1

1

1050

2000

1

0

0

0

2400

2400

1

0

0

1

4800

4800

1

0

1

0

7200

1800

1

0

1

1

9600

9600

1

1

0

0

38.4k

19.2k

1

1

0

1

TIMER

TIMER

1

1

1

0

-

-

1

1

1

1

-

-





Command Register
UCR





MBASE+0x0105

7

6

5

4

3

2

1

0

-


MISC2

MISC1

MISC0

TC1

TC0

RC1

RC0


MISC2
-
0. Miscellaneous commands


see table


MISC2

MISC1

MISC0

Command

0

0

0

No command

0

0

1

Reset MR pointer

0

1

0

Reset R
X

0

1

1

Reset TX

1

0

0

Reset Error status

1

0

1

Reset Break
-
change Int

1

1

0

Start Break

1

1

1

Stop Break



Reset MR pointer. Re
-
access the UMR1 register.

Reset RX. Reset and disable receiver


clears RxDRY and FFULL bits in the USR. Places receiv
er
in known state.

Reset TX. Reset and disable transmitter


clears TxDRY and TxEMP bits in the USR. Places
transmitter in known state.

Reset Error status, break change Int. These reset the various error bits on the USR and UISR
registers.

Start and st
op break. Force the transmission of a break character.


TC1
-
0 & RC1
-
0 transmitter and receiver commands


see table


TC1
-
RC1

TC0
-
RC0

Command

0

0

No action

0

1

Enable transmitter(TC) or receiver(RC)

1

0

Disable transmitter(TC) or receiver(RC)

1

1

Do no
t use





Receiver Buffer
URB






MBASE+0x0107

7

6

5

4

3

2

1

0

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0


RB7
-
0.
These bits hold the received data for the UART. Data here is indicated by the setting of
the RxRDY and FFULL bits in the USR.



Tra
nsmitter Buffer
TRB





MBASE+0x0107

7

6

5

4

3

2

1

0

TB7

TB6

TB5

TB4

TB3

TB2

TB1

TB0


TB7
-
0. These bits hold the transmit data for the UART. Data in TRB clears the TxRDY bit in the
USR, blocking further transmission, TxRDY is set by th
e transmission of the data.


Input Port Change Register
UIPCR



MBASE+0x0109

7

6

5

4

3

2

1

0

-


-

-

COS

-

-

-

CTS



This port reflects the state of the CTS pin.


COS. Reflects a change in the state of the CTS pin.

CTS. Reflects the curre
nt setting of the CTS pin.


Auxiliary Control Register
UACR



MBASE+0x0109

7

6

5

4

3

2

1

0

BRG

CTMS2

CTMS1

CTMS0

-

-

-

IEC


BRG. Selects the table of baud rates for the UCSR. 1 = set 2. 0 = set 1.

CTMS2
-
0.. Counter timer mode select. T
here is only one legitimate setting for these


0 0 1. This
selects counter mode with an external clock.

IEC. This bit, when set to 1, generates interrupts on the COS bit of UIPCR.




Points for Credit


1a
































FSD
-

extra marks for dealing with SOH & STX correctly. Marks for higlighting

problems of time out. Dealing with non
-
storage of data after bad BCC.


1b Marks for delaing with repeated transmission of bad packets
-

ie a badbcc

coun
t. Details on data storage and bcc check.


State

Event


Action


Next State

Comment

S0

SYN


-


S1

S0

!SYN


-


S0


TIMEOUT required?

S1

SYN


-


S1


TIMEOUT?

S1

STX|SOH


-


S2

S1

!SYN|STZ|SOH

-


S0


TIMEOUT

S2

ETX


-


S3



S2

ETB


-


S4

S2

!ETX | ETB

store
data

S2


Buffer overflow?

S3

BADBCC

Send NACK

S0


clear buffer

S3

GOODBCC

Send ACK

S0


save buffer

S4

BADBCC

Send NACK

S5


clear buffer

S4

GOODBCC

Send ACK

S5


save buffer

S5

SYN


-


S6

S5

!SYN


-


S5


TIMEOUT required?

S6

SYN


-


S6


TIMEOUT?

S6

STX


-


S
2

S1

!SYN|STX

-


S5


TIMEOUT


1c. Discussion of styles of coding FSD. Use of switch and if else.

! SYN|STX

BADBCC

SYN

SYN

BADBCC

ETB

!
ETX|ETB

!SYN| STX
!SOH

ETX

STX|SOH

GOODBCC

S0

S1

S3

SYN

S2

S4

S5

GOODBCC

S6

STX

SYN

Good for trivial design
-

> 6 states starts to become a

problem. Example of coding style. Using look up tables, pointers to

functions. Use of dispatch loop.

Easy to code STT into large C

structure. Use of information strings for debugging. Exampleof coding

style.


1d. Problem of timeouts. Really requries some form of ISR based on a

timer. Each state sets the timer going on entry and resets on exit.

Would
also need some counter for bad packets
-

could be a floating value to

vary dependant upon the loading/stress of the system.


1e. Use of simulation to test and debug design first off. Modular

code
-

try to locate likely system/hardware dependencies
-

ie

timer

code, serial port handling. Unit testing of each module.

Difficulties of isolating errors. Use of loopback modes
-

local and

remote on UART. Use of serial line monitors. Difficulties of debugging

interrupt code.


1f.General system requires
-

ra
m rom etc. Serial port requirement
-

only 1 on the board so probelms there! Timer chips
-

2 is useful as

one can be for OS other for application. Useful digital io
-

ie

diagnositic leds, keypads, lcds could be useful.


Section B


1B


i Use of simulation

and unit testing very important. Requires careful
segregation of hardware specific code. Tools need to produce stand alone code.
Need to be targeted at hardware


and all family variants. Need to be able to
see assembler output


go documentation of AL
P HLL interface. More knowledge on
the hardware and how it is initialised. Debugging is much more difficult.
There is a download phase.

ii Compiler, assembler output, cross assembler. Ability to turn off
optimisation. Relocatable code. Linker


abil
ity to place segments in
specified locations, creation of map file, linker control languages.

Easy of
loading different libraries esp. startup libs.Static and dynamic linking. Gas
ability to inline assemble, standard assembler, easy of linking alp & hll.

Variety of processor families. Objcopy


to produce various output format


ie
srecord intel hex, as well as coff elf et al. Production of libraries


ability
to easily maintain libs, extraction.

Make ability to control complex builds,
use of compiler

flags, difficult command lines, ability to create various
version


ie production and debug. Gdb


standard features


single step, break
points, trace, register/memory dumping, disassembly, remote debugging a la gbd.
Target


ability to reconfigure for
various boards/targets, ability to
download/upload binaries.


B2Details on link and ulnk commands


_get:


link

a5,#
-
46


a5 frame pointer, 46 bytes







storage



unlk


a5


move.l

8(a5),d0

get hold of parameter n


move.l

12(a5),a0

get hold of parameter s
2


move.l

16(a5),a1

get hold of parameter s1



3B. C use of pointers, pointer arithmetic, bitwise operators, storage classes such as volatile for rt
applications, can generate small code, often translate well into assembler language, easy to embed
and li
nk assembler. Problems with portability, no interrupt support, can be difficult to read,
sometime as difficult as assembler.



4B i Discuss the various type of registers, mode, data and status. Go through the various settings,
baud rates, bits per char

etc

ii normally disable rx & tx, set up mode registers, wait for settle time, check status registers for
data, space or errors, send or receive data.

iii

/* messages */

#define


PAPER_OUT

-
1



#define


DE_SELECT

-
2

#define


YES


0

#define


NO


-
1

#de
fine


OK


0

#define

void


int


/* address, offsets and setting for M68681 DUART */

#define


DUART


0XFFFF81

/*base address*/

#define


ACR


8


/*aux control reg */

#define


CRA


4


/*command reg A */

#define


MRA


0


/*mode reg A */

#define


CSRA


2


/*cl
ock select A */

#define


SRA


2


/*status reg A */

#define


RBA


6


/*rx reg A*/

#define


TBA


6


/*tx reg A */

#define


RXRDY


1


/*rx ready bit */

#define


TXRDY


4


/*tx ready bit */


/*

Settings for the Motorola M68230 Parallel Interface Timer


These
only deal with mode 0.0 , and for ports B and C


No details about the timer.

*/


/* PI/T offsets and adresses */

#define

PIT


0Xffff41

/*address of PI/T */

#define


BCR


0Xe


/*offset for port B cntrl Reg*/

#define


BDDR


6


/*offset for B data direction*
/

#define


BDR


0X12


/*offset port B data reg */

#define


CDR


0X18


/*offset port C data reg */



#include "io.h"

/* set up bowman 68681 duart serial port A only */

int TFLAG;

void dinit()

{


volatile char *p;


int i;




p = (
char *)DUART;


*(p+ACR) = 128; /* set baud rate */


*(p+CRA) = 16; /*reset rx */


*(p+MRA) = 19; /*no modem,prty 8 bits */


*(p+MRA) = 7; /*no echo no modem cntrl, 1 sb */


*(p+CRA) = 5; /*enable rx & tx */



*(p+CSRA)= 187; /*rx & tx at 9600 */





p = ( char *) PIT; /* set to base address of PI/T */


*(p + BCR ) = MODE0; /* mode 0.0 */


*(p + BDDR ) = OUT;




for(i=0; i != 1000;i++)



;/*delay*/



}


/* set up 68230 PIT for print out on port B */

void pinit()

{


char *p;


p = ( char *) PIT; /* set to base address of PI/T */


*(p + BCR ) = MODE0; /* mode 0.0 */



*(p + BDDR ) = OUT;



}


/* get char from serial port A returns character */

char get()

{


volatile char *p;




p = (char *)DUART;




while ( !( *(p+SRA) & RXRDY ))


; /* do nothing */



return *(p+RBA);

}

/* put character c to serial port A */

char put(c)

char c;

{


volatile char *p;




p = (char *)DUART;




while ( !(
*(p+SRA) & TXRDY ))


;/* do nothing */


*(p+TBA) = c;

}

/* put string to serial port A using put routine */

puts(p)

char *p;

{


while( *p )


put(*p++);


put('
\
n');


}