Accellera Systems Initiative Overview

sanatoriumdrumElectronics - Devices

Nov 25, 2013 (3 years and 8 months ago)

100 views

Accellera

Systems Initiative Overview

Bill Read | August, 2012


© 2012 Accellera Systems Initiative, Inc.

August, 2012

Accellera Systems Initiative

Our Mission


To provide design and verification
standards required by systems,
semiconductor, IP and design tool
companies to enhance a front
-
end
design automation process
.


To collaborate
with its community
of companies, individuals and
organizations
in delivering the
standards that lower the cost to
design commercial
EDA, IC
and
embedded system solutions.

2

© 2012 Accellera Systems Initiative, Inc.

August, 2012

Broad Industry Support

Diverse Membership from EDA Vendors, IP Suppliers,
Semiconductor Manufacturers and System Houses

Corporate Members

Associate Members

3

© 2012 Accellera Systems Initiative, Inc.

August, 2012

Why Standards?

4


Design
tools & methodologies continue to evolve rapidly

-
Simulation

-
Emulation

-
IP integration

-
DFx

Architecting
DFx

-
Mixed environment


Standards help reduce overcall cost of migrating design, IP & tools

© 2012 Accellera Systems Initiative, Inc.

August, 2012

Accellera Systems Initiative

Supported IEEE Working Groups

1800
SystemVerilog

Karen Pieper

Tabula

1801 UPF

John Biggs

ARM

1076 VHDL

Jim Lewis

SynthWorks

1666 SystemC

Stan Krolikoski

Cadence

SystemC

TLM

Bart
Vanthournout


Synopsys

SystemC AMS

Martin
Barnasconi

NXP

SystemC

CCI

Trevor
Wieman


Intel

IP
-
XACT

Christian
Fraisse

STMicrosystems

VIP

Hillel Miller

Freescale

Tom Alsop
Intel

IP Tagging

Kathy Werner

Freescale

Technical Committee

Karen Pieper,
Tabula

Board
of
Directors

Shishpal

Rawat
,
Intel

Marketing Committee

Thomas Li,
Springsoft

Administration

SystemC


Language

David Black

Doulos

SystemC


Synthesis

Andres Takach

Calypto

UCIS

Richard Ho

DE Shaw

OVL

Kenneth Larson

Mentor Graphics

Verilog
-
AMS

Scott Little

Intel

Interface

(ITC)


Brian Bailey

EDA
DesignLine

5

SystemRDL

Oren
Katzir

Intel

© 2011
-
2012 Accellera Systems Initiative, Inc.

2012



2011



2
010



2009



2
008



2007



2
006



2005



2
004



2003



2
002



2001



2
000

Accellera Standards Success

Accellera formed from
VI & OVI

Corporate
IEEE Member

IEEE IPR
adopted

Merger with

SPIRIT

Merger with
OSCI

OVL

1.0

1.8

2.1

2.3

2.4

2.5

2.6

V
-
AMS

2.0

2.1

2.2

2.3

2.3.1

SV

3.1

3.1a

IEEE 1800

PSL

1.1

IEEE 1850

UPF

1.0

IEEE 1801

ITC

1.0

1.1

2.0

2.1

2.2

UCIS

1.0




VHDL

1.0

3.0

3.1

4.0

IEEE 1076

UVM

1.0 & 1.1

OCI

1.0

IEEE 1450

IP
-
XACT

1.5

IEEE 1685

2.0

6

© 2012 Accellera Systems Initiative, Inc.

August, 2012

2012

OSCI Standards Success

LWG

1.0

2.0

2.1 & IEEE 1666
-
2005

2.2 & IEEE 1666
-
2011

2.3

TLM

1.0

2.0

SCV

1.0

1.0p2

SWG

Draft 1

Draft 2

AMS

AMS Study Group

Draft 1

1.0

CCI

Requirements

1.0

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

OSCI

formed

IEEE

1666
-
2005

released

OSCI

10 year
anniversary

IEEE

1666
-

2011

Merger

with

Accellera

7

© 2012 Accellera Systems Initiative, Inc.

August, 2012


UVM and IP
-
XACT


SystemC and IP
-
XACT

System
-
Level IP
Integration


Verilog
-
AMS,
SystemVerilog AMS,
SystemC AMS


UVM, TLM
-
2.0, CCI


SystemC and UCIS

Synergies and Future Opportunities

Mixed
-
Signal Design &
Verification

System
-
Level
Verification

8

© 2012 Accellera Systems Initiative, Inc.

August, 2012

EDA and IP Design Standards and
Initiatives

9

System
C

Design

Testbench

SoC

Integration

SV
-
AMS

UPF

SDF

OCI

OVL

VHDL

Verilog

System
-
Verilog

UVM

SCE
-
MI

IP
-
XACT

IP
-
Tagging

UCIS

© 2011
-
2012 Accellera Systems Initiative, Inc.


Verification Intellectual Property (VIP) Universal Verification Methodology (UVM) 1.1


Open Verification Library (OVL) 2.6


Verilog
-
AMS (V
-
AMS) 2.3.1


Standard Co
-
Emulation Modeling Interface (SCE
-
MI) 2.1


Unified Coverage Interoperability Standard (UCIS) 1.0


IP
-
XACT
-

Update to IEEE 1685


Intellectual Property (IP) Tagging


SystemC Synthesizable Subset Draft 1.3


SystemC Analog Mixed
-
Signal (AMS) 1.0


SystemC Configuration, Control & Inspection (CCI

Requirements)


SystemC Language Standard


SystemRDL (launched)


Transaction Level Modeling (TLM) 1.0 and 2.0


Open Source Companions:


-

UVM Reference Implementation 1.1


-

SystemC Proof of Concept Library (POCL)

-

SystemC

Verification Library
1.0p2

Current Standards

10
th

Annual DVCon


Our flagship conference

Ongoing Technical Activities

10

© 2012 Accellera Systems Initiative, Inc.

August, 2012

Strong Relationship with IEEE


Using Get
IEEE
program to allow access to EDA standards

-
IEEE
1666
SystemC


-
IEEE
1685
IP
-
XACT


Accellera Systems Initiative Continues IEEE Standards Association
Advanced Corporate Membership

-
1076
VHDL

-
1666
SystemC
Language

-
1685
IP
-
XACT

-
1800
SystemVerilog (SV)

-
1801
Unified Power Format (UPF)



-
1850
Property Specification Language (PSL)


11

© 2012 Accellera Systems Initiative, Inc.

August, 2012

What’s Next?


Universal Verification Methodology (UVM) 2.0


Verilog and SystemC Analog/Mixed
-
Signal (AMS)


SystemC Configuration, Control, & Inspection (CCI)


IP Tagging


IP
-
XACT


SystemRDL

12

© 2012 Accellera Systems Initiative, Inc.

August, 2012

13

Global Events
2013


Silicon Valley: DVCon 2013 and North American SystemC
Users Group Meeting


Germany: DATE 2013 and European SystemC Users Group
Meeting


Bangalore: India SystemC Users Group Meeting, Spring
2013


Austin, TX: DAC 2013


Japan SystemC Users Group, July 2013


Taiwan SystemC Users Group, Fall 2013


© 2011
-
2012 Accellera Systems Initiative, Inc.

Summary


Accellera

Systems Initiative is
the standards body
for front
-
end design and IP integration


Ongoing Integration of Accellera and OSCI


Strong collaborative relationship
With the
IEEE

A robust organization serving the electronics industry since 1987!

www.accellera.org

14

©
2012
Accellera Systems Initiative, Inc.

August, 2012

15

© 2012 Accellera Systems Initiative, Inc.

August,
2012

Acronyms & Definitions


AMS:
Analog/Mixed Signal


CCI:
Configuration, Control & Inspection


DVCon:
Design & Verification Conference


EDA:
Electronic Design Automation


GET:
Free IEEE LRM download program


IC:
Integrated Circuit


IP:
Intellectual Property


IPR:
Intellectual
Property
Rights


IP
-
XACT
:
Metadata standard for
IP integration


IEEE
:
Institute of Electrical and Electronics
Engineers


ITC:
Interface Technical Committee


LWG:
Language Working Group


OCI:
Open Compression Interface


OSCI:
Open SystemC Initiative


OVI:
Open Verilog International


OVL
: Open Verification Library


PSL:
Property Specification Language


SDF:
Standard Delay Format


SC:
SystemC


SCV:
SystemC Verification



SPIRIT:
Structure for Packaging, Integrating,
and Reusing IP within Tool
-
flows


SV:
SystemVerilog


SWG:
Synthesis Working Group


TLM:
Transaction
-
Level Modeling


UCIS:
Unified Coverage Interoperability
Standard


UPF:
Unified Power Format


UVM:
Universal Verification Methodology


V
-
AMS:
Verilog
-
Analog/Mixed Signal


VHDL:
VHSIC Hardware Description Language


VI:
VHDL International


VIP:
Verification Intellectual Property

16

©
2012
Accellera Systems Initiative, Inc.

August, 2012

17

Recent Accomplishments


Completed
the
merger
to form the Accellera Systems Initiative


Hosted two SystemC User Group meetings in Taiwan


Held a session
at IP
-
SOC in Grenoble, France about our EDA and IP
Standards Roadmap


Published SystemC AMS extensions white paper


Completed next revision of the SystemC LRM, IEEE 1666
-
2011, which is
available for free download


Continued interest in our IEEE 1685 (IP
-
XACT) standard with over 4000
free downloads to date


Released Video Tutorial "Software
-
Driven Verification Using TLM
-
2.0
Virtual
Platforms“


Released Unified Coverage Interoperability Standard (UCIS) 1.0


Released the SystemC
2.3
Library


Accellera Systems Initiative Technical Achievement

and Leadership
Awards