VLSI Design Automation

salamiblackElectronics - Devices

Nov 27, 2013 (3 years and 8 months ago)

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VLSI Design Automation

D. Zhou,

Page
1

11/28/2013

VLSI Design Automation


I
nstructor D. Zhou

zhoud@utdallas.edu

phone: 972 883 4392


Th
is

course
focuses on the
algorithms occurred

in
VLSI design automation
.
Particularly,

i
t
addresses
the typical issues
related to

VLSI physical design,
verification, and hi
gh
-
level synthesis.
Detailed topics include:


1.

Introduction to VLSI design automation

1.1

VLSI design

1.2

CAD (or EDA) tools

1.3

Introduction to algorithms

1.4

Computational complexity

2.

Physical design

2.1

R
outing

2.2

Interconnect circuit order reduction

2.3

Buffer sizing and insertion

2.4

C
lock
signal distribution

2.5

F
loor plan

and placement

3.

Verification

3.1

Equivalent checking

3.2

SAT problem

3.3

Integer programming

4.

High
-
level synthesis

4.1

Scheduling

4.2

Resource allocation



VLSI Design Automation

D. Zhou,

Page
2

11/28/2013

Grading policy:

H
omework
-
>15%, reading assignment
-
>15%, middle term project
-
>30%,

and final project
-
>40%.

85
-
100
-
>A, 70
-
84
-
>B, 60
-
69
-
>C, below 60
-
>F


Reference:

1.

N. Sherwani, “Algorithms for VLSI Physical Design,” Kluwer Academic
Publishers, 1999.

2.

T. H. Cormen and
etc.
, “Introduction to Algorithms,” McGraw
-
Hill, 2001.

3.

M. R. Garey
and D. S. Hohnson, “Computers and Intractability,” W. H.
Freeman and Company, 1979.

4.

S. M. Rubin, “Computer Aids for VLSI Design,” Addison
-
Wesley, 1987.

5.

W. Wolf, “Modern VLSI design,” Prentice Hall, 2002.

6.

N. Weste and K. Eshraghian, “Principles of CMOS Desi
gn,” Addison
-
Wesley Publishing Company, 1993.