ECE 425
Introduction to VLSI System Design
Course Goals
This course provides an introduction to the design, layout, and testing of VLSI circuits
for complex digital systems. The goals are to enable students to design circuits using
custom and cell

based a
pproaches, generate layouts, verify the designs, apply tests to
manufactured chips, and understand the algorithmic aspects of VLSI CAD tools.
Instructional Objectives
A. By the time of Exam No. 1 (after 14 lectures), students should be able to do the
fol
lowing:
1.
Show
the basic steps of CMOS IC fabrication process. (a)
2. Given the N

network for a complex static CMOS logic gate, derive the P

network (or
vice versa) and the Boolean function. (e)
3. Given the Boolean function for a complex static CMOS l
ogic gate, derive the N and P
networks. (e)
4. Given the transistor

level diagram for a complex CMOS logic gate, show an efficient
Sticks Diagram to implement the gate. (e)
5. Given a layout and a set of capacitance parameters, compute node capacitances.
(e)
6. Given a layout and set of resistance parameters, compute interconnect resistances. (e)
7. Given a transistor

level diagram with specified input, capacitance and resistance values,
show an equivalent RC network. For a given input transition, compu
te the time at which
the output makes a corresponding transition. (e)
8. Show the DC transfer characteristic
s for a static CMOS inverter. (a
)
9.
Show the different conditions for a transistor to be in cutoff, linear and saturation
modes. (a)
10. Show th
e first order formulas for
computing the C
urrent I
ds
, which flows through the
transistor channel in linear and saturation modes. (a
,
m
)
11
. Show a logic

level diagram for a VLSI subsystem, such as an adder, ALU, shifter,
counter, or multiplier. (c
)
12
. S
how the organization of a RAM, provide transistor

level diagrams of static and
dynamic RAM cells, and give logic

level or transistor

level schematics for row and
column decoders. (c
)
13
. Illustrate the organization and timing of a PLA. (
a,
c)
14
. Compute
the relative sizes of nMOS and pMOS transistors needed to equalize worst
case rise and fall times. (e)
15
. Show the state diagram, state table, and required PLA programming for a simple
finite state machine. (e)
16. Compute gate sizes on a path to optim
ize
the path
delay using logic effort. (e
)
B. By the time of Exam No. 2 (after 26 lectures), students should be able to do the
following:
17
. Analyze the power consumption of a simple gate

level circuit, and itemize various
ways t
o reduce power dissipati
on. (
a,
e)
18
. Given a gate

level circuit diagram, generate a test vector to test for a stuck

at fault.
(e)
19
. Show how test vectors are applied to a fu
ll scan design. (e
)
20
. Explain how self

testing i
s done in a BIST environment. (a
)
21
. Compare and
contrast various design methodologies, such as custom design and cell
based
design. (a
)
22. Use a Hardware Description Language, such as Verilog
, for circuit design
.
(a,
c,
k)
23
. Illustrate the operation of a logic optimization procedure for a simple B
oolean
function. (
a,
e
)
24
. Use BDD to represent and optimize logic function. (a
,
e
)
25
. Perform partitioning using a constructive partitioning algorithm, such as the
Fiduccia

Mattheyses alg
orithm. (
a,
e
)
26
. Illustrate the operation of vari
ous shortest
path algorithms. (
a,
e
)
27
. Illustrate the operation of various net routing algorithms, such as the left

edge and
greedy algorithms for channel routing, the Hightower and Mikami

Tabuchi line
probe
algorithms, an
d the maze routing algorithm. (a
)
28
. Give
n a high

level circuit description, construct the corresponding sequencing graph,
schedule all operations using various scheduling algorithms, and perform resource
allocation
and binding
. (
a,
e
)
29
.
Show the basic steps involved for chip packaging. (a)
C
. By the end of the course, students should be able to do the following:
30
. Describe the procedures used in static and dynamic timing analysis tools. (a)
31
. Custom design various simple and complex logic gates, and interconnect cells to
form
a subsyste
m. (a, c, k)
32
. Custom design the datapath for a 4

bit microcontroller
(Am2901)
. (a, c, k)
33
. Use automatic synthesis and automatic placement and routing tools to implement the
control logic for a 4

bit microcontroller
(Am2901)
. Interconnect the datapa
th and control
logic. (c, k)
34. Specify test vectors, run the functional test, and analyze the results to
adequately
verify the functionality of the Am2901 design. (a, c, k)
35
. Explain how trends in technology impact circuit characteristics, such as de
lay and
power consumption. (j)
Updated Spring
2007
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