Computer Assignment #2
Digital VLSI Systems
,
©Mohammad Sharifkhani, Fall 2011.
Goals:

Getting familiar with
transistor level layout
tools

Transistor level modeling of basic gates
(CMOS, Pass

T, Dynamic logic)

Transistor level design of a simple digital
circuit
Due Date:
Aban
2
2
th
, 1390.
Instruction:
Part
1:
Desi
gn and characterization of basic
combinatorial and sequential
circuits
a.
Based on the observations in the first computer assignment, design, layout and
characterize the following gates based on the
unit sized inverter
using standard CMOS
topology
:
i.
NAND2, NOR2, NAND3, NOR3,
AND2, OR2
.
ii.
Perform the characterization based on linear relationship between the gate load
capacitance and the propagation delay.
b.
Design and implement a static DFF with reset with
minimum transistor counts based on
the topologies provided in the course.
i.
Characterize the DFF for setup time, hold time and average clock capacitance.
c.
Perform parts a and b for a simple dynamic circuit.
i.
What is the average delay reduction compared with
the circuit designed in part
a for a given load (FO4)?
ii.
What is the average power reduction compared with the circuit designed in part
a and b?
iii.
What is the minimum tolerable clock frequency?
Part 2: Design and characterization of
a binary signed
right
shifter
a.
Use the circuits you designed in the previous part to d
esign a shifter that provi
des the
following functionality:
a.
8 bit input and output
b.
Includes
a reset signal
c.
Synchronized loading
b.
Perform the simulation in
Cadence
environment using a practical te
stbench using
some
random numbers.
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