Application for IEEE Standards Education Grant
for
Student Application Papers Applying Industry Standards

Step 1: Application Information
1.1.
Date of
Application:
14
th
October 2012
1.2.
Project Title:
Design & Characterization of reusable IP Core for Error Correction using
Improved Hamming Code.
1.3.
Lead Student’s Name:
Arathy S
(Graduate Student)
VLSI Design Group
NIELIT
Calicut, Kerala, India

673601
arathysnair
89
@gmail.com
1.4.
Faculty Mentor
:
Nandakumar.R
VLSI Design Group
NIELIT
Calicut, Kerala, India

673601
nanda24x7@gmail.com
1.5.
Educational
Institution:
National Institute of Electronics & Information Technology
(NIELIT)
1.6.
Program/Course of Study
:
VLSI & Embedded System

Step 2: Project information
2.1
Project Title
Design
and characterization
of
Error Correction
IP Core
using Improved Hamming Code.
Scope of
Project
The error correction IP core
design described in this paper
employs improved hamming
code
error correction method
. This method can detect and correct single

bit errors and detect
double

bit errors.
In conventional hamming code method large number
of
overhead bits
are used
in the process of calculation of parity/redundancy bits. In improved hamming code
[1]
method
the number of overhead bits is greatly reduced
.
The parity bits are
appended at the end of data
bits
. This
eliminates the overhead of int
erspersing the redundancy bits at the sender end and their
removal at the receiver end. This work is believed to serve as a good error correction mechanism
for transmission of large size data bit

streams as long as there is likelihood of at the most single

bit error during transmission.
Goal of Project
The
goal o
f the project is to design an error correction IP core using improved hamming
code
.
Hamming code with additional parity bit can detect and correct single

bit errors and detect
double

bit errors. I
n comparison with conventional hamming code, improved hamming
code
[1]
employs less number of overhead bits in the process of calculation of redundancy bits.
Rationale for selecting the project
Whenever data is stored or transmitted, there is some chance that one or more bits will
“
flip
”
–
that
is, will change to an incorrect value. Such incorrect values are called
errors
; they
may be due to a
permanent fault (broken hardware) or a transient cond
ition
.
To counteract this
problem and ensure reliable operation, error correcting codes (
ECC
) are used.
Extra bits are sent
or stored alongside the data bits to provide redundant information. With enough
bits of carefully
chosen redundant information, we c
an detect or correct the most probable classes
of errors.
Hamming code error correction is most commonly used for computer memories. Hamming code
with extra parity/redundancy bit can detect and correct single

bit errors and detect double

bit
errors. Hammin
g code is normally used for transmission of data with small lengths. Scaling it for
larger data lengths results in a lot of overhead due to interspersing the redundancy bits and their
removal later. Improved hamming code method
[1]
is highly scalable witho
ut such overhead.
Therefore it is suitable for transmission of large size data bit

streams with much lower
overhead
bits per data bit ratio.
2.2
Plan
of the project
The
project is to design an error correcti
on IP Core using
improved hamming code
.
The
first st
age of the project includes literature survey
on
different error correction methods
,
error
correction by
conventional
hamming code
and error correction by improved hamming code
.
Next step is to
describe the design of error correction method
using improved
hamming code
in
Verilog HDL
. Next step is to calculate the overhead bits in the process of calculation of
redundancy bits in conventional hamming code method and improved hamming code
[1]
method
using Matlab. Next step is to
compare the results using Matl
ab plot.
The final stage of the project
is FPGA implementation
Project Flow
1.
To study error correction mechanism by conventional hamming code.
2.
To
study error correction mechanism by improved hamming code
[1]
.
3.
To design the improved hamming code error
correction scheme
using Verilog HDL
.
4.
To calculate overhead bits in both methods and plot result using Matlab.
5.
To synthesize
the design using Altera
®
Quartus

II.
6.
To
prototype
the design
in Altera
®
platform
FPGA
.
7.
To perform power analysis using Power
Play
Power
Analyzer
Tool
and to obtain hardware
test
result using Signal Tap
II
Logic Analyzer.
2.3
Technical standards
1.
Verilog
HDL (
IEEE Std 1364

2005
) : Verilog HDL
(
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10779
) is used to describe
the design of Error Correction IP core.
2.4
Target Date for Final Paper Submission
: 25
th
December 2012
Reference
[1]
Kumar, U.K.; Umashankar, B.S.; ,
"Improved Hamming Code for Error Detection and
Correction,"
Wireless Pervasive Computing, 2007. ISWPC '07. 2nd International Symposium
on
, vol., no., 5

7 Feb. 2007
doi: 10.1109/ISWPC.2007.342654
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