Chapter 7 Built-in Self Test

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Dec 1, 2013 (3 years and 9 months ago)

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1

Chapter 7 Built
-
in Self Test

7.1 Introduction

Very Large Scale Integration (VLSI) has had a dramatic impact on the growth of digital technology.
VLSI has not only reduced the size and the cost but also increased the complexity of the circuits. This has
bro
ught significant improvements in performance. These welcomed improvements have resulted in signif
i
cant
performance/cost advantages in VLSI
-
implemented systems. There are, however, potential problems which
may retard the effective use and growth of future V
LSI technology. Among these is the problem of circuit
testing, which becomes increasingly difficult as the scale of integration grows.

Because of the high device counts and limited input/output access that characterize VLSI circuits, co
n-
ventional testing
approaches are often ineffective and insufficient for VLSI circuits. Automatic test pattern
generation for sequential circuits is not feasible even for many LSI circuits. Thus, design for testability tec
h-
niques such as serial scan must be employed, as stat
ed in the previous chapter. But for VLSI circuits, such
techniques still involve large amounts of test pattern generation and simulation efforts, huge volumes of test
input/output data, and excessive testing times. Therefore, alternatives to test methodolo
gies which employ test
pattern generation and externally applied test patterns are essential to continue the growth of VLSI industry.

For any such alternative, the following goals are desirable: high and easily verifiable fault coverage,
minimum test patte
rn generation, minimum performance degradation, at
-
speed testing, short testing time, and
reasonable hardware overhead.
Built
-
In Self
-
Test

(BIST) provides a feasible solution to the above demands.
First, BIST significantly reduces off
-
chip communication to

overcome the bottleneck caused by the limited
input/output access. Further, it eliminates much of the test pattern generation and simulation process. Testing
time can be shorten by testing multiple units simultaneously through test scheduling. Hardware ov
erhead can
be minimized by careful design and through the sharing of test hardware.

7.1.1 The VLSI Testing Problem

VLSI circuits are characterized by high device counts, limited input/output (I/O) access, and sequential
behavior. These characteristics are

responsible for the difficulties in testing such circuits. The high device
count increases the complexity of test generation and fault simulation. The limited I/O access greatly d
e
crea
s-
es the controllability and observability of the internal circuitry. Th
e sequential behavior implies pe
r
forming
sequential test pattern generation. The automation of such sequential test pattern generation is a major u
n-
solved problem in the testing area.


High device count is the most prominent feature of VLSI. Typically,
a VLSI chip contains hundreds of
thousand devices. With deep submicron technologies, the device count is pushed well over one million mark.
This high device count has an immediate impact on test pattern generation and fault simulation. Even for the
much s
impler combinational circuit, it has been observed that the computer run time to do test generation and
fault simulation is approximately proportional to the number of logic gates to the power of three [Will82].
The high device count also has impacts on te
st pattern storage and on testing time. A reasonable assumption is
that both the number of test vectors and the width of a vector is linearly proportional to the circuit size. Hence,
testing time and test pattern storage are proportional to the circuit siz
e to the power of two.


2

S
S
I
1
9
7
0
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S
I
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0
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S
I
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8
5
V
L
S
I

1
9
9
0
V
L
S
I

2
0
0
0
1
0
1
0
0
1
,
0
0
0
1
0
0
,
0
0
0
1
0
,
0
0
0
,
0
0
0
G
a
t
e
C
o
u
n
t
S
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1
9
7
0
M
S
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1
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8
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5
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L
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I

1
9
9
0
V
L
S
I

2
0
0
0
1
0
4
0
2
0
0
1
0
,
0
0
0
P
i
n

C
o
u
n
t
S
S
I
1
9
7
0
M
S
I
1
9
8
0
L
S
I
1
9
8
5
V
L
S
I

1
9
9
0
V
L
S
I

2
0
0
0
1
5
2
5
5
0
0
1
0
,
0
0
0
G
a
t
e
/
P
i
n

R
a
t
i
o
2
0

Figure 7.1 Gate/Pin ratio in the development of IC technologies

Limited I/O access, although perhaps not as significant as high device count, still contributes to testing
problems. The consequence of limi
ted I/O access is low testability in terms of both controllability and o
b-
servability. The testability of a chip can be roughly estimated by its gate
-
to
-
pin ratio, i.e., the ratio between
the number of interface pins and the number of gates. Thus, productio
n of tests for VLSI circuits is likely to
be difficult due to poor testability. Figure 6.1 shows the device counts, pin counts, and gate
-
to
-
pin ratios in the
development of IC technologies. The higher the ratio is the lower the testability will be.

Built
-
i
n self
-
test (BIST) significantly reduces off
-
chip communication by accommodating test gener
a-
tion and response evaluation hardware on the chip. Therefore, the limited I/O access constraint is eased.
Well
-
organized BIST also partitions the circuit into piec
es of moderate size to reduce the complexity of test
generation and fault simulation. In fact, many built
-
in self
-
test approaches avoid either test pattern generation,
fault simulation, or both. It is also easier to schedule simultaneous testing of multipl
e blocks by using BIST
rather than off
-
chip testing, thus providing potential for reducing the testing time.

7.1.2 Built
-
in Self
-
Test Architecture

The basic BIST architecture is composed of three hardware modules in addition to the circuit under test
(CUT)
. The architecture is shown in Figure 2. The functions of these blocks are as follows. The

test pattern
generator
generates the test patterns for the CUT. The
response analyzer
compresses and analyzes the test
responses to determine correctness of the CUT.

The
BIST controller

is the central unit to control all the BIST
operations. In a BIST system hierarchy, there are BIST controllers at each level of the circuit hierarchy, such
as module, chip, board, and system levels. Each BIST controller is responsible
for the self test in that pa
r
tic
u-
lar level, the controls of BIST operations for the lower level BIST, and the report of the test results to the u
p-
per level. The design of a test generator is determined by the test strategy being deployed. The test strategy

being selected is determined by the fault coverage, test hardware overhead, and testing time. The commonly
seen test strategies include the fo
l
lowings.


3

T
e
s
t

G
e
n
e
r
a
t
o
r
C
i
r
c
u
i
t

U
n
d
e
r

T
e
s
t
(
C
U
T
)
R
e
s
p
o
n
s
e

A
n
a
l
y
z
e
r
B
I
S
T
C
o
n
t
r
o
l
l
e
r

Figure 7.2 BIST Architecture

Stored Patterns:
Stored
-
pattern approach store
s the pregenerated test patterns to achieve certain test
goals. It is often found in system level testing such as the power
-
on self test of a computer and m
i-
croprocessor functional testing using microprograms.

Exhaustive Testing:

Exhaustive testing applie
s all possible input combinations to the CUT. It guarantees
that all detectable faults that do not produce sequential behavior will be detected. The strategies is
often applied to complicated and well isolated small modules such as PLAs. [McClusky 1981]
[W
ang 1986].

Pseudorandom Testing:
Pseudorandom testing applies a certain length of test patterns with certain ra
n-
domness property. The sequence of test patterns are in a deterministic order. The fault coverage is
determined by the test length and the conten
ts of the patterns. [Savir 1984], [Williams 1985],
[Wagner 1987].

Weighted Pseudorandom Testing:
Weighted pseudorandom testing applied pseudorandom patterns
with certain 0s and 1s distribution to handle the random pattern resistant faults undetectable by t
he
pseudorandom testing. It can effectively shorten the test length. [Schnurmann 1975], [Chin 1984],
and [Wunderlich 1987].

Pseudorexhaustive Testing:

Pseudoexhaustive testing partitions the CUT into several smaller subci
r-
cuits and tests each of them exhau
stively. All detectable faults within the subcircuits can be d
e-
tected. However, such a method requires extra design effort to partition the circuits and deliver the
test patterns and test responses. [McCluskey 1981], [Chandra 1983], and [Udell 1986].

For t
he test pattern generator, the major consideration include the fault coverage, the test length, and the
hardware overhead. The hardware design for the generation of above patterns include read only memories
(ROM) for deterministic test patterns, linear fee
dback shift registers (LFSR) for exhaustive and random pa
t-
terns. In Section 3.2 we will discuss LFSR in detail because it is the most important module in BIST env
i-
ronment. In Section 3.3 we will discuss the use of LFSRs and other module for the generation
of the desire
test pa
t
terns.

The response analyzer, in most case, compresses a long test response sequence into a single word. Such a
word is called a signature or syndrome. Then, the signature/syndrome is compared with a prestored golden
signature/syndrom
e obtained from a fault
-
free circuit to determine the correctness of the CUT. Depending on
how the responses are compressed, the techniques are classified as follows.


4

Signature Analysis:

Signature analysis uses LFSRs to compress the responses into a single
-
word sign
a-
ture. This is the most popular form of response analysis because it is simple and robust. [Peterson
1972] and [Colomb 1982].

Ones Count:
Ones count counts the number of 1s in the test response sequence to determine the correc
t-
ness of the circuit
s. This is a very simply way of compression. It only requires a simple counter to
accomplish the goal. The order of the test patterns being applied can be permuted. [Barzilai 1981]
and [Hayes 1976].


Transition Count:
Transition count counts the number of
transitions in the test response sequence to d
e-
termine the correctness of the circuits. It is compatible in complexity with the ones count method.
However, the test sequence cannot be permuted. [Barzilai 1981] and [Hayes 1976].

Syndrome Count:
Syndrome cou
nt counts the probability of 1s in the test responses to determine the
correctness of the circuits. It is very similar to the ones count except that the patterns need not be
fixed. [Hayes 1976], [Reddy 1977], and [Savir 1985].

The selection of test respons
e analysis methods include the aliasing probability and hardware overhead.
The aliasing probability is the probability that faulty responses are compressed into a fault
-
free signatuer. In
Section 7.4, we will have the detail discussion on the response anal
ysis techniques. In addition to the LFSR in
Section 7.2, test pattern generators in Section 7.3, and response analyzers in Section 7.4, we will present
many BIST architectures in Section 7.5. Finally, we will offer several examples of BIST being employed i
n
real products in Section 7.6.


7.2 LFSR Fundamentals

LFSR is the most important and popular BIST hardware module. It has the following advantages. First, it
is theoretically sound because it is linear in GF(2) (Galois Field of modulo 2 polynomials) and a
ll the the
o-
rems in GF(2) is applicable to LFSR. Second, it has a very simple and regular structure which minimize the
hardware overhead and dsign effort. Third, it is able to generate random test patterns with very good rando
m-
ness property. Forth, it can a
lso be used to compress test responses with a very low aliasing probability. Fifth,
its shift property is easily integratable in a DFT scan environment hence the hardware overhead is minimum
when upgrading from a scan DFT design. In addition to LFSR, we wi
ll also discuss a different structure called
cellura automata (CA). CA has better randomness property than LFSR. It also has more varieties in the design
of test pattern generator and response compressor.

7.2.1
LFSR Structure


Two examples of LFSRs are shown in
Figure 7.3. Both versions use D type flip
-
flops and linear logic
elements (exclusive
-
or gates) to realize LFSRs. The basic differences in these two structures are as follows.
The
external type LFSR

puts XOR gates outside the shift path. It is also called
type 1 LFSR

by Abramovici,
Breuer, and Friedman [Abramovici et al. 1990]. The
internal type LFSRs
, also called
type 2 LFSR
, puts XOR
gates in between the flip
-
flops. These two types are equivalent in the sense that one
-
to
-
one correspondence
between these t
wo structure can be derived. The location of the XOR gates in Figure 7.3 is determined by a
polynomial in GF(2) called
characteristic polynomial
. The general form of a characteristic polynomial is

5

shown below.


g
x
g
x
g
x
g
x
n
n
n
n
(
)






1
1
0
0



(7
-
1)

The correspondence between the characteristic polynomial and the circuit structure of both types is shown
in Figure 7.4. The basic building blocks of LFSRs are D
-
type flip
-
flop, XOR gates, and connections. The
connections are
marked as circle with coefficient
g
i
. When
g
i

is 1, the circle passes the signal to the
XOR gates. Otherwise, the connection is off. For the characteristic polynomial of
x
x
4
3
1


, the LFSRs
are shown

in Figure 7.3.

(
b
)

I
n
t
e
r
n
a
l

T
y
p
e
(
a
)

E
x
t
e
r
n
a
l

T
y
p
e
D
0
D
1
D
2
D
3
D
0
D
1
D
3
D
2

Figure 7.3 Two Types of LFSRs

.
.
.
D
0
D
1
D
n
-
2
D
n
-
1
g
1
+
g
2
+
g
n
-
1
+
.
.
.
(
a
)

E
x
t
e
r
n
a
l

T
y
p
e

L
F
S
R
(
b
)

I
n
t
e
r
n
a
l

T
y
p
e

L
F
S
R
.
.
.
D
0
D
1
D
n
-
2
D
n
-
1
g
1
+
g
n
-
2
g
n
-
1
.
.
.
+
+

Figure 7.4 LFSR with Characteristic Polynomial
g
x
g
x
g
x
g
x
n
n
n
n
(
)






1
1
0
0



One of the most important properties of LFSRs is their recurrence relationship.

The recurrence relation
guarantees that the states of a LFSR are repeated in a certain order. The recurrence relation can be repr
e-
sented by the following equations.


G
x
g
x
a
x
a
x
g
x
i
i
i
i
i
n
(
)
(
)
(
)










1
1
1

(7
-
2)

Here, G(x)

is the pattern being generated.
a
i

is the initial state of the flip
-
flop
D
i
. If the initial state is
(00…01), (7
-
2) degenerate to
G
x
g
x
(
)
(
)

1
. An example of the recurrence relation is shown in Figure 7.5
.
Here, the initial state of the LFSR is (1000). The initial state repeats after 15 cycles. The same sequence will
repeat the next cycle and thereafter. If one examine the sequence carefully, one will notice that the period
of the recurrence is 15 or
2
1
4

. The recurrence cycle contains all possible combinations except all zeros
(0000). Here, we would like to look into the characteristic polynomial and the patterns it generates in

6

more detail.

D
3
D
2
D
1
D
0
+
g
x
x
x
(
)



4
3
1
a
n


1
1
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
D
3
D
2
D
1
D
0

Figure 7.5 Examp
le of a LFSR

There are some definitions and theories associated with the characteristic polynomial. The sequence
generated by an n
-
stage LFSR has a period of
2
1
n


is called a
maximum
-
length sequence

(M
-
sequence).
A M
-
sequence contains al
l possible combinations except all zeros. The characteristic polynomial associated
with the M
-
sequence is called a primitive polynomial. A primitive polynomial must satisfy the following
three criteria. First, it must be irreducible. A polynomial is irredu
cible if it can only be dived evenly by 1
and itself. Second, it has an odd number of terms, including the 1 term. Third, if the degree n is greater than
3, then
g(x)

must divide
x
k

1
, where k=
2
1
n

.


The patterns ge
nerated by a primitive polynomial satisfies the following randomness properties. First,
the number of 1s in a M
-
sequence differs from the number of 0s by one. Second, a M
-
sequence produces an
equal number of runs of 1s and 0s. In every M
-
sequence, one half

the runs have length 1, one forth have
length 2, one eighth have length 3, and so forth. Here, a run of 1s of length 3 is (111). For instance, there are
two runs of (111) in the serial patterns generated at D
3
, D
2
, D
1
, or D
0

locations. The run is not limi
ted to the
consecutive ones. It can be any combinations. For instance, you are able to find that there are two runs of
(101) and four runs of (01) in each bit positions.


In addition to these static randomness properties, there are also dynamic randomn
ess properties. The
autocorrelation of any output bit is very close to zero. The autocorrelation is referred to the correlation of
the patterns generated at the same bit position with a certain amount of time difference. Here, 0 is regarded
as 1 in calcula
ting the correlation. Moreover, the crosscorrelation of any two output bits is very close to
zero as well. With both static and dynamic randomness properties, a M
-
sequence is also called a pse
u-
dorandom sequence. The term
pseudo

is given to indicated the re
currence relation discussed earlier.

7.2.2 LFSR as a polynomial multiplier

A LFSR can be used as a polynomial multiplier. Figure 7.6 shows the circuit diagram of a LFSR being
used as a polynomial multiplier in GF(2). Initially, the initial state of D flip
-
flops are set to 0s. The presence
of the input bit
f
k
is multiplied by the characteristic polynomial g(x). The result
f
g
x
k
(
)
is added into the
register. When the clock comes, the LFSR is shifted one position to multiple
current result by
x
. At the m
o-
ment, the coefficient whose calculation has just completed is shifted to the output. Such a shift and add o
p-
erations repeats until all the input bits are processed. Figure 7.7 shows an example of the polynomial mult
i-

7

plication
done by a LFSR. As one can see, the process is the same as the long multiplication by hand.

+
g
1
+
g
n
-
2
+
g
n
-
1
+
g
n
g
0
.
.
.
i
n
p
u
t
f
(
x
)
o
u
t
p
u
t
h
(
x
)
g
x
g
x
g
x
g
x
I
n
p
u
t
f
x
O
u
t
p
u
t
h
x
h
x
g
x
f
x
n
n
n
n
(
)
(
)
(
)
(
)
(
)
(
)









1
1
0
0


Figure 7.6 Structure of LFSR as a Multiplier

7.2.2 LFSR as a polynomial multiplier

A LFSR can be used as a polynomial multiplier. Figure

7.6 shows the circuit diagram of a LFSR being
used as a polynomial multiplier in GF(2). Initially, the initial state of D flip
-
flops are set to 0s. The presence
of the input bit
f
k
is multiplied by the characteristic polynomial g(x). T
he result
f
g
x
k
(
)
is added into the
register. When the clock comes, the LFSR is shifted one position to the left to multiple current result by
x
.
At the moment, the coefficient whose calculation has just completed is shifted to the output. S
uch a shift and
add operations repeats until all the input bits are processed. Figure 7.7 shows an example of the pol
y
nomial
multiplication done by a LFSR. As one can see, the process is the same as the long multiplication by hand.

D
0
D
1
D
2
+
D
3
+
g
x
x
x
(
)



4
3
1
1
1
0
1
1
3
x
x


O
u
t
p
u
t

s
t
r
e
a
m



D
3


D
2


D
1


D
0


I
n
p
u
t

s
t
r
e
a
m












1



0

0

0

0



1

1

0

1










1

0



1

0

0

1



1

0

1








1

0

1



1

0

1

1



0

1






1

0

1

1



0

1

1

0



1




1

0

1

1





0

1

0

1




x
7


x
5
x
4






x
2


1




x
x
x
x
x
x
x
x
4
3
3
7
5
4
2
1
1
1










Figure 7.7 Example of a LFSR as a multiplier



8

g
x
g
x
g
x
g
x
M
x
R
x
Q x M x P x g x R x
n
n
n
n
(
)
(
)
(
)
( ) ( ) ( ) ( ) ( )











1
1
0
0

I
n
p
u
t
R
e
m
a
i
n
d
e
r
Output
D
0
+
g
1
+
g
n
-
2
+
g
n
-
1
g
n
g
0
.
.
.
i
n
p
u
t
o
u
t
p
u
t
+
D
1
D
n
-
2
D
n
-
1

Figure 7.8 Structure of LFSR as a divider

Input
110110110
Output
10011
M(x)
Q(x)
g
x
x
x
(
)



4
3
1
D
0
D
1
D
2
+
D
3
+

Q(x)
D
3

D
2

D
1

D
0

M(x)
0 0 0 0 1 1 0 1 1 0 1 1 0
1 1 1 0 1 1 0 1 1 0
1 0 0 0 1 0 0 1 1 0
1 0 0 0 1 0 0 1 1 0
1 0 0 1 1 0 0 1 1 0
1 0 0 1 1 1 0 1 0 0
1 1 0 1
after 4 shifts
Q(x)
R(x)




x
x
x
x
x
x
x
x
x
x
x
x
8
7
5
4
2
4
3
4
3
3
2
1
1
1













/

Figure 7.9 Example of a LFSR as a divider

7.2.3 LFSR as a polynomial Divider


A LFSR can be used as a polynomial divider. Figure 7
.8 shows the circuit diagram of a LFSR being
used as a polynomial divider in GF(2). The presence of the input polynomial
M(x)

is divided by the cha
r
a
c-
teristic polynomial g(x). Initially, the initial state of D flip
-
flops are set to 0s. After n shifts, the
quotient bit
q
i

appear at the output. The quotient
q
i
is multiplied by
g(x)

and subtracted from the register. Note that ,
the subtraction in GF(2) is equivalent to the add operation. When the clock comes, the LFSR i
s shifted one
position to produce a quotient bit and lower the order by one. Such a shift and subtract operations r
e
peats
until all the input bits are processed. Figure 7.9 shows an example of the polynomial division done by a
LFSR. As one can see, the pro
cess is the same as the long division by hand.

g
x
g
x
g
x
g
x
M
x
R
x
Q x M x P x g x R x
n
n
n
n
(
)
(
)
(
)
( ) ( ) ( ) ( ) ( )











1
1
0
0

I
n
p
u
t
R
e
m
a
i
n
d
e
r
Output
D
0
+
g
1
+
g
n
-
2
+
g
n
-
1
g
n
g
0
.
.
.
i
n
p
u
t
o
u
t
p
u
t
+
D
1
D
n
-
2
D
n
-
1

Figure 7.8 Structure of LFSR as a divider


9

I
n
p
u
t
1
1
0
1
1
0
1
1
0
O
u
t
p
u
t
1
0
0
1
1
M
(
x
)
Q
(
x
)
g
x
x
x
(
)



4
3
1
D
0
D
1
D
2
+
D
3
+




Q
(
x
)





D
3


D
2


D
1


D
0










M
(
x
)












0

0

0

0



1

1

0

1

1

0

1

1

0








1



1

1

0

1



1

0

1

1

0






1

0



0

0

1

0



0

1

1

0




1

0

0



0

1

0

0



1

1

0


1

0

0

1



1

0

0

1



1

0
1

0

0

1

1



1

0

1

0



0












1

1

0

1
a
f
t
e
r

4

s
h
i
f
t
s
Q
(
x
)
R
(
x
)




x
x
x
x
x
x
x
x
x
x
x
x
8
7
5
4
2
4
3
4
3
3
2
1
1
1












/

Figure 7.9 Example of a LFSR as a divider

7.2.3 Cellura Automata

A
cellular automaton

(CA) is a 1
-
dimensional
array of cells. Each cell consists of a storage element
and a nest state logic. The next state is determined by the current values of the storage element and the left
and right neighboring cells. The function of the logic blocks for all the cells can be id
entical, but it is not
necessary. The two commonly used structures are shown in Figure 7.10. The cell function naming is pr
o-
posed by Wolfram in [Wolf83]. The name is determined by the next state function
F
ca
. The naming mech
a-
nism is show
n in Figure 7.11. Here,
Ci

is the state of the current CA cell.
C
i+1

and
C
i
-
1

are the states

D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
0
0
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
D
Q
Fca
(a) CA with null boundary conditions
(b) CA with null cyclic boundary conditions

Figure 7.10 The structure of cellura automata

of its neighboring cells. The next state of cell Ci is determined by (Ci
-
1 Ci Ci+1). The next state function
can b
e represented by the entries in the Karnauph map (K
-
Map) denoted as A
7

throughA
0
. The name given
to the cell is defined as follows.


A
i
i
i



2
0
7

(7
-
3)


10

An example is also sho
wn in the Figure 7.11.

State
A
0
A A
2
A
3
A
4
A
5
A
6
A
7

C
i+1
0 0 0 0 1 1 1 1
C
i
0 0 1 1 0 0 1 1
C
i-1
0 1 0 1 0 1 0 1

Next State KMap F
CA
A
0
A
2
A
1
A
3
A
5
A
4
A
6
A
7
Name
A
i
i
i



0
7
2
Example:
F
C
C
CA
i
i



1
Name = 128+16+4+2
= 150
0
1
1
0
0
1
0
0
(defined by Wolfram)

Figure 7.11 Example of Cellura Automata Cells


7.3 BIST Test Pattern Generation

The design of a test generator is determined by the test strategy being deployed. In this section, we would
like to discuss the test strategies and tes
t hardware structure. The strategies are compared in terms of fault
coverage, test hardware overhead, testing time, and the design efforts required to convert a design into a BIST
design.

7.3.1
Stored Patterns


Stored
-
pattern approach stores the pregenerated tes
t patterns to achieve certain test goals. It is often
found in system level testing such as the power
-
on self test of a computer and microprocessor testing using
microprogram. Successful applications of such a technique can be found in [Kuban 1984]. The te
st procedure
is as follows. We pergenerate the test pattern by an ATPG and store the pattern on chip or board. When BIST
is activated, we apply them to the CUT and compare the responses with the corresponding stored responses.
Because of the stored data si
ze is limited, this method is attractive only in limited situation. This include the
testing of regular circuits and the handle of hard
-
to
-
detect faults. For regular circuits like PLAs, only a very
small amount of test patterns are required to achieve a ve
ry high fault coverage if certain properties hold, such
as C
-
Testable. For stored pattern approach, read only memories (ROM) are used to store test patterns and test
responses. A counter is also required to sequence the memory in order.

7.3.2 Exhaustive Te
sting

Exhaustive testing applies all possible input combinations to the CUT. It guarantees that all detectable
faults that do not produce sequential behavior will be detected. Note that the faults that produce sequential
property may not be detected becaus
e the test sequence may not contain the test sequence for that particular
faults. Please refer to
Sequential Test Generation

for detail on sequential test generation. The test length is
exponentially proportional to the number of input pins (
2
n
). Since all possible inputs combinations are a
p-
plied, it is also regarded as the
complete function testing
. [McClusky 1981] [Wang 1986].

The hardware structure for exhaustive testing is very simple, as shown in Figure 7.12. Here, the order of

11

LFS
R must be the same as the number of inputs of the CUT. The test cycle include all possible input comb
i-
nations. Note that, a LFSR is unable to generate the pattern with all zeros. If the pattern is desired, one can
add some logic gates to the LFSR to make i
t cycle through the all
-
zero state. If so, it is no longer linear. It is
called nonlinear feedback shift register.

L
F
S
R
C
U
T
S
A

Figure 7.12 Exhaustive test hardware structure.

7.3.3
Pseudorexhaustive Testing


Pseudexhaustive testing partitions the

CUT into several smaller subcircuits and tests each of them exhau
s
t-
ively. All detectable faults within the subcircuits can be detected. The main goal of pseudoexhaustive test is to
obtain the same fault coverage as the exhaustive testing and, at the same
time, minimize the testing time.
Since close to 100% fault coverage is guaranteed, there is no need for fault simulation for exhaustive testing
and pseudoexhaustive testing. However, such a method requires extra design effort to partition the circuits
int
o pseudoexhaustive testable subcircuits. Moreover, the delivery of test patterns and test responses is also a
major consideration. The added hardware may also increase the overhead and decrease the perfo
r-
m
ance.[McCluskey 1981], [Chandra 1983], and [Udell 1
986].


Circuit partitioning for pseudoexhaustive testing can be done by
cone segmentation

as shown in Figure
7.13 Here, a cone is defined as the fanins of an output pin. To test the circuit in the cone exhaustively, one
must applied exhaustive patterns

to the fanins. Note that, these input might not be adjacent. If the size of the
largest cone in K, the patterns must have the property to guarantee that the patterns applied to any K inputs
must contains all possible combinations.

C
o
n
e
E
x
h
a
u
s
t
i
v
e

T
e
s
t

W
i
n
d
o
w

Figure 7.13 Cone Segmentation for pseudoexhaustive testing

To generate pseudoexhaustive test for the circuit in Figure 7.13, we can use a LFSR and a shift register
as shown in Figure 7.14 [Barzilai 1983]. The length of LFSR is usually greater than the
size of the largest
cone. Usually, at least two seeds are required. The number of test patterns generated is near minimal when the

12

size of the cone is much smaller than the total number of inputs. Such a structure has the minimal hardware
overhead. It is a
lso compatible with the DFT structure. If LFSR has the shift mode. The seeds can be sifted in
through scan chain. Moreover, the test responses of other module can be shifted in for compression. A simple
way to determine the length of the LFSR is by examini
ng span of the cones. The length of the LFSR is equal
to the largest span, assume. As a result, all the cones with span less than K will have exhaustive patterns if
2
K
patterns are applied.

Cone
LFSR
Shift Register

Figure 7.14 LFSR+SR for pseudoexhaustive tes
ting

Another approach for pseudoexhaustive test is to partition the circuit via the use of multiplexer as shown
in Figure 7.15. In normal mode, the subcircuit under test accepts the normal input data. While in the BIST
mode, the pattern generated by the LF
SR is delivered to the subcircuit via the multiplexer. The responses are
compressed by a signature analyzer. In the next section, we will have detail discuss on signature analyzers.
With such a design, the test length is minimized. The drawback is the hard
ware overhead incurred by the mu
l-
tiplexers and the routing area for the wire to deliver test patterns.

S
u
b
c
i
r
c
u
i
t
u
n
d
e
r

t
e
s
t
M
U
X
L
F
S
R
S
A
C
U
T
n
o
r
m
a
l

i
n
p
u
t
s

Figure 7.15 Pseudoexhaustive via multiplexer partitioning.

7.3.4 Pseudorandom Testing


Pseudorandom testing applies a cert
ain amount of random test patterns. The test patterns being applied
satisfy the randomness properties. The sequence being applied is in a deterministic order. The fault coverage
is determined by the test length and the contents of the patterns. For random
patterns, the fault coverage v.s.
test length has the typical exponential curve shown in Figure 7.16. As one know, the longer the test length is,

13

the higher the fault coverage will be. Theoretically, it takes infinite time to reach 100% fault coverage. A
m
ore precise analysis has been done by Savir and Bardell in [Savir, Bardell 1994]. There, the test length is
dete
r
mined by the following equations.


N
e
k
p
N
e
k
e
p
kD
U
t
kD
L
t
t

























ln(
/
)
ln(
)
ln(
/
)
ln(
./2
)
ln(
)
1
1
1

(7
-
4)

N
kD
U

and
N
kD
L
are upper and lower bounds of the test length.
e
t

is the escape probability threshold. It
corresponds to the confidence level is at least
(
)
1

e
t
.
p

is the detection probability of all faults.
k
is the
number of hard to detect faults. For example, for
p

of
10
5

,
e
t

of 0.001, and k of 10, the test length is in
between (920980, 921030). If k is 50, the test length becomes in between (1081923, 1091973). Other than
tes
t length, there are
random pattern resistant faults

that is difficult to test by a random pattern. For example,
the stuck
-
at
-
0 fault of the adder
-
tree shown in Figure 7.17 quires the pattern (111…1) for the fault detection.
Therefore, it is not likely to b
e detected by random patterns. With random pattern resistant faults, we need
some modification to improve the detection probability. The test pattern generation for pseudorandom testing
is the simplest. Either circuits in Figure 7.12 and 7.14 is able to ge
nerate the desired patterns. [Savir 1984],
[Williams 1985], [Wagner 1987].

F
a
u
l
t

C
o
v
e
r
a
g
e
T
e
s
t

L
e
n
g
t
h
1

Figure 7.16 Fault coverage v.s. test length for pseudorandom testing.

Random Pattern
Resistant Fault

Figure 7.17 Example of random pattern resistant faults

7.3.5 Weighted Pseudoran
dom Testing


Weighted pseudorandom testing applied pseudorandom patterns with certain 0s and 1s distribution to
deal with the random pattern resistant faults. It is a hybrid technique between pseudorandom testing and

14

store
-
pattern approach. In weighted
pseudorandom testing, the weight must be selected such that the test pa
t-
terns for hard
-
to
-
detect faults are more likely to occur. On can use software to determine a single or multiple
weights based on the probability analysis of hard
-
to
-
detect faults. For
instance, if the weight of the seudora
n-
dom pattern for the s
-
a
-
0 fault in Figure 7.13 is chosen as 0.9, the desired pattern of (111…1) is more likely to
happen [Schnurmann 1975], [Chin 1984], and [Wunderlich 1987].

The test pattern generator for weighted p
seudorandom testing can be accomplished in two ways. First, it
can be produced by a LFSR and some logic gates as shown in Figure 7.18(a). As we know, LFSR generates
pattern with equal probability of 1s and 0s. If a 3
-
input AND gate is used, the probability

of 1s becomes 0.125.
If a 2
-
input Or gate is used, the probability becomes 0.75. Second, one can use cellura automata to produce
patterns of desired weights as shown in Figure 7.18(b). For cellura automata, the selection and arrangement of
the next state
function, Fca, will produce patterns of different weights.

LFSR
1/8
3/4
1/2
7/8
1/2
0.8 0.6 0.8 0.4 0.5 0.3 0.3
0
D
Q
123
D
Q
193
D
Q
61
D
Q
114
D
Q
228
D
Q
92
D
Q
25
0
(a)
(b)

Figure 7.18 The generation of weighted pseudorandom patterns.

7.3.6 Test Strategies Comparison


As mentioned earlier, the considerations for deploying a BIST methodology are fault coverage, h
ar
d
ware
overhead, test time overhead, and design effort. These four considerations have very complicated relationship.
For instance, exhaustive test has the highest fault coverage however the test time can be very long. Pseudoe
x-
haustive test has good compr
omise between test time and test hardware overhead. However, the design effort
can be significant. Table 7.1 lists the characteristics of the test strategies mentioned earlier. In terms of fault
coverage, exhaustive test and pseudoexhaustive test has the h
ighest coverage. In terms of hardware overhead,
the pseudorandom testing is the lowest. For the test time, stored pattern approach has the shortest test time.
While pseudoexhaustive test requires a signification amount of design effort.

Table 7.1 Compariso
n of different test strategies.

T
e
s
t

M
e
t
h
o
d
S
t
o
r
e
d

P
a
t
t
e
r
n
E
x
h
a
u
s
t
i
v
e
P
s
e
u
d
o
e
x
h
a
u
s
t
i
v
e
P
s
e
u
d
o
r
a
n
d
o
m
W
e
i
g
h
t

P
s
e
u
d
o
r
a
n
d
o
m
C
o
v
e
r
a
g
e
H
i
g
h
H
i
g
h
H
i
g
h
L
o
w
M
e
d
i
u
m
H
a
r
d
w
a
r
e
H
i
g
h
L
o
w
H
i
g
h
L
o
w
M
e
d
i
u
m
T
e
s
t

T
i
m
e
S
h
o
r
t
L
o
n
g
M
e
d
i
u
m
L
o
n
g
L
o
n
g
D
e
s
i
g
n

E
f
f
o
r
t
L
a
r
g
e
S
m
a
l
l
L
a
r
g
e
S
m
a
l
l
M
e
d
i
u
m

7.4
BIST Response Compression and Analysis


15


The response analyzer compresses a very long test responses into a single word. Such a word is called
a signature. The signature is then compared with th
e prestored golden signature obtained from the fault
-
free
responses using the same compression mechanism. If the signature is the same as the golden copy, the CUT
is regarded fault
-
free. Otherwise, it is faulty. In this section, we will study the following

response analysis
methods, ones count, transition count, syndrome count, and signature analysis. As mentioned earlier, there
is a store
-
pattern approach which stores test patterns and responses in advance. The response analysis is
done by one
-
to
-
one compa
rison of the prestored fault
-
free responses. Since the method is very straightfo
r-
ward, we will not discuss it further.


Compression is like a function which map a large input space (the response) into a small output space
(signature). It is an n
-
to
-
1
mapping. Therefore, a faulty response may have the same signature as the
fault
-
free one. Such a situation is referred as the aliasing. The aliasing probability is the possibility that a
faulty response is treated as fault
-
free. It is defined as follows.



P a l i a s
Nu mb e r
of
faulty
responses
with
fault
free
syndrome
Number
of
faulty
responses

_
_
_
_
_
_
_
_
_
_

(7
-
5)

The aliasing probability is the major considerations in response analysis. Due to the n
-
to
-
1 mapping pro
p-
erty of the compression, it is unlikely to do diagnosis after compression. Therefore, the diagnosis re
sol
u-
a
tion is very poor after compression. In addition to the aliasing probability, hardware overhead and har
d-
ware compatibility are also important issues. Here, hardware compatibility is referred to how well the BIST
hardware can be incorporated in the CUT

or DFT.

7.4.1 Ones Count


Ones count counts the number of ones in the output sequence. Hence, the signature is the number of
ones. It is a intuitive method to compress a long output sequence into a single word. Figure 7.19 shows test
structure of one
s count for a single output CUT. The pattern generator can be any one of the technique in
Section 7.3. Figure 7.19 shows the structure for a single
-
output CUT. For multiple output ones, one can use
a counter for each output or do one output at a time with
the same input sequence. The aliasing probability
is derived as follows. Let m be the test length, r the number of ones. The aliasing probability is shown as
follows.




P
m
r
m
oc
m










1
2
1
0
5

.

(7
-
6
)

Here, the denumerator is the total number of faulty output sequences. Note that
2
m

is total number of
output sequences and only one of them is fault
-
free. The numerator is the total number of sequences that has
r ones
m
r






, the same as the fault
-
free sequence. From the above equation, we know that, when r equals one
half of m, the aliasing probability is the largest. When

r=0
or
r=m
, the aliasing probability is 0. From the
compression method, we know that, the input
test sequence can be permuted without changing the count.


16

T
e
s
t
P
a
t
t
e
r
n
C
U
T
C
o
u
n
t
e
r
C
l
o
c
k

Figure 7.19 Ones count compression circuit structure


7.4.2 Transition Count


Transition count compression is very similar to ones count compression. Instead counting

the number
of ones, it counts the number of transitions, zero to one and/or one to zero. Figure 7.20 shows the circuit
structure for the transition count. The aliasing probability of the transition count compression is shown as
follows.





P
m
r
m
tc
m












2
1
1
2
1
0
5

.

(7
-
7)

Similarly, the denumerator is the total number of output sequence when the test length is m. The numerator
is the number faulty sequences that has r transitions. Note that, for the test leng
th of m, there are
m
-
1transitions. Hence,
m
r







1

is the number of sequences that has r transitions. Since the first output can
be either one or zero, therefore, the total number must be multiplied by 2. Again, only one of them is
fault
-
fre
e.


Same as the ones count,
r=m/2

has the highest aliasing probability. However, when r=0 or r=m
-
1 the
aliasing probability is not zero It is
1
2
1
/
(
)
m


which is also very close to zero. Different from ones count,
the input sequence cannot
be permuted. If permuted, the number of transitions will be changed as well. On
the other hand, one can reorder the test sequence to maximize or minimize the transitions, hence, minimize
the aliasing probability. Note that, if all the test patterns with ou
tput 0s are applied before those with output
1, the number of transition is only 1. As a result, the aliasing probability is almost zero and the hardware
overhead is also minimized. Here, only one
-
bit counter is required.

T
e
s
t
P
a
t
t
e
r
n
C
U
T
C
o
u
n
t
e
r
C
l
o
c
k
D
F
F

Figur
e 7.20 Transition count compression circuit structure


17

7.4.3 Syndrome Testing


Syndrome is defined as the probability of ones of the output sequence. The syndrome is
1/8

for a
3
-
input AND gate and
7/8

for a 3
-
input OR gate if the inputs has equal proba
bility of ones and zeros. Figure
7.21 shows a BIST circuit structure for the syndrome count. It is very similar to ones count and transition
count. The differences is that the final count is divided by the number of patterns being applied. The most
disting
uished feature of syndrome testing is that the syndrome is independent of the implementation. It is
solely determined by its function of the circuit.

random
test
pattern
CUT
Syndrome counter
Counter
/
Clock
Syndrome

Figure 7.21 Syndrome testing circuit structure


The originally design of syndrome test applies exhau
stive patterns. Hence, the syndrome is
S
K
n

/
2
, where n is the number of inputs and K is the number of minterms. A circuit is syndrome test
a-
ble if all single stuck
-
at faults are syndrome detectable. The interesting part of syndrome testing
is that any
function can be designed as being syndrome testable. There are many researches on syndrome testing,
please refer to [Savir 1980] and [Barzilai 1981] for further detail.

7.4.4 Signature Analysis


Signature analysis is a compression technique

based on the LFSR discussed in the previous section.
The circuit structure for the signature analysis is shown in Figure 7.22. Mathematically, the output sequence
(polynomial) is divided by the characteristic polynomial. The remainder of the division is c
alled the sign
a-
ture. The example shown in Figure 7.9 can also be regarded as an example of signature analysis. The input
sequence (110110110) is compressed into a signature of (1101), the remainder. For an output sequence of
length m, there are a total of

2
1
m


faulty sequence. Suppose that we represent the input sequence
P(x)

as


P(x)=Q(X)G(x)+R(x)

(7
-
8)

G(x)

is the characteristic polynomial;
Q(x)

is the quotient; and
R(x)

is the

remainder or signature. For those
aliasing faulty sequence, the remainder R(x) will be the same as the fault
-
free one. Since,
P(x)

is of order m
and
G(x)

is of order
n
, hence
Q(x)

has an order of
m
-
n
. Hence, there are
2
m
n


possible
Q(x)

or
P(x)
. One
of them is fault
-
free. Therefore, the aliasing probability is shown as follows.


P s a
m
n
m
n






2
1
2
1
2

(7
-
9)


18

T
e
s
t
P
a
t
t
e
r
n
C
U
T
L
F
S
R

Figure 7.22 Signature analysis circuit struc
ture

D
3
+
D
2
+
D
1
+
D
0
+
D
3
+
D
2
+
D
1
+
D
0
+
+

Figure 7.23 MISR
-

Multiple
-
input signature register

Different from previous methods, the aliasing probability of signature analysis is independent of the
test responses. The aliasing probability can be reduced by increase
the length of LFSR. According to the
characteristics of polynomial field, signature analysis by LFSR has the following properties. First, An LFSR
with two or more nonzero terms detects any single fault. Second, a LFSR with primitive characteristic po
l-
ynomi
al detects any double faults separated by less than
2
1
n


positions. Third, a LFSR with
g
0
1


detects all burst error of length less than
n
. Figure 7.22 shows the hardware structure for a single
-
output
LFSR. For multiple

output circuits, one need not use multiple LFSRs or compress the responses of an ou
t-
put one at a time. Instead, there is a
multiple
-
input signature register

or MISR. Figure 7.23 shows the ci
r-
cuit structure of two MISRs based on the LFSR in Figure 7.3. The

multiple input bits are from the top of the
MISRs. MISR share the same properties as LFSR for single
-
input signature analysis.

7.4.5 Space Compression


So far, we have presented many techniques to compress a long test sequence into a single
-
word sign
a-
t
ure for verification. This can be regarded as the compression in time domain. Here, we would like to di
s-
cuss the space compression. Space compression is a technique to handle circuits with a lot of outputs. With
a lot of outputs, take signature analysis us
ing MISR as an example, the length of the MISR will be very long.
As a result, the hardware overhead can be excessive.

One can use XOR gates to combine two or more output pins into a single output before the time co
m-
pression. To minimize the aliasing prob
ability, error control coding techniques can be used. Figure 7.24
shows the space compression using a 16
-
bit SEC
-
DEC (single error correction and double error detection)
code. Here, 16 outputs are compressed into only 5 outputs. In conjunction with time co
mpression, the a
r-
chitecture is shown in Figure 7.25. Here, TC (time compression) can be though of as a LFSR or MISR.


19

1
2
3
4
5
6
7
8
+
+
+
+
+
+
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
+
+
+
+
+
+
+
+
+
+
+
+
+
+
P
1
P
2
P
3
P
4
P
5
+
+
+
+
+
+

Figure 7.24 Space compression using 16 SEC
-
DEC code

CUT
TC
SC

Figure 7.25 Space and time compression architecture.


7.5
BI
ST Architecture


After describing the BIST fundamentals, in this section, se will focus on the BIST architecture. Since,
LFSR and MISR are compatible with scan DFT and are overwhelming more popular than any other BIST
modules, we will concentrate on th
e techniques based on LFSR, MISR, and scan registers. Most BIST te
n-
iques involve a fundamental trade off between testing time and test hardware overhead. In [Argrawal 1993],
BIST techniques are classified into two categories: test
-
per
-
clock and test
-
per
-
sc
an.
Test
-
per
-
clock

BIST
applies test vectors and captures test responses onces every clock cycle.
Test
-
per
-
scan

BIST use scan chains
to delivery test vectors and test responses, therefore, a complete test cycle has the same period as a complete
scan cycle.

In the following subsections, we will discuss the sequential and combination BIST techniques
in the categories of test
-
per
-
clock and test
-
per
-
scan.

7.5.1 Combinational Test
-
Per
-
Clock BIST

Basic Structure


Figure 7.12 shows a basic structures of test
-
per
-
clock BIST. For every test clock, LFSR generates a
test vector and SA (MISR) compresses a response vector. Such a structure is the most versatile. By this
we mean it can be used for exhaustive test, pseudoexhaustive test, pseudorandom testing, and we
ight pse
u-
dorandom testing. For the last one, the structure of the LFSR must be replaced by the hardware structure
shown in Section 7.3.5. For this approach, the length of the LFSR and MISR must be the same as the
number of the inputs and outputs of the CU
T. Hence, the hardware overhead can be execessive. The tec
h-
niques use such a basic approaches include centralized and separate board
-
level (CSBL) BIST in [Benowitz
1975] and built
-
in evaluation and self
-
test (BEST) in [Resnick 1983]. The architecture of bo
th methods are
shown in Figure 7.26 and Figure 7.27 respectively. Note that both CSBL BIST and BEST are proposed for
combinational as well as sequential circuits.


20

C
U
T
(
C

o
r

S
)
M
U
X
M
U
X
S
I
S
R
C
o
u
n
t
e
r
L
F
S
R
n
k
1
m
n
m
1
P
I
s
P
O
s
k
m

l
o
g
2

Figure 7.26 CSBL BIST architecture

L
F
S
R
C
U
T
(
C

o
r

S
)
M
I
S
R
P
I
P
O

F
igure 7.27 BEST BIST architecture

CBIST


Concurrent BIST (CBIST) shown in Figure 7.28 is another example of test
-
per
-
clock approach
[Saluja 1988]. For the concurrent part, the comparator monitor the normal operation data. If it is the same as
the patte
rn in the LFSR, the test clock is ticked. The response is fed to the MISR for the compression and
LFSR advances one clock cycle. If there is no match for a long time, the LFSR generate test clock is ticked
once automatically to advance one test cycle. At t
he same time, the system clock is hold for one cycle.

C
o
m
p
a
r
a
t
o
r
L
F
S
R
M
U
X
N

/

T
N

/

T
N
o
r
m
a
l

i
n
p
u
t
s
C
U
T
(
C
)
M
I
S
R
N
o
r
m
a
l

o
u
t
p
u
t
s
E
N
C
B
I
S
T
C
i
r
c
u
i
t
r
y

Figure 7.28 CBIST architecture

LFSR+SR


Figure 7.29 shows the architecture which uses LFSR and scan register. Every time the LFSR shifts out
one bit to the scan register,

a test pattern is applied and a test response is compressed. With such a structure,
we are able to minimize the hardware overhead in the test pattern generator. The response co
m
pressor r
e-
main the same. Combining the scan register with LFSR, the patterns b
eing generated have the same property
as the LFSR being used. The test strategies that can be deployed using such a structure i
n
clude pseudoe
x-
haustive (see Figure 7.14) and pseudorandom. Centralized and embedded BIST (CEBS) is an example of
this approach.


21

Circuit Under Test
Shift register
LFSR
SA

Figure 7.29 LFSR+SR structure for test
-
per
-
clock approach.

Built
-
in Logic Block Observation


Built
-
in logic block observation is a well know approach for pipelined architecture. The circuit di
a-
gram of a BILBO module and the architecture using BILBOs
are shown in Figure 7.30. The BILBO has two
control signals (B1 and B2) to configurate a BILBO block into a shift register, reset, MISR, and parallel
load (normal). The BIST architecture using BILBO is shown at the right of Figure 7.30. For the test of C1,

BILBO1 and BILBO2 are configured as MISR. If one looks at BILBO1, C1, and BILBO2 only, they are
the same configuration as the one shown in Figure 7.12. The initial state of the BILBOs can be reset by a
co
m
mand of (01). The signature in BILBO2 can be shift
ed out by setting all the BILBOs into shift register
mode by (00) command. With such a BILBO structure, multiple modules can be tested simultaneously
through the careful scheduling of test resources. [Koenemann 1979]

0
1
M
U
X
Z
1
Q
D
Q
Q
1
Z
2
D
Q
Q
Q
2
.
.
.
.
.
.
.
.
.
Q
D
Q
Q
n
-
1
Z
n
D
Q
Q
Q
n
S
0
.
.
.
S
i
B
2
B
1
C
1
B
I
L
B
O
1
B
I
L
B
O
2
C
2
B
I
L
B
O
3
C
3
B
1

B
2
B
I
L
B
O
0


0
s
h
i
f
t

r
e
g
i
s
t
e
r
0


1
r
e
s
e
t
1


0
M
I
S
R

(
i
n
p
u
t


Þ
c
o
n
s
t
a
n
t


Þ
L
F
S
R
)
1


1
p
a
r
a
l
l
e
l

l
o
a
d

(
n
o
r
m
a
l

o
p
e
r
a
t
i
o
n
)

Figure 7.30

BILBO circuit diagram and architecture

7.5.2
Test
-
Per
-
Scan BIST

Basic Structure

Test
-
per
-
scan approach aims at reducing the hardware overhead as much as possible. Instead of using LFSR
and MISR for every input/output pins, this approach combine LFSR/MISR with
shift register to minimize
the hardware overhead. Figure 7.31 shows the basic circuit structure of a test
-
per
-
scan BIST. In BIST mode,
LFSR generates test vectors and shifted to the inputs of the CUT via scan register. At the same time, the

22

response are sc
anned in and compressed by the LFSR. Due to the use of scan chain for the delivery of test
patterns and responses, the test speed is much slower than the previous approach. The clocks required for a
test cycle is the maximal of the scan stages of input and

output scan registers. Also fall in this category i
n-
clude CEBS, LOCST, and STUMP. We will discuss these in detail.

C
i
r
c
u
i
t

U
n
d
e
r

T
e
s
t
S
h
i
f
t

r
e
g
i
s
t
e
r
L
F
S
R
L
F
S
R
S
h
i
f
t

r
e
g
i
s
t
e
r

Figure 7.31 Basic test
-
per
-
scan structure

Centralized and Embedded BIST Architecture with Boundary Scan (CEBS)



Centralized and Embedded BIST Architecture with Boundary Scan

l BIST

(CEBS) expands the basic
structure in Figure 7.31 to include internal scan chain in the scan path. The circuit diagram is shown in Fi
g-
ure 7.31. The test procedure is the same as the b
asic one. However, the test time can be very long due to the
inclusion of internal scan chains. Such a design is well compatible with the scan DFT design. The extra cost
in addition to the scan DFT is minimum. Hence, it is especially useful for the circuit
s with full scan
DFT.[Komanytsky 1982]

C
U
T
S
i
S
o
B
o
u
n
d
a
r
y
-
s
c
a
n

r
e
g
i
s
t
e
r
L
F
S
R
B
o
u
n
d
a
r
y
-
s
c
a
n

r
e
g
i
s
t
e
r
M
I
S
R
P
I
s
P
O
s
S
i
n
S
o
u
t

Figure 7.32 CEBS architecture

Self
-
Testing Using MISR and Parallel SRSG (STUMP)


The architecture of the self
-
testing using MISR and parallel SRSG (STUMP) [Bardell 1987] is shown
in Fig
ure 7.33. Instead of using only one scan chain, it uses multiple scan chains to minimize the test time.
Since the scan chains may have different lengths, the LFSR runs for N cycles (the length of the longest scan
chain) to load all the chains. For such a
design, the internal type LFSR is preferred. If the external type is
used, the difference between two LFSR output bits is only the time shift. Hence, the correlation between two
scan chains can be very high.


23

L
F
S
R
M
I
S
R
S
R
S
R
S
R
C
U
T
C
U
T

Figure 7.33 STUMP Ar
chitecture

7.5.3 Sequential BIST



The BIST techniques mentioned above either focus on combinational circuits or uses scan chains to
transform sequential circuit into combinational in test mode. The patterns being applied is independent of
test respons
es. Here, we would like to discuss the techniques that pertain the sequentiality of the circuit in
the test mode. The test patterns being applied is not only a function of test pattern generator. It is also d
e-
termined by the test responses. Since the respo
nses are circulated back as the test patterns, it is also called
circular BIST.

Cyclic Analysis Test System (CATS)


Cyclic analysis test system (CATS) is a typical example of circular BIST. The architecture of CATS
is shown in Figure 7.34. In test mode
, the outputs are fed back to the inputs directly. The responses are used
as the test vector without modification. If there are more inputs than outputs, one output may drive multiple
inputs. If there are more outputs than inputs, we can use XOR gates to d
o space compression, as the one
shown in Figure 7.24. The hardware overhead is very low. However, the fault coverage is circuit dependent.
The recyling of test responses might create the fault masking effects. Note that, fault masking here is diffe
r-
ent fro
m the aliasing discussed earlier. Here, the faulty and fault
-
free circuits have different test patterns.
[Burkness 1987]

C
U
T
x
n
.

.

.
.

.

.
y
1
y
n
.
.
.
M
U
X
.
.
.
b
i
s
t

Figure 7.34 Cyclic analysis test system architecture

Random Test Data (RTD)


Random test data (RTD) tr
ansforms internal flip
-
flops into MISR. The circuit structure is shown in
Figure 7.35. In normal mode, the MISR is operated as latches. In test mode, it operates as MISR. Both i
n-
ternal responses are compressed into and the internal test vectors are generat
ed from the MISR. RTD is able
to do one test per clock cycle. As compare to CATS, the hardware overhead is much higher. However, due

24

to the extensive use of MISR, the test responses are scrambled before being used as the test patterns. Hence,
the self mask
ing probability can be lowered.

M
I
S
R
M
I
S
R
M
I
S
R
S
i
n
S
o
u
t
P
I
s
P
O
s
C
U
T

Figure 7.35 Random test data architecture

Simultaneous Self Test (SST)


Instead of using MISR for internal memory devices,
simultaneous self test

(SST) uses a simpler
structure. The circuit st
ructure of SST in BIST mode is shown in Figure 7.36. In test mode, the internal
latches receive the XOR of the result from the normal feedback path and the contents of the previous latch.
As a result, the contents of the latches are scrambled by previous s
tages. In normal operational mode, the
XOR gates are disabled. [DasGupta 1982].

P
O
C
U
T
C
o
m
b
i
n
a
t
i
o
n
a
l
P
I

Figure 3.36 Simultaneous self test architecture

7.5.4
BIST for Structured Circuits


Structured design techniques are the keys to the high integration
of VLSI circuits. The structured ci
r-
cuits include read only memories (ROM), random access memories (RAM), programmable logic array
(PLA), and many others. In this section, we would like to focus on PLAs because they are tightly coupled
with the logic circu
its. While, memories are usually categorized as different category. Due to the regularity
of the structure and the simplicity of the design, PLAs are commonly used in digital systems. PLAs are eff
i-
cient and effective for the implementation of arbitrary log
ic functions, combinational or sequential. Ther
e-
fore, in this section, we would like to discuss the BIST for PLAs.


A PLA is conceptually a two level AND
-
OR structure realization of Boolean function. Figure 7.37
shows a general structure of a PLA. A PL
A typically consists of three parts, input decoders, the AND plane,
the OR plane, and the output buffer. The input decoders are usually implemented as single
-
bit decoders

25

which produce the direct and the complement form of inputs. The AND plane is used to
generate all the
product terms. The OR plane sum the required product terms to form the output bits. In the physical impl
e-
mentation, they are implemented as NAND
-
NAND or NOR
-
NOR structure.

A
N
D

P
l
a
n
e
F
i
r
s
t

N
O
R

P
l
a
n
e
I
n
p
u
t

D
e
c
o
d
e
r
s
.

.

.
.

.

.
PLA Inputs
O
R

P
l
a
n
e
S
e
c
o
n
d

N
O
R

P
l
a
n
e
O
u
t
p
u
t

B
u
f
f
e
r
s
.

.

.
.

.

.
PLA Outputs
.
.
p
r
o
d
u
c
t
l
i
n
e
s
.
.

Figure 7.37 A general structure of a P
LA.


As mentioned earlier in the fault model section, PLAs has the following faults, stuck
-
at faults, brid
g-
ing faults, and crosspoint faults. Test generation for PLAs is more difficult than that for the conventional
logic. This is because that PLAs hav
e more complicated fault models. Further, a typical PLA may have as
many as 50 inputs, 67 inputs, and 190 product terms [Liu and Saluja 198xxx]. Functional testing of such
PLAs can be a difficult task. PLAs often contain unintentional and unidentifiable re
dundancy which might
cause fault masking. Further more, PLAs are often embedded in the logic which complicates the test appl
i-
cation and response observation. Therefore, many people proposed the use of BIST to handle the test of
PLAs. So far, most PLAs in a
dvanced microprocessors have BIST. Here, we would like to discuss some of
them.

Yajima's PLA BIST

Yajima's scheme for the BIST of PLA is shown in Figure 7.38 [Yajima and Aramaki 1981]. Yahima’s
scheme has the following extra hardware for the BIST of PLAs.
(1) A modified
Augmented Decoder

(AD)
which activate one bit
-
line in the AND plane at a time. (2) A
Product Term Shift Register

(PSR) shifts 1 in
it to activate one product line to test OR plane. (3) Four extra product lines in AND plane for the parity of
the AND plane and the control of the test procedure. (4) An
AND Parity Circuit

checks the parity of the
product terms when one bit
-
line in the AND plane is activated at a time. (5) Two extra line in OR plane for
the parity and control of the OR plane testi
ng. (6) An
OR Parity Circuit

checks the parity of the sum terms
when product terms are activated one at a time by PSR. (7) A
Feedback Value Generator

generates nece
s-
sary control signals to control the test procedure. The use of FVG is based on the concept
of autonomous
testing.

In Yajima’s approach, the added hardware allows the PLA to activate one input bit
-
line at a time in the
AND plane by AD in testing the AND plane. The result is verified by the AND Parity circuit. In testing the
OR plane, one product

term in activated at a time by PSR and the results are verified by the OR Parity Ci
r-
cuit. The correct parity is accomplished by the two extra lines, one in each plane. The autonomous control is
achieved by the other extra lines. Yajima’s approach is able
to detect all stuck
-
at faults in AND/OR planes,
extra lines, AND/OR parity circuits, AD, and PSR. It can also detect all crosspoint faults in AND/OR

26

planes, original lines and extra lines. The limitation is that multiple faults coverage is not gua
r
anteed a
nd the
EXOR trees in the parity circuits influence the testing speed.

A
N
D

P
l
a
n
e
4

E
x
t
r
a

P
r
o
d
u
c
t

L
i
n
e
s
O
R

P
l
a
n
e
2

E
x
t
r
a
O
u
t
p
u
t
L
i
n
e
A
N
D
P
a
r
i
t
y
C
i
r
c
u
i
t
s
O
R

P
a
r
i
t
y

C
i
r
c
u
i
t
s
.

.

.
A
u
g
m
e
n
t
e
d

D
e
c
o
d
e
r
s
(
A
D
)
O
u
t
p
u
t

B
u
f
f
e
r
s
.
.
.
.
.


.


.


.


.


.
.
.
.
.
.


.


.


.


.


.
F
e
e
d
b
a
c
k

V
a
l
u
e
G
e
n
e
r
a
t
o
r
.
.
.
.
P
r
o
d
u
c
t
T
e
r
m
S
h
i
f
t
R
e
g
i
s
t
e
r
(
P
S
R
)
.
.
.
.
F
l
a
g
C
i
r
c
u
i
t
.


.


.


.


.


.
.


.


.


.


.


.
Y
C
o
n
t
r
o
l
S
i
g
n
a
l
s
P
L
A

I
n
p
u
t
s
P
L
A

O
u
t
p
u
t
s

Figure 7.38 Yajima's PLA BIST.

Daehn’s PLA BIST


Daehn and Mucha proposed the BIST of PLA based on the use of BILBO [Daehn and Mcha 1981].
BILBOs are used

for test pattern generation and and response analysis. Figure 7.39 shows the architecture
of Daehn’s approach. Here, BILBOs are inserted in between the interface of input decoder, AND plane, OR
plane, and output buffers. When testing the AND plane, BILBO1

works as the test pattern generator and
BILBO2 as the response analyzer. Instead of functioning as a pseudorandom pattern generator, BILBO1
shifts a 1 in the input bit lines to activate one bit line at a time (similar to Yajima’s AD). While, BILBO2 is
fun
ctioning as a MISR. For the OR plane testing, the situation is the same. This is a very simple approach as
compare to the previous one. It achieves 100% coverage on single stuck
-
at faults and crosspoint faults. The
most significant disadvantage is the area

overhead of the BILBOs.

A
N
D

P
l
a
n
e
B
I
L
B
O
1
I
n
p
u
t

D
e
c
o
d
e
r
s
O
R

P
l
a
n
e
B
I
L
B
O
3
O
u
t
p
u
t

B
u
f
f
e
r
B
I
L
B
O
2

Figure 7.39 Daehn’s PLA BIST


27

Liu’s PLA BIST

Liu et. al. proposed the design which requires a rearrangement of the AND/OR plane on the basis of
the number of crosspoints on the lines in the PLA [Liu 1987]
. Figure 7.40 shows the architecture of Liu’s
scheme. Different from the above methods, only one bit line and one output line are activated in the testing
of AND/OR plane. The extra line Z
1

with all the connection to the AND plane product lines is responsi
ble
for detecting the cross point at the intersection of the bit line (activated by TPG1) and the product line (a
c-
t
i
vated by TG2). If there is a crosspoint, then, Z1 will produces an one. The crosspoint counter (C1) will be
increased by one. At the end of
the testing, the count in C1 indicates the number of crosspoints in product
lines and/or in the plane. Simiarly, the same procedure is done for the OR plane. Such a technique is able to
detect all stuck
-
at faults and crosspoint faults.

AND Plane
Additional Logic to Control Input
(TPG1)
. . . . . .
.
.
.
.
Product
Shift
Register
(PSR)
. . . . . .
OR Plane
Output Buffers
. . . . . .
. . . . . .
PLA Inputs
PLA Outputs
Additilnal Logic to
Control Output Lines
(TPG3)
Crosspoint Counter
(C1)
Reference Counter
(C2)
Z
1
Z
2
Response
Evalutor
(RE)
External
Control
Input

Figure 7.40 Liu’s

PLA BIT.


7.6
BIST Applications

Manufactures are increasingly employing BIST in real products. Here, we offer several examples of such
applications to illustrate the use of BIST in semiconductor, communications, and computer industrial.

Exhaustive Test in the

Intel 80386 [Gelsinger 1987]

Intel 80386 has BIST logic for the exhaustive test of three control PLAs and three control ROM. For PLAs,
the exhaustive patterns are generated by LFSRs embedded in the input registers. For ROMs, the patterns are
generated by

the microprogram counter which is part of the normal logic. The largest PLA has 19 input bits.
Hence, the test length is 512K clock cycles. The test responses are compressed by MISRs at the outputs.
The contents of MISRs are continuously shifted out to an

LFSR. At the end of testing, the contents of
LFSRs are compared.

Circular BIST in AT&T ASICs [Stroud 1988]


AT&T has employed a partial sequential approach using circuit BIST in seven ASICs. The goal was

28

complete self
-
test except for I/O buffers and p
ortions of the multiplexer logic on the inputs. AT&T’s a
p-
proach uses a module similar to BILBO. In addition, BIST is provided for the embedded RAMs. There are
four ASICs has embedded RAM. The logic overhead is about 20% and the area overhead is 13%. The a
v-
e
r
age fault coverage is 92%. The large overhead is due to the small size of the chip. AT&T has automated
BIST design tools for standard cell design.

Pseudorandom Test in the IBM RISC/6000 [Ratiu and Bakoglu 1990] [Yen et. al. 1995]


The RISC/6000 has e
xtensive BIST structure to cover the entire system. In accord with their tradition,
RISC/6000 has full serial scan. Hence, the BIST it uses is the pseudorandom testing in the form of
STUMPS. For embedded RAMs, it performs self
-
test and delay testing. For t
he BIST, it has a on chip pr
o-
c
essor (COP) on each chip. In COP, there are an LFSR for pattern generation, a MISR for response co
m-
pre
s
sion, and a counter for address counting in RAM bist. The COP count for less than 3% of the chip area.

Instruction Cache B
IST in Alpha AXP 21164 [Bhavsar and Edmondson 1994]

Alpha AXP 21164 is a super scalar implementation of Digital’s Alpha AXP architecture. It has an 8
Kbyte direct mapped cache array. The cache is organized into several columns of by
-
1 RAM arrays stacked
si
de by side to support a data channel each. Figure 7.41 shows the BiST/BiSr structure of the cache. It c
o-
v
ers all three RAM arrays associated with the cache, namely, data, tag, and branch history table. The data
paths here contains Fill Scan Path, Read Scan

Path, Address Generator, Background Generator, and the
Failing Row CAM. Before packaging, the BIST do a BIST first. The failing rows are stored in the

C
a
c
h
e

A
r
r
a
y
F
i
l
l

S
c
a
n

P
a
t
h

R
e
a
d

S
c
a
n

P
a
t
h

&

C
o
m
p
a
r
e
s
p
a
r
e

r
o
w
s
B
a
c
k
g
r
o
u
n
d
G
e
n
e
r
a
t
o
r
C
o
n
t
r
o
l
S
e
q
u
e
n
c
e
r
A
d
d
r
e
s
s
G
e
n
e
r
a
t
o
r
F
a
i
l
i
n
g
R
O
W

C
A
M
F
u
s
e
s

Figuer 7.41 Instruction Cache BiST/BiSR of AXP 21164

Failing ROW CAM. If th
e third row fails, the “unrepariable cache” flag is raised to abort the testing. The
next step is the laser repair of the rows in the Failing ROW CAM. After repair, BIST runs again to verify.

Embedded Cache Memories BIST of MC68060 [Crouch et al. 1994]

MC
68060 has two test approach for embedded memories. First it has adhoc direct memory access for
manufacturing testing because it has the only memory approach that meets all the design goals. The adhoc
direct memory acess uses additional logic to make addres
s, data in, data out, and control line for each
memory accessible through package pins. An additional set of control signals selects which memory is act
i-

29

vated. The approach make each memory visible through the chip pins as though it is a stand
-
alone memory

array. For the burn
-
in test, it builds the BIST hardware around the adhoc test logic. The two
-
scheme a
p-
proach is used because it meets the burn
-
in requirements with little additional logic.

ALU Based Programmable MISR of MC68HC11 [Broseghini and Lenhert1
993]


Broseghini and Lenhert implemented an ALU
-
Based self
-
test system on a MC68HC11 Family m
i-
crocontroller. A fully programmable pseudorandom pattern generator and MISR are used to reduce test
length and aliasing probabilities. They added microcodes t
o configure ALU into a LFSR or MISR. It tran
s-
forms the adder into a LFSR by forcing the carry input to 0. With such a feature, the hardware overhead is
minimized. The overhead is only 25% as compare to the implementation by dedicated hardware.


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