KeyStone NETCPx

qualtaghblurtingMobile - Wireless

Dec 12, 2013 (3 years and 8 months ago)

93 views

KeyStone

Training

Network Coprocessor (NETCP)

Overview

Agenda


What is NETCP?


Purpose of the NETCP


NETCP

Block Diagram


Internet Protocol Classification Levels


Communication with the
NETCP

NETCP Subsystem Overview


What is NETCP?


Purpose of the NETCP


NETCP

Block Diagram


Internet Protocol Classification Levels


Communication with the
NETCP

What is the Network Coprocessor (NETCP)?

1 to 8 Cores @ up to 1.25 GHz

MSMC

MSM

SRAM

64
-
Bit

DDR3 EMIF

Application
-
Specific

Coprocessors

Power

Management

Debug & Trace

Boot ROM

Semaphore

Memory Subsystem

S

R

I

O





x4

P

C

I

e





x2

U

A

R

T

A

p

p

l

i

c

a

t

i

o

n

-

S

p

e

c

i

f

i

c



I

/

O

S

P

I

I

C

2

Packet

DMA

Multicore Navigator

Queue

Manager

O

t

h

e

r

s

x3

Network Coprocessor

S

w

i

t

c

h

E

t

h

e

r

n

e

t

S

w

i

t

c

h

S

G

M

I

I

x2

Packet

Accelerator

Security

Accelerator

PLL

EDMA

x3

C66x™

CorePac


L1

P
-
Cache

L1

D
-
Cache

L2 Cache

HyperLink

TeraNet

Network Coprocessor
consists of the
following modules:


Packet Accelerator
(PA)


Security Accelerator
(SA)


Ethernet Subsystem


Packet DMA
(PKTDMA) Controller

Purpose of the Network Coprocessor


Motivation

behind

NETCP:


Use

hardware

accelerators

to

do

L2,

L3,

and

L4

processing

and

encryption

that

was

previously

required

to

be

done

in

software


Goals

for

both

Packet

Accelerator

and

Security

Accelerator:


Offload

DSP

processing

power


Improve

system

integration


Allow

cost

savings

at

the

system

level


Expand

DSP

usability

within

current

products


Allow

DSP

usage

in

new

product

areas


Security

Key

applications:


IPSec

tunnel

endpoint

(e.g.

LTE

eNB,

...)


Secure

RTP

(SRTP)

between

gateways


Air

interface

(3GPP,

Wimax)

security

processing

NETCP Block Diagram

3
-
Port

Ethernet

Switch

CPSGMII

CPSGMII


CP_ACE

Security

Unit

MDIO 0 INTS

Switch Status INTS

SGMII 1

SGMII 0

CPU/3 Main
TeraNet SCR

CPU/3 CFG
TeraNet SCR

PKTDMA_VBUSM_TXRX



128 bits

Config 32
-
bits


PKTDMA

Controller

Pass 1 LUT

CDE

PDSP+

1

Pass 1 LUT

CDE

PDSP+

2

Pass 1 LUT

CDE

PDSP+

3

CDE

PDSP+

5

Timer16 1

Timer16 2

Timer16 3

Timer16 4

PDSP

Scratchpad RAM 1

PDSP

Scratchpad RAM 2

.

:

PDSP

Scratchpad RAM n

Timer16 5

32
-
bit VBUSP TeraNet SCR

32
-
bit VBUSP TeraNet SCR

Streaming Interface Switch

Pass 2 LUT

CDE

PDSP+

4

CDE

PDSP+

6

Timer16 6

CPMDIO

PA

Stats

INTD

SERDES

SERDES


CP_ACE

Security

Unit


PKTDMA

Controller

Packet DMA in NETCP

PKTDMA

PKTDMA

PKTDMA

PKTDMA

PKTDMA

PKTDMA

Queue Manager

SRIO

Network

Coprocessor

FFTC (A)

AIF

8192

5

4

3

2

1

0

.

.

.

Queue Manager Subsystem

FFTC (B)

Internet Protocol Classification Layers


Layer 2 (L2): Media Access Control (MAC) Layer


IEEE 802.3 standard


Layer 3 (L3): Internet Layer


Internet Protocol Version 4 (IPv4)


Internet Protocol Version 6 (IPv6)


Custom L3 Classification


Layer 4 (L4): Transport Layer


User Datagram Protocol (UDP)


Transmission Control Protocol (TCP)


Custom L4 Classification

Payload

UDP

IPv4

MAC

Data

L4

L3

L2

Example Packet

Communication with the
NETCP

NETCP

relies on QMSS and PKTDMA to communicate with the CorePac.


TX Queue Mapping


Q64
0
: PDSP1


Q64
1
: PDSP2


Q64
2
: PDSP3


Q64
3
: PDSP4


Q64
4
: PDSP5


Q64
5
: PDSP6


Q64
6
: SASS0


Q64
7
: SASS1


Q64
8
: Switch


RX Queues


Can use any
general purpose
queues (Q864
-
Q8191)


Can also use
other special
purpose queues
(e.g. 704
-
735)

PKTDMA TX channels mapped to
QMSS PA TX queues

For More Information


For more information, refer to the Network
Coprocessor (NETCP) User Guide.


http://www.ti.com/lit/SPRUGZ6


For questions regarding topics covered in this
training, visit the support forums at the
TI E2E
Community

website.