Kursplan høsten 2003

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Nov 3, 2013 (3 years and 11 months ago)

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Kursplan høsten 2003

Her er kursplanen for studieåret 2003/2004, høstsemesteret.

Kursene er akkreditert for deltagere i gradsprogrammet, bortsett fra
Java Web
Component Development with Servlets, JavaServerPages and
Javabeans

og
FPGA
-
Synthesis
.

Kursavgifte
n for kursene er kr. 11.900/14.800 pr. deltager for henholdsvis 4 og
5 dager. For FPGA
-
Synthesis er kursprisen kr. 4.800 pr. deltager.

Mer informasjon kan også fås ved henvendelse til Grethe Larsen, tlf.
32 86 95
46
, faks
32 86 95 51
.

KEVIT´s e
-
post adres
se er
kevit@hibu.no


KURS

TIDSPUNKT/VARIGHET

PÅMELD.FRIST

Java Web Component
Development with Servlets,
JavaServerPages and Javabeans

uke 38, 15.


19 september / 5
dager

29. august
2003

Software Requirements
Engineering

uke 41, 6.


9. oktober / 4 dager

12. september
2003

FPGA
-

Synthesis

(2)

uke 42, 13.


15. oktober / 3 dager

19. september
2003

Essential C++ Part Two

uke 45, 3.


6. november / 4 dager

10. oktober
2003

Object
-
Oriented Analysis &
Design with UML

uke 50, 8.


12. desember / 5 dager

14. november
2003

(1) Ikke akkreditert i gradsprogra
mmet.

(2) I samarbeid med Mentor Graphics, ikke akkreditert i gradsprogrammet



Java Web Component Development with Servlets,

JavaServerPages and Javabeans

Duration: 5 days

Course Description

The Web Component Development w
ith Servlet and JSP[tm] Technologies course
provides students with the knowledge and skills needed to quickly build reference
implementation
-
compliant Web tier components from JavaServer Pages[tm] (JSP) and
Java[tm] Servlet extensions using the Tomcat serv
er environment. Students are exposed
to the current best practices for analysing, designing, developing, testing, and deploying
Web applications with Java technologies. Real
-
world lab exercises provide students
experience with constructing and deploying sm
all
-

to medium
-
scale Web applications
found in intranet and low
-
volume commercial sites.

This course also provides an ideal method of preparing for the Sun Certified Web
Component Developer certification examination. As such, students are not only taught
t
he technical details of JSP and servlet technology, they also learn about the best
practices for integrating the Web tier with the other tiers, from the browser display to
Enterprise JavaBeans[tm] (EJB[tm]) components running on an application server and
b
ack
-
end database resources.

What You Will Achieve

Who Should Attend

Delegates with Java programming experience.

Course Content


Java Servlets, JavaServerPages, JavaBeans and their correct use in the Model
-
View
-
Controller


Handling HTTP Requests and Respons
es


Develop a HTTP servlet that accesses form data


Describe the requirements of a robust web application model


Deploy a web application using a deployment descriptor


Develop robust Servlets and JSPs using error handling


Write servlet code to capture a
Java technology exception and forward it to an
error handling servlet


Write servlet code to log exceptions


Explain the importance of Web security


Use the deployment descriptor to configure authorization for a Web application
resource


Use the deployment

descriptor to configure authentication of users of a Web
application


Describe the attribute scope rules and the corresponding concurrency issues


Describe the single thread model for servlets and the issues with this concurrency
strategy


Design a Web ap
plication for concurrency


Design a Web application to integrate with a DBMS


Develop a Web application using a connection pool


Develop a Web application using a data source and the Java Naming and Directory
Interface[tm] (JNDI)


Describe JavaServer Page
(JSP) technology


Write JSP code using scripting elements


Write JSP code using the page directive


Create and use JSP error pages


Describe the structure and execution of a custom tag in a JSP page


Develop the tag handler class for a simple, empty custom

tag


Write the tag library description for a simple, empty custom tag


Develop a custom tag that includes its body in the content of the HTTP response


Develop a custom tag in which the body is conditionally included


Understand the J2EE software at a hig
h level


Develop a Web application that integrates with an EJB component using the
Business Delegate pattern



04.12.02

Software Requirements Engineering

Course Code : SDV08

Course Description

Incorrect or incomplete requirements specifications are the
major cause of software
development problems. This course covers the software engineering discipline used to
establish a software specification that captures correctly and completely the
requirements of a software system under development and the expectati
ons of the
potential user.

What You Will Achieve

At the end of the course you will:




have an understanding of the importance of software requirements engineering




be able to identify software requirements




be able to understand the effectiveness of and
use the Concept of Operations
(ConOps) document




be able to analyse a user's software requirements and document this requirement
as a software requirements specification




be able to plan for and control the development of a software requirement




be able

to verify software requirements




identify the most effective software requirement tools and techniques for
successful software development

Who Should Attend

Software and system engineers, project managers, quality assurance personnel,
and verification a
nd validation engineers.



Course Content

Modules on: The Engineering of Software Requirements, Software Requirements
Concepts, System and Software System Engineering, Requirements Elicitation,
Concept of Operations (ConOps) Document, Software Requirements

Analysis,
Software Requirements Specifications, Software Requirements Tools, Software
Requirements Verification, Software Requirements Engineering Management,
Developing a Successful Software Requirement.



19.06.03

FPGA
-

Synthesis

Course Code : HLD03

3
-
day Kevit course
-

supported by Mentor Graphics Scandinavia and Memec Norway
-

offered at Buskerud University College, Kongsberg, in the period

13/10

15/10/

2003

Course Price, Registration and Practicalities

The course price is 4800 NOK, which amount c
overs lunch and a complete set of course
materials. For companies registering more than 10 attendees a special discount is
available. Course deliveries are subject to the condition of a minimum of 10 attendees. A
detailed agenda will be sent to all attende
es well ahead of the course start. For
registration please contact Grethe Larsen at

Grethe.Larsen@hibu.no

Tel: +47 32869546

Fax: +47 32869551



before 19/09/03.

Course Description

A previous version of this three
-
day course has been delivered to univers
ities and
colleges, companies, and R&D institutes in several European countries. The contents
have been particularly adjusted to meet the needs of working engineers and system
developers taking up language
-
driven digital design and focusing on modern FPGA
target
technologies. An abbreviated version of the theory
-
part has been used for an invited full
-
day tutorial at the CAE conference "DAK
-
Forum" in Trondheim, Norway.

In its present form the course module reflects experience from previous course deliveries

and valuable advice from leading companies. It contributes insight into strong
-
points of
current FPGAs, methods and techniques of VHDL
-
driven RTL
-
synthesis, presents

synthesizable language constructs and the P1076.3 standard synthesis
recommendations, an
d contrasts simulation with synthesis semantics. The exposition is
application oriented and reflects the view that the subject matter is best explained
through examples carefully selected to illustrate coding styles and decisions conducive to
high
-
quality
designs and avoidance of typical pitfalls.

Particular emphasis is placed on powerful features of the Xilinx Virtex

family and on how to best exploit these features in a synthesis methodology. In
particular this updated and extended course includes theory
and practice on soft
embedded processor cores and dsp facilities.

The course is organized as a three
-
day introduction to basic synthesis theory, current
status of FPGA technology, and language
-
driven
-
design methodology; dividing time
equally between practi
cal design tasks and presentation of key concepts.

Buskerud College will present an overview of the possibilities and limitations of current
digital synthesis technologies, Mentor Graphics Scandinavia will contribute an in
-
depth
account of its state
-
of
-
th
e
-
art synthesis tool as well as generic advice on modular and
hierarchical design, while Memec Norway will give an overview of new and advanced
features of modern FPGAs.

Practical exercises are based on the 1993 version of the IEEE 1076 standard, the IEEE

1164 substandard, VITAL/SDF formats, access to state of the art Xilinx Virtex FPGA
technology and the market leading tools Modelsim and Leonardo Spectrum from Mentor
Graphics. New and revised exercises have been detailed by Buskerud College in
cooperation

with Mentor Graphics. They are supported by ready
-
made test
-
benches and
VHDL
-
RTL descriptions in various stages of prefabrication to accommodate users with
different levels of previous VHDL experience. The entire set of exercises constitutes a
complete se
t of design files for a simple digital camera. One workstation becomes
allocated to each attendee.

What You Will Achieve

By the end of this course you will:


understand the advantages of high level description languages in logic design on
the RT
-
Level.


kn
ow how to apply de
-
facto standard, synthesis oriented VHDL packages.


understand the possibilities and limitations of current RT
-

tools and thereby
become able to avoid typical pitfalls.


gain practical experience with the state
-
of
-
the
-
art Leonardo synthes
is tool.


be familiar with strongpoints (e.g. embedded processors and dsp facilities) of the
powerful Xilinx Virtex FPGA family and know how to implement them within a
VHDL environment.


understand the particular rules that apply to FPGAs within an automat
ed synthesis
design flow.


Gain insight into hierarchical and modular design.

Who Should Attend


Engineers engaged in digital systems design.


In order to get the most from this course, it is necessary to have:


Working knowledge of VHDL


Working knowledge

of digital electronic systems




19.06.03

Essential C++ Part Two

Course Code : STL10

Course Description

This course moves into more complicated regions of C++, covering specialised elements
along with techniques that the language encourages.

What You W
ill Achieve

Exposure to involved elements within C++; exposure to the application of C++ to
existing problems and the opportunities that the language provides.

Who Should Attend

Software Developers who have constructed their first classes and are familiar

with
the core language as covered in Essential C++ Part One.
(1)


Course Content

Modules on: Containers and Iterators, Pure Virtual Functions, Multiple and Virtual
Inheritance
, Enumerations, Templates, Exceptions, Namespaces, Standard
Template Library (STL), Auto Pointers, Run
-
time Type Information (RTTI), Pointer
to Member Functions, New Cast Notation, Streams, String Classes, Pre
-
Processor,
Mutable.



(1) For KEVIT:

Part One

kreves ikke, forutsatt at deltagerne har generell programmeringskompetanse og
-
erfaring, helst grunnleggende standard C programmering.

14.10.03

Object
-
Oriented Analysis & Design with UML

Course Code : SAD17

Course Description

As a
lingua franca

for obje
ct modelling, UML has been widely adopted. It is the industry
standard notation for OO models, is under continuing development by OMG and has a
solid base of support from the CASE tool vendors.


This course focuses on two
complementary areas
-

firstly, the

application of techniques for OO
-
based analysis of real
world problems and, secondly, the syntax of UML and the nature of UML diagrams
-


because it is never sufficient to know a language; you must know how to apply it in
context.

Practical examples, in t
he form of case studies, are presented and solved both as
group and individual exercises.

What You Will Achieve


you will understand the concepts of the OO paradigm and how they apply to the
analysis of software systems, to system and object design,


be ab
le to apply Use Case Modelling to capture the essential specification of a
system,




understand the Use Case driven approach to the process of constructing static and
dynamic models of a system,




be able to evaluate alternative strategies for identifying
'good' objects,


apply those strategies to construct and review static and dynamic models, based
on the criteria of reusability, stability and maintainability




be familiar with the diagram elements of UML notation,




understand the concept of Design Patte
rns and see patterns in action both to
solve architecture problems and problems of decoupling among objects,


gain experience with a leading CASE tool for OO software development

Who Should Attend

Systems and software engineers who need to become proficie
nt in OO Analysis
technique. Project managers who wish to evaluate UML or understand the
migration route to this


approach from the other mainstream software
development methods. Business analysts who specify information systems.



You should be familiar w
ith an OO programming language, typically C++ or Java,
in order to benefit from the discussion of polymorphism and the use of abstract
classes in the design phase of this course.

Course Content

Modules on: The Object
-
Oriented Paradigm, UML Overview, The O
bject Model, Use
Case Analysis, Advanced Object Modelling, Identifying and Specifying Dynamic
Behaviour, Design of Collaboration Between Objects, System Level Design Issues,
Object Level Design, Detailed Design, The


Process of OO Software Development.

A
CASE tool is used on this course along with the textbook


Unified Modelling
Language User Guide,


Booch, Rumbaugh, Jacobson (1999).


Addison Wesley
Longman, Inc.

04.12.02