Signal Processing Objects for Wireless Communications and the ...

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Nov 24, 2013 (3 years and 9 months ago)

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Signal Processing Objects (SPOs)

for

Wireless Communications

and
Software Defined Radio

SDR
Communications Systems

Introduction


Wireless Communications

Cell phones, wireless internet, etc.



Software Defined Radio

Radio technology is moving away from analog to almost entirely
digital. This opens up the possibility of designing adaptive
systems which can be reconfigured to respond to virtually any
waveform being transmitted. Adaptive systems are of particular
interest to the military where, at present, there is little
compatibility among the radio equipment used by the different
services.

Introduction


Why a new SPO ?
(Signal Processing Object)


Academia (University of California at Berkeley, e.g.) and
industry (Quicksilver and Pentek, e.g.) are moving away from
the use of DSPs in wireless applications such as SDR.


The SPO is a new and novel (ITT proprietary) approach to the
construction of the SDR using FPGA technology.


The SPO is based on proven designs used in military systems
as far back as the early 80s.



Signal Processing Object

What is it?


Block Diagram







Implementation


The object can either be
software



-

a
m
P or DSP program, or
hardware…

-

a cell on a FPGA, ASIC or custom integrated circuit.


S
X
S S D


SPO

Product Offerings

SDR Communications Systems



A reconfigurable Xilinx FPGA digital signal processor based on
the proprietary SPO architecture.



A board level product offering high speed digital signal
processing using FPGA Based reconfigurable processors.



A software suite based on Matlab products.



Competitive Advantages


A unified (software and hardware) approach to the specification
and design of reconfigurable systems



Efficient means ( software and hardware) for implementing
signal processing algorithms for all waveforms



Means for meeting critical system design requirements.


-

Low power


-

Greatly reduced memory requirements for


configuration management


-

Greatly reduced programming effort because we offer a


direct path
-

from mathematical description to hardware

Other Perspectives on DSP for

Wireless and SDR Applications


Berkeley


Quicksilver


Triscend


Pentek


Xilinx


QuickLogic


Annapolis Micro Systems

Recent Technical Publications



“A Reconfigurable Architecture for Digital Signal
Processing” , Susan Emeny, Fred Schlereth, ERSA,
2001.


“A Reconfigurable * GOP ASIC Architecture for High
Speed Data Communications, E. Grayver, B.
Daneshrad, IEEE Journal on Selected Areas in
Communications, Vol 18, No. 11, November 2000.






Past Technical Publications


"A Programmable Signal Processor for Array
Applications," IEEE International Solid State Circuits
Conference, 1987.



“ A New Method for Circuit Simulation Suitable for
Parallel Computing”, Ping Chen Koo, Ph.D.
Dissertation, Syracuse University, May 1993,


"The Signal Processing Circuit", Miconex'87
Conference Proceedings, Winnipeg, Canada, 1987.





Past Technical Publications


"The Cellular Array Computer", Proceedings, 30th
Midwest Symposium on Circuits and Systems 1987.



U.S. Patent No. 4,128,890, “Integrated Arithmetic
Unit and Digital Networks using the Unit”, Irwin,
Schlereth, issued December 5, 1978


“The Design of Digital Leapfrog Ladder Filters",
Conference Record of the Eighth Asilomar
Conference on Circuits, Systems and Computers,
1974, pg. 294.



Signal Processing Object

Berkeley Perspective


In the following slides we present some of the
ideas being promoted by the


Berkeley Wireless Research Center


Note

we will see that

the SPO we have defined above is the
next step

in the design approach being promoted at Berkeley.

Berkeley Wireless Research Center
Communications Algorithms and Their
Implementation

Blast algorithms (Lucent)
-
antenna arrays which
have demonstrated 40 bits/Hz (1Mb/s in 25kHz)

Multiuser detection
-
eliminates multiuser
interference

Digital implementation of timing and carrier
synchronization …
Requires 1000’s of
MOP’s
of processing

how to do it at the lowest energy
and smallest area???
Berkeley Wireless Research Center
First choose the right architecture …
MAC
Unit
Addr
Gen
m
P
Prog Mem
Embedded
Processor
(
lpArm
)
Direct Mapped
Hardware
Embedded
FPGA
DSP
(e.g. TI 320CXX )
Flexibility
Area or Power
Reconfigurable
Processors
(
Maia
)
Factor of 100
-
1000
100
-
1000
MOPS/mW
10
-
100
MOPS/mW
.5
-
5
MIPS/mW
Berkeley Wireless Research Center
Comparison
-
Software
vs
Direct mapped
Wideband CDMA

FDMA


Matched
Filter

Trained

MMSE

Blind

MMSE

Multiple

Antenna

Parallel
Processors

5

11

23

87

Power (mW)

70

150

300

1150

Software
Programmable

(Optimized for
DSP)

Area (mm
2
)

115

250

530

2000


Power (mW)

.4

1.6

3.1

8

Direct Mapped

Area (mm
2
)

.6

2

3

10



Software solutions > 100 times less efficient
(even ignoring
overhead of parallel processing)
»
.5
-
5 MIPS/mW software DSP (best case) processor
»
100
-
1000 MOPS/mW dedicated
Berkeley Wireless Research Center
Is Arbitrary Digital Complexity Possible?

Complexity is increasing by a factor of 100
every 10 years

so that is not a problem

The power requirements are!

Conclusion

the energy efficiency of the
architectures and algorithms is critical
Berkeley Wireless Research Center
The Situation Now for Embedded Applications

Hardware is cheap
»
Potentially 1000’s of multipliers on a
chip

Power, cost and size is critical

Applications are I/O and DSP
intensive

Software is becoming “harder” than
hardware

Hardware and software are on one
chip
Berkeley Wireless Research Center
Time multiplexing a multiplier … is
that a good idea?
DSP processor
(25 mm
2
)
12x12 multiplier
(.05 mm
2
)
Berkeley Wireless Research Center
What is the solution?

Software based parallelism is becoming
increasingly inefficient
»
Speculative execution,
Superscalar
, VLIW

The basic problem is that a conventional
software description obscures the parallelism
Algorithms
Software
Architecture
Parallel
Sequential
Parallel
A Better Approach
-
skip the sequential
description
Algorithms
Architecture
Parallel
Parallel
Berkeley Wireless Research Center
An Energy Efficient Architecture: Direct Map
Describe the algorithm using
a description which preserves
the parallelism and
directly
convert to hardware
Berkeley Wireless Research Center
Module generation

Take parameters (e.g.
bit width) from block
diagram as input and
generatelayout

Allows deterministic
area, power and delay
estimates

Retains optimized
density, speed and
power of custom design

Allows reuse
e.g. 12X12 Multiplier
Berkeley Wireless Research Center
Energy, Area and Delay parameters from
Module Generators
2
2
00017
.
0
0019
.
0
0044
.
0
)
(
N
N
mm
Area



Area model of complex MAC in terms of word length:
Energy model of real multiplier in terms of word length:
2
019
.
0
15
.
0
68
.
1
)
/
(
N
N
MHz
W
Energy



m
N = 12
-
bit

Area (mm
2
)

Energy (
m
W/MHz)

Delay (ns)

Real multiplier

0.051

6.2

18.5

Complex multiplier

0.182

24.9

20.7

Complex MAC

0.272

37.2

27

Adder

0.003

2.4

8.7

Memory(128x16)

0.04

7.0

8.0


Signal Processing Object

ITT Perspective


Berkeley is “right on” in terms of perspective.



But … how to do it?


… how should these ideas be


implemented in hardware and software?


… how, specifically, can the four problem descriptions


system level, mathematical, algorithmic, hardware


be unified into a single “language”.



The following is the proprietary ITT solution.

Signal Processing Object

ITT Perspective


Think in terms of an SPO rather than just a multiplier or
dynamic cells.



An SPO is a “digital operational amplifier”, analogous to an
analog op
-
amp.



As with analog op
-
amps, SPOs fall naturally into arrays


no
sequential programming step (ala Berkeley) is required.



The state variables of the digital system are identical to the state
variables of the analog system. (
particularly important in filters
)

SPO Application Example

Signal Processing Object

ITT Perspective


SPOs are an efficient use of chip area

-

A single FPGA or ASIC can have 50
-
100 SPOs



SPOs are easy to program

-

virtually all signal processing operations are stored


in ROM, on the chip

-

An array of SPOs is derived from a direct map of the system


equations



A consequence of the SPO architecture is that a circuit



is as much software as hardware




Signal Processing Object

ITT Perspective



and finally … Power Savings


-

Each of the operations using SPOs can run at a clock rate
suited to the task being performed.

-

High rate filters operate at high clock rates


low rate filters


at low clock rates.

-

SPOs can have narrow busses




SPOs are an embodiment of the architectures envisioned


by groups such as Berkeley and the companies mentioned
above; Quicksilver, Pentek, Triscend.



Signal Processing Object

Quicksilver Technology Perspective


“The future of wireless/mobile communications and software
-
defined radio (SDR) is in making handsets a more versatile and
valuable product for consumers.”



“Existing, conventional methodologies and integrated circuits
(ICs)
--

microprocessors, digital signal processors, FGPAs, and
ASICs
--

are having a difficult time keeping pace with today's 2G
requirements for handsets. This will be increasingly more
difficult with the emergence of 3G and 4G technologies.”




Signal Processing Object

Quicksilver Technology Perspective


To meet these emerging needs, QuickSilver's first initiative is
the adaptive computing machine
TM

(ACM), a new class of digital
integrated circuit technology (IC) that will be embedded directly
into handsets, or mobile devices, of the future.



The ACM's architecture has inherent system adaptability in
which dynamic algorithms are directly mapped onto dynamic
hardware resources, resulting in the most efficient use of
hardware in terms of cost and size, with amazingly high
performance and extremely low power consumption.


Signal Processing Object

Quicksilver Technology Perspective


“The key problem is that traditional hardware and software
design tools and devices (including ASICs,
m
Ps, DSPs, and
FPGAs) are based on "rigid computing" techniques, which rely
on the use of rigid hardware resources and/or rigid algorithms. “



“By comparison, "adaptive computing" (ACM) is a revolutionary
new method of computing in which dynamic algorithms are
directly mapped onto dynamic hardware resources, resulting in
the most efficient use of hardware in terms

of cost, size (silicon
real estate), performance, and power consumption.”


Signal Processing Object

Quicksilver Technology Perspective


uP/DSP uses fixed, general purpose hardware to reconfigure by
changing algorithms. This results in an inefficient use of
resources.



ASICS use fixed resources and algorithms which are not easily
adaptable



What is needed are dynamic hardware resources (ACM) that
can be deployed quickly (on the fly) to meet dynamically
changing algorithmic demands.



Quicksilver’s claim is that ACM will lead to the


Death of the DSP




Signal Processing Object

Triscend Technology Perspective


The emerging Configurable System
-
on
-
Chip (CSoC) market is
quickly establishing itself as one of the most exciting sectors in
the semiconductor industry.


Fueled most notably by communications applications, the CSoC
sector is poised to explode into a

$50 billion market by the end of the decade.



Dataquest's estimates tell us that CSoCs will, within ten years,
account for about

80% of all SoC
-
class semiconductor devices shipped
.


Signal Processing Object

Pentek Technology Perspective


By incorporating the new generation of FPGAs in the
architecture of the typical software radio system, processing
tasks can now be judiciously split between the FPGA and the
DSP.



FPGA's are especially suitable for bit manipulation, pattern
recognition, frame detection, decoding and formatting. When
performed by the DSP, these low
-
level tasks consume many
valuable processor cycles and do not take full advantage of
DSPs signal processing hardware.





Signal Processing Object

Pentek Technology Perspective




By freeing the DSP to concentrate on more complex and
sophisticated tasks, the use of FPGA's can be a useful strategy
for improving system performance and throughput, lowering
total system cost, as well as shortening development time.

Signal Processing Object

Xilinx, Quicklogic Technology Perspectives


Xilinx very recently announced its Platform FPGA
initiative, which will embed hard cores into an FPGA.
The first Platform FGPA devices will put an IBM PowerPC
405 microprocessor hard core and up to 90 18x18
multipliers onto a single Virtex II chip. Cost is about
$100.



Another programmable
-
logic convert is QuickLogic,
which has announced its intention to produce a CSoC
device that incorporates a MIPS processor.

QuickLogic, which calls its configurable devices
Embedded Standard Products (ESPs), embeds a hard IP
core with a programmable logic array, coupling the core
and array with a high
-
speed interface.



Signal Processing Object

Annapolis Technology Perspective


Annapolis Micro Systems, Inc. has earned a reputation for
excellence in the areas of


-

Custom XILINX FPGA Design

-

System Design

-

Application Development

-

ASIC Design

-

Complex Printed Circuit Board Design

-

Surface Mount Assembly

-

Customer Support



These key competencies have allowed Annapolis Micro
Systems, Inc. to become the market leader in the emerging
technology of Reconfigurable Computing.



Signal Processing Object

Annapolis Technology Perspective



In 1994 Annapolis Micro Systems, Inc. licensed the technology
for SPLASH 2, a Reconfigurable Computing Engine, from the
US National Security Agency, as part of NSA's Technology
Transfer Program.


With the release of WILDFIRE
TM
, our Xilinx 4000 Series based
VME product, which had 17 Processing Elements, we became
leaders in the field of Adaptive Computing.



Start
-
up Strategy


SDR Communications Systems


Design FPGA using Proprietary SPO

An initial design has been started.


Secure patent protection for architecture

Our patent attorney believes that a simple extension of our earlier
patent will issue.


Contract with a company such as Annapolis Micro
Systems to build a board.


Market this product to military customers


Special Strengths


SDR Communications Systems


Expertise in system and circuit architecture

Our emphasis is on “broader” issues such as
configuration
management, transaction processing analysis and power minimization
.
Circuit and board design and manufacture will be contracted.
Algorithms for communications systems will be provided by customers.


Strong relationships with potential customers


ITT, Rome Labs


Strong relationship with sources of technical talent


SU, CASE


Experience with start
-
up management

Initial Requirements


SDR Communications Systems


Tasks


System design and general management


FPGA circuit design


Applications engineering


Market development


Manpower Complement


Three senior professionals


Three junior professionals


Secretarial, accounting, legal


Computing Equipment and Licenses


Xilinx, Matlab

Schedule
(first nine months)


SDR Communications Systems



Complete a board level product suitable for beta test


Complete patent application


Secure contracts for specific applications


Secure additional financing

Present Activities



The ITT effort is for system analysis for SDR using
microprocessors developed at ROME LAB.


Working with CHASS, Inc. to develop smart antennae


Teaching courses in wireless communications


Seeking first round financing for



SDR Communications Systems