UNIVERSITY OF NEW YORK AT BUFFALO

parkagendaElectronics - Devices

Nov 2, 2013 (3 years and 11 months ago)

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UNIVERSITY OF NEW YORK AT BUFFALO

Department of Electrical Engineering







CSE593 INTRODUCTION TO VLSI ELECTRONICS






PROJECT REPORT ON


SRAM LEAKAGE SUPPRESSION BY MINIMIZING
STANDBY SUPPLY VOLTAGE


SUBMITTED BY


DARISH M SONY

JOEL G ABRAHAM









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Table of
Contents


1. INTRODUCTION

................................
................................
................................
.............................
4

2. BASIC DESIGN OVERVIEW

................................
................................
................................
..........
5

2.
1 BLOCK DIAGRAM

................................
................................
................................
....................
5

2.2 BASIC WORKING
................................
................................
................................
......................
5

3. COMPONENTS

................................
................................
................................
................................
6

3.1 6T SRA
M Cell

................................
................................
................................
.............................
6

3.2 Layout

................................
................................
................................
................................
..........
9

3.3 Schematic

................................
................................
................................
................................
...
10

4. Word Pre
-
Charge

................................
................................
................................
..............................
10

4.1 Layout & Schematic
................................
................................
................................
...................

11

5. Write Driver

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................................
................................
................................
.....

11

6. Entire Memory Desig
n
................................
................................
................................
.....................
12






























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S
PECIFICATIONS




Individual 6
T

Cell Size

Width

9.6um

Length

20.25um

Area

194.4um2







PAD FRAME
DETAILS





PIN USAGE

Pin

Pin
Usage

Pin

Pin

Usage


1

D0

21

NC

2

B1

22

B4

3

D1

23

D3

4

B1

24

NC

5

NC

25

GND

6

Vdd

26

NC

7

NC

27

B5

8

D2

28

D4

9

B2

29

B6

10

NC

30

D5

1
1

A0

31

D6

12

A1

32

A4

1
3

NC

33

NC

1
4

NC

34

B7

1
5

NC

35

NC

1
6

A2

36

NC

1
7

NC

37

D7

1
8

NC

38

WEnable

19

A3

39

A5

20

B3

40

REnable

512 Bit Array

Width

307.2um

Length

337.05um

Area

103.54mm

Avg Area/Cell

202.23um2

Pad Frame
Pin
s


PADFC

Pad frame corner, non
-
usable

PADAREF

Analog reference pad, non
-
usable

PADGND

Pad ground, 1 pad

PADINC

Buffered input pad: The input signal to
chip received at the pad is buffered and
the signal and its complement mad
e
available to the circuit inside, 9 pads

PADIO

Input/output pad, 7 pads

PADNC

Spacer pad, non
-
usable

PADOUT

Output pad with buffer, 8 pads

PADVDD

Vdd power pad, 1 pad



40

39

38

37

36

35

34

33

32

31

1



30

2

29

3



28

4



27

5

26

6



25

7

24

8

23

9



22

10


21
11

12 13

14

15

1
6

17

18

1
9 20

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1. INTRODUCTION


Many of elec
tronic equipments use memory for the process execution. In other way, memory is an
extremely important part of digital electronics. Suppressing the leakage
current in

memories is critical
in low
-
power design. By
reducing the

standby supply voltage (Vdd) to

its limits; which is the Data
Retention
Voltage (
DRV), leakage current can be substantially reduced. In SRAM design the Data
Retention
Voltage (
DRV) defines the minimum VDD under which the data in the memory is preserved.
In this project we targeted ultra
-
low power applications and
used a

customized on
-
chip switched
capacitor converter to generat
e

the standby Vdd.


The following table shows the specifications with which the SRAM was build.


SRAM Specification

Total Memory

512 Bits

Address Lines

6(4
-
Word
line,2
-
Read/Write)

Data Lines

8

Read Enable

1

Write Enable

1

Vdd & Gnd

1 each

Standby Voltage

1





We have designed
a
512

bit SRAM and it was laid out using the IBM 60nm process. The key
design tools used are Cadence’s Virtuoso for layout editing and
Calibre DRC (for design rule
checking).




16 rows x 32 columns = 512 bits



8 bit Read and 8 bit Write



6 Address Lines are used





4 Lines are used for Word Line selection





2 Lines are used
for Byte selection for Read/Write



8 Data Lines



1 Read Enable



1 Write
Enable



1 Standby Voltage



















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2
. BASIC DESIGN OVERVIEW


The SRAM is a memory architecture which is capable of storing data as long as the power supply is
active. The SRAM that we have designed consists of 16 rows and 32 columns of memory cell
s. Each
row consists of 4 words. All the first bits of the four words are grouped as one column. Effectively
there will be 32 columns as each word is 8 bits in size.

2
.1
BLOCK DIAGRAM



Figure
1
-
SRAM Block

The above is the entire

block diagram of the (16 x 32) SRAM.

2.2 B
ASIC WORKING


Figure

1 shows the basic block diagram of the circuit.
The components of the SRAM compri
s
es of




6


Transistor SRAM cell



Row Decoder



Column Decoder



Word Pre
-
charger



Column Multiplexer



Write driver



S
ense Amplifier



D
RV(Data Retention Voltage) Unit


The 4 Address lines A0
-
A4 are given as inputs to the Row Decoder. Using these 4 lines
the

16
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Word lines

are selected.

The data stored in the SRAM is a
c
cessed through the bit lines which is
connected to the R
ead Circuit. The Address lines A5

&

A6 are used to select the 8 bit word
. D
a-
ta is written to the SRAM unit in a similar manner. The Write circuit uses address lines A5

&

A6 to select the 8 bit word to be written to the SRAM.

The DRV unit is initialized on
giving the
Standby Voltage Supply
. On doing so, the SRAM unit alone gets fed with the standby VDD.


3.

CO
MPONENTS

3.1 6T SRAM Cell


The 6T cell stores a bit and its complement inside it. It consists of two access transistors and two i
n-
verters

connected ba
ck to back to form a latch. The sizing of the inverters and the access transistors
could be kept

as minimum sizes so that the overall SRAM area is kept minimum. But the scenario of
read stability and

write st
a
bility needs to be taken into consideration.

3
.1.1
Schematic









Figure
2
-


6T Wire Schematic



Figure 2 shows the schematic of a 6T SRAM cell. M2
-
M1 and M4
-
M3 form the cross
-
coupled inverters
that store the actual data. M5 and M6 are the access transistors through

which read and write is ca
r-
ried out.

BL and BL are the bit lines through which data is read and written. WL(Word Line) is the co
n-
trol signal to switch on the access transistors M5 and M6.

3.1.2
Write
Operation


For Write Operation, we drive one of the Bit

lines high and the other one low and then turn on the
word

li
ne. The Bit lines overpower the cell
with the

new values. The new value should be able to
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overpower the feedback i
n
verters
. Assume 1 is stored in the cell(or Q=1). A 0
is written in the cell by
setting BL to 1 and BL to 0.

This causes the inverters to change states if sized properly.


During the initiation of a write, the schematic of the SRAM cell be simplified into the model as show in
Fig 3.

It is reasonable to assume that the gates of transi
stors M1 and M4 st
ay at Vdd and GND respe
c-
tively, as long as the switching has not commenced.



Figure
3

-

Simplified Operation during Write


Q cannot be pulled high enough to ensure the writing of 1. The sizing constraint,
impos
ed by

the read
stability, ensures

that this voltage
is kept below the threshold voltage. Hence, the new value has to be
written through transistor M6.


A reliable writing of the cell is ensured if we can pull node Q low enough
-

this is below the threshol
d
value of the transistor M1. The condition for this can be derived by writing out the dc current equ
a-
tions

at the desired threshold point as follows.




Sol
v
ing for Vq leads to



where
Pull
-
up
-
ratio

(PR) is defined as

PR

= W4/L4









W6/
L6

The value of PR has to be less than 1.8.

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3.1.3
Read
Operation


For Read

Operation both the bit lines BL and BL

are pre
-
charged to 1

before the read operation
.

A
s-
sume that Q is 1, and hence Q has 0.
The read cycle is started by asserting t
he word li
ne, enabling
both the access transistors M5 and M6 after the in
i
tial word
-
line delay. During a correct read oper
a-
tion , the values stored in Q and Q are transferred to the bin lines by
leaving BL at its pre
-
ch
arge value
and by discharging BL through M1
-
M5.

A careful sizing of the transistors is necessary to avoid acc
i-
de
n
tally writing a 1 into a cell. This type of malfun
c
tion is called read upset.


This is illustrated in Fig 3.

Consider the

BL side of the cell. The bit line capacitance for larger memories



Figure

4
-

Simplified Operation during Read


is in the pF range. Consequently the value of BL stays at the pre
-
charged value of Vdd upon enabling
of the read
operation (
WL
--
> 1).

This series combination of the 2 NMOS transistors pulls down the BL
tow
ards ground. We would like to have transistors sized
as close to minimum as possible, which
would result in a very slow discharge of the large bit capacitance. As the difference between the BL
and BL builds
up,

the sense amplifier is activated to acce
le
ra
te the reading process.


Initially upon the rise of
WL,

the intermediate node between these 2 NMOS
transistors Q, is pulled up
towards the precharge value of BL. This voltage rise of Q must stay low enough not to cause a su
b-
stantial current through the
M3
-
M4
, which in the worst case could flip the cells. It is hence necessary
to keep the resistance of M5 large than that of M1.


The boundary constraints on the device sizes can be derived by solving the below current equations.



which simplifies to

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whe
re CR

is called the
Cell Ratio

and is defined as

.


To keep the node voltage from rising above transistor threshold (of above 0.7V) the cell ratio must be
greater than 1.2V.


According to the de
si
gn criteria the size of the transistors we
re

chosen as

below
.


Transistor Sizing

Size of the Transistor

M2&M4

1.5um

M5&M6

3um

M1&M3

4.05um


3.2 Layout



Figure

5
-

Layout of 6T SRAM cell

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3.3 Schematic



Figure 6
-

Schematic

of 6T SRAM Cell


4. Word Pre
-
Charge


The word pre
-
charger is used to pull the b
it and bit bar lines to logic one during read. The word pre
charger

i
s created in such a way that it does not fight with NMOS in the back to back connected i
n-
ve
r
ters so that it

does not try to charge the output node connected to the back to back inverters
in
the case of reading. The

input to the word pre charger is given only when a read is to be done. Whe
n-
ever the read enable goes high,

the PMOS is off. So the pseudo NMOS style is avoided to remove the
sc
e
nario of static power dissipation.

The absolute log
ic “0” cannot be realized in the case of pseudo
NMOS style because of the always ON

PMOS, due to which the output cannot be pulled to a complete
logic “0”.




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4.1 Layout

& Schematic



Figure 7
-

Layout & Schematic of Pre
-
Charge


5. Write Driver


The w
rite driver is designed to write a new bit to a cell or overwrite an already existing value. The
write

driver has two input pins namely the write data bit and the write enable signal. Once the write
enable

signal goes high, the write data is pushed onto th
e appropriate cell. Note that, both the data
ad its

complement has to be written into the memory. This is ac
complished by using an inverter.

Also,
the write en
a
ble signal drives

two transmission gates. The write driver must be capable of writing a
clean vo
ltage value on the bit line.

There is a big parasitic capacitance seated on the bit line. So the
sizing is again based on the m
e
thod of

logical effort.





Figure 8
-

Layout of Write Driver



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Figure 9
-

Schematic of Write Driver



6. Entire Memory Desi
gn


All the components have been interconnected and the wiring has been done using M1, M2 and M3 metal layer.

M1 wires were used for horizontal wiring and M2 wire was used for vertical wiring. M3 wire was used only

in
the cases where it was unavoidable.



Figure 10
-

Schematic of 512 SRAM Grid

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Figure 11
-

Layout of 512 SRAM Grid



REFERENCES


[1]
Digital Integrated Circuits by Ja
n M. Rabaey, Anantha Cha
ndrakasan, and Borivoje Nikolic

[2]
SRAM Leakage Suppression by Minimizing Standby Supply Voltage (
Dep
t of EECS, University of
California at Berkeley
)
Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, and Jan R
a-
baey
.