Layout and Physical Verification

parkagendaElectronics - Devices

Nov 2, 2013 (4 years and 12 days ago)

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Lab 2


IL2227 VLSI Fundamentals


1


Layout and Physical Verification

In this exercise
you

practice layout

based on the Inverter that you created in the previous Lab
. Basic
functionality of the layout editor is

explained. Schematic driven
layout, metal interconnects
,

vias and
well contacts

are practiced.

You also learn to execute the Design
-
Rule
-
Checking (DRC), Layout
-
vs
-
Schematic, and Parasitic
-
Extraction using XRC.

1.

Virtuoso
Layout Editor

Start the layout editor

Start

up

the Virtuoso. Choose the schematic view of the inverter that created in the previous
exercise
from the Library Manager window (Fig. 1).


Figure 1.
Open the inverter schematic

Start the layout generation tool from schematic window by selecting th
e menu
Tool
-
> Design synthesis
-
> Layout XL.

The
first time you start the tool you are asked to create a new layout view

(Fig. 2).



Figure 2. Creating new layout view


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Then, the layout window is opened and the
Layer Select Window

(LSW) appears (Fig. 3). The LSW is
used to select which layer to display and edit. For example, to create wires in the Metal 1 drawing layer,
select ME1, drw.


Figure 3. Layer Select Window

Some useful features of the LSW are the AV NV AS NS buttons.
These buttons specify which layers in
the layout window can be viewed or selected.

AV
: All viewable


Make all layers visible


Use redraw or
CTRL
-
r

for this to take affect

NV:
None viewable


Make all layers except the one currently selected i
n the LSW invisible


Select other layers in LSW to make them visible as well


Middle
-
clicking a layer in the LSW toggles view on and off


Use redraw or CTRL
-
r for this to take affect

AS
: all selectable


allows you to select any layer



Pin layers and instance (subcells) selection controlled by Inst and Pin at top of window

NS
: none selectable


Turns off selection of layers (darkens layer in LSW window)


Right
-
clicking a layer in the LSW toggles select on and off



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Generate
Layout

When the layout editor is opened the first time the layout is empty.
The layout is basically done
by
instantiating the layout view of the cells from the design kit, and wiring them up. In order to instantiate
all of the

schematic
components in the l
ayout window select
Design
-
> Gen from Source

or
you can
instantiate each component separately by selecting it in the schematic window and place it in the layout
window using
Create
-
> Pick from Schematic
.

This brings out the layout Generation Form (Fig.
4).


Figure 4. Layout Generation Form

Make sure that IO pins are
symbolic type and placed on the text layer M1_T as shown in figure 4 and
press
Apply
.

Press OK to generate the layout (Fig. 5).


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Figure 5.

Generated layout

By default only the outline of the components are displayed.
To view all layers, select the
Options
-
>
Display

or press
e
.

Set the display stop level to
32

to view all layers of the components. In addition, in
this form change the
X/Y Snap Spacing

to
0.005
. Also change the
Snap Modes

to
anyAngle

which makes
it possibl
e to move the components freely (Fig. 6).


Figure 6. Display options

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Select
Options
-
> DRD Edit

and choose
Notify

for the
Interactive Mode

so that tool alerts you
automatically when violating
the design rules (Fig. 7).


Figure 7. Set the DRD options

Now, in the layout editor, you can see 4 pins and 2 transistors. Boundary layer is also visible (Fig.
8
).
Click on every component and press m to move it. Place all components within the boundary.

In order to
make the boundary non
-
selectable, do right
-
click on its layer prBoundary in LSW.


Figure
8
.
Lines indicate connection of pins when moving components.

Save your design by using the
Design → save

command from the menu bar. To prevent any unexpected
loss of data, save your work

regularly throughout the course of this laboratory exercise.


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Create interconnect

When the components are placed in the right place, you can create interconnect using metal
wires and
poly. Choose the appropriate layer in LSW and select
Create
-
> path
or press
p

to create connections.
You can also choose
Create
-
> Rectangle

to create a rectangle instead of a path.
The distance between
the components can be measured using
Windo
w
-
> Cerate Ruler
.

To connect the poly gate
s

of two transistors
,

choose
P01

from LSW,
and

connect the
m by creating a
path.
In order to interconnect between layers you need to create a VIA or contact. For instance, if you
want to create a VIA between the ga
te poly and
Metal1, use the
Create
-
> contact
or press
o
.

The size of
the via is fixed, but you can adjust the number of rows and columns. In order to create a low resistance
contact it is necessary to use an array of contacts.

Connect the drains of the tr
ansistors with Metal 1 and
locate one of the port rectangles on it to be labeled as the outport later. Fig.
9

shows details of a possible
layout around the inverter input and output. Note the port rectangles in the Metal 1 layer.


Figure
9
. Details of gate contact and I
n

and Out ports

Body and Substrate Connections

The drawing
in the Fig.
10

shows a sideview of a P
MOS

and N
MOS

put together.

outport

in
port

PMOS

NMOS

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Figure
10
. Sideview of a CMOS

The PMOS transistors are placed in a sepa
rate NWELL which has to be connected to VCC. For this
purpose, you should create a contact between ME1 and NWELL

(Fig.
1
1
)
.


Figure
1
1
. Connect
NWELL to the VCC

If the NWELL contact cannot be placed directly between the transistors it may be necessary to

extend
the NWELL by drawing for example an NWEL rectangle

(Fig. 1
2
)
.

In
continue,

connect the

Source of
the PMOS to the VCC.


Figure 1
2
. Connect Source and N
-
WELL of the PMOS to the VCC

VCC Pin

PMOS

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Similarly, you should connect the substrate to the GND pin by
creating a ME1 to PWELL contact (Fig.
1
3
).
What is the reason that NWell and Psubstrate should be connected to the VDD and GND
respectively
?............................................................................................................................
......................


Figure 1
3
.

Create a VIA to connect the substrate to GND


Figure 1
4
.
Connecting subst
rate to the GND pin

Add labels for pins

The final step in layout is creating labels for pins. This is done in order for the Layout Versus Schematic
(LVS) tool to recognize the pins in the layout. Labels are created as text in the metal layer where the
port

is located using the menu
Create
-
>Label
. This brings up the Create label form (Fig. 1
5
).

GND

Pin

NMOS

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Figure 1
5
.
Creating label for pins

The final inverter layout may look like Fig. 1
6
.

Save the final layout using
Design
-
>Save
.


Figure 1
6
. The final layout

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2.

Design
Check Rules (DRC)

When the layout is finished it needs to be checked for errors according to the process design rules. We
will use
Assura

to check the design.

In the folder which you run Cadence make a folder for DRC runs.



mkdir
LSI/LAB0/
DRCs

Remember to

erase the files in the temporary folder after finishing the DRC
.

In the layout window, s
elect
Assura
-
> Run

DRC from the menu.
In the run form you need to set the
correct switches and process options.

Fill in the DRC Run form to be exactly as Fig. 1
7
.

Select
“umc90nm_DRC”
as the
Technology

and “
Option13
” for
Rule Set
.



Figure 1
7
. DRC configuration form

By default the UMC design kit is configured to checks for all possible errors. Many errors, such as the
corner check, die seal ring etc. are only mean
ingful when performing the final top
-
level verification of
the complete circuit. On top
-
level it is also necessary to have sufficient metal and poly coverage. The
DRC checks for coverage by default. It is therefore convenient to filter out some of these wa
rnings in
the beginning. In the DRC configuration window, click the
Set Switches

button to configure which DRC
switches to use (Fig. 18).

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Figure 18. Set switches for DRC

Now, p
ress OK to start running
the
DRC.
A
Progress

window pops up and is visible as

long as the DRC
is running. By clicking the
Watch log file

(Fig. 19)
button you can watch the progress of the DRC. You
can review all of the errors in Error Layer Window (ELW) and highlight ea
ch of them in the layout
window. All spacing errors (between w
ires or other materials) have to be fixed. You can use
rulers

(press
k
)

to modify the layout. Rulers can be cleared using
shift + k
.

After modifying the layout, rerun
the DRC until all errors are captured.


Figure 19. Watch log file

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3
-

Layout Versus

Schematic (LVS)

When the layout is DRC clean, run the Layout Versus Schematic (LVS) check, to check that all wires
are correctly connected, no vias are missing, all ports are in place and that all
components

have the
correct value
s
.

Remember that due to
the bug in the tool/PDK, the pins are not always recognized correctly. To avoid
LVS problems, a simple method is to place labels with the name of the ports over the metal connecte
d to
that.

Invoke the
Assura LVS
run form (Fig.
20
) using the
Assura
-
>Run LVS

menu.

Configure the LVS for
correct process options in a similar way as the DRC and run the LVS.

The LVS can take a long time to
finish, watch the progress in the output log if necessary.
When the LVS is finished the LVS complete
window opens.


Figure
20
.

Assura LVS run form

Run LVS and if it asks to overwrite layout and source files, accept. The LVS debug window will appear
and you can examine the results and discrepancies between the netlist and layout. The LVS process
finishes when the schematic and la
yout match.

In the window a number of warnings are listed. These
can usually be ignored (Fig. 21).

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Figure 2
1
. LVS complete window

When the LVS is finish you can open the LVS debug form

(Fig. 22). Select an error and click the Open
Tool button. This brings up the correct LVS debug tool, for example the
Parameter Missmatch

tool.

Modify the layout or schematic and rerun the LVS until all errors are captured

(Fig. 23)
.


Figure 2
2
. LVS
debu
g form


Figure 2
3
. LVS
complete match

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4
-

Hierarchical Design

In this section, we will use the inverter cell containing schematic and the layout to construct a digital
buffer.
Create a new schematic cell view “digitalBuffer”. Use the inverter symbol to cre
ate a digital
buffer consisting of two cascaded inverters (Fig. 24).


Figure 24. Digital buffer using two cascaded inverters

Create a
layout view for this circuit. The final layout should look similar to Fig. 25.
Remember to label
the pins according to
their names in the schematic view.


Figure 25. Final layout of the digital buffer

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Rerun the DRC and LVS to verify that the complete circuit contains no errors.

Use the rulers to measure
the outline of the final buffer.

What is the final area of your design?..........................................................
……...........................................................................................................................
.................................
....

5
-

Parasitic Extraction

Open the Assura parasitic extraction run form (Fig. 11) using the menu
Assura
-
>Run RCX
in the layout
editor (Fig. 26). In the
extraction

tab of RCX run form (Fig. 2
6
), specify
RC

as the
extraction type
,
which
means the parasiti
c resistance (R) and capacitance (C) are extracted. You should also specify
VSS

as the
reference node
.
Then press
Apply

and
OK

to run the parasitic extraction.




Figure 26. Parasitic extraction form

Now, a new view
av_extracted

is generated in the
Library Manager
.
Open it, parasitic elements are
visible over the layout (Fig. 27).

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Figure 27. Parasitic elements of the
digital buffer

6
-

Simulating using the extracted view

By creating a symbol for the digital buffer and make a test bench, the final ci
rcuit using the extracted
view can be simulated and compared to the standard schematic.


Figure 28.
D
igital buffer test bench

Set the

characteristics of the pulse generator
as the below.

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t
r
= t
f

= 10p, Pulse width= 90p, Period= 190p

In the
A
nalog Design
Environment, set the stop time for the transient calculation to be 1ns. Run the
simulation to see the output

(B and C)

and input

(A)

voltages.

Measure and record the output (C) rise time and fall time using the crosshair markers. Rise time of the
output i
s defined as the time taken for the output to rise from 10% of the final value to 90% of the final
value………………………………………………………………………………………………………

Determine the pulse propagation delay for output signal B and C with reference start of delay time
measurement a
t the 50% level of the Low
-
to
-
High change of the input signal (A) respectively at the 50%
level of the High
-
to
-
Low change of the input signal.

Pulse propagation delay time for B:

t
pLH,B

=………………………………….. t
pHL,B
=……………………………………………

and the mean time del
ay value t
d,B
=(

t
pLH,B

+ t
pHL,B
) / 2 =……………………………………..

Pulse propagation delay time for C:

t
pLH,C

=………………………………….. t
pHL,C
=……………………………………………

and the mean time delay value t
d,C
=(

t
pLH,B
+ t
pHL,C
) / 2 =……………………………………..

Then, modify the
switch list

in the
Setup
-
> Environment
to use extracted view by inserting
av_extracted

before schematic

(Fig. 29)
. Change the
plotting mode

to
Append

and run the simulation and compare the
outputs.


Figure 29. Switch list setup to simulate parasitic extracted view

Calculate the mean time delay value for B and C again.
What is the difference between delays in the
case of schematic and extracted simulation?

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Pulse propagation delay time for B using av_extracted view:

t
pLH,B

=………………………………….. t
pHL,B
=…………………………………
…………

and the mean time delay value t
d,B
=(

t
pLH,B
+ t
pHL,B
) / 2 =……………………………………..

Pulse propagation delay time for C using av_extracted view:

t
pLH,C

=………………………………….. t
pHL,C
=……………………………………………

and the mean time delay value t
d,C
=(

t
pLH,B
+ t
pHL,C
) /

2 =……………………………………..

7
-

Power Calculation

Add a capacit
ive

load of
1
fF

to the output C. Plot the current of the capacitance. Measure the
peak
current values when the output changes the value.

The NMOS transistor peak current value I
dNMOS
…………………………………………………
.

The PMOS transistor peak current value I
dPMOS
…………………………………………………
.
.

Calculate the value of the electric charge Q which
passes

from the power source VDD to the lowest
potential VSS during one period of the input signal.

Q=………………………………………………………………………………………
…………...

How much power does the inverter consume in the stationary state?


P
s
=……………………………………………………………………………………………………

Calculate the switching power of the inverter? (P
d
= cfv
2
+ (I
PMOS_peak
*VDD*t
r
+

I
NMOS_peak
*VDD* t
f
)/T
)
)

……………………………………………
…………………………………………………………..

………………………………………………………………………………………………………..

How much is the total power consumption of the inverter? (P=P
s
+P
d
)
……………………………….

………………………………………………………………………………………………………….