FIELD EFFECT TRANSISTORS: Basic N Channel FET.

parkagendaElectronics - Devices

Nov 2, 2013 (3 years and 9 months ago)

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FIELD EFFECT TRANSISTORS: Basic N Channel FET.



JFET is short for 'Junction
-
Gate Field Effect Transistor' normally referred to as FETs.
FETs are controlled
by an electric field

as opposed to an electric current as is the case
for a bi
-
polar transistor.

The channel is made of n
-
type material and the gate p
-
type.

As the gate voltage is made more negative (gate to channel junction is reverse biased)
the depletion region widens. This is an area where positive holes are filled with negative
electrons, thereb
y removing the current carriers through cancellation.



As VGG is made more negative a point is reached when ID ceases to flow, known as
'pinch off'. By holding VGG at 0V, then current through the device can be controlled by
voltage VDD. Behaving as fixed

value resistor.

Also available are p
-
type FETs where the channel is made of p type semiconductor
material. Voltages for this device are simply a reversal of those for the n
-
type.


MOSFET Transistor.


MOSFET stands for Metal
-
Oxide
-
Semiconductor Field Effec
t Transistor. The n channel
is normally made very thin and insulated from the gate electrode forming a small
capacitor.

On connecting VDD between the channel and the substrate it forms a PN
junction which is reverse biased. Current can then flow between t
he 'source' and 'drain'
through the channel which is n
-
type material.


Making the gate positive with respect to the source and the effective width of the channel
is made greater
(enhanced
) so more current flows.

This is called the 'enhancement'
mode.



B
y making the gate negative with respect to the source and its in 'depletion' mode and
the effective width of the channel is reduced (
depleted)

thereby restricting current flow.




FET Negative Biasing



Increasing
Negative
Bias




Automatic Bias




Th
e FET can be DC biased automatically
. Ie bias is not provided by a cell

RS provides the bias voltage to
make
the source more positive than the gate.

Because the source is at a higher potential the gate will effectively be negative


Owing to the very high
input impedance of the FET there will be negligible current
flowing into the gate.


T
here is a reduction in signal gain as the source resistor generates negative feedback
which opposes the gate voltage change. The addition of the source de
-
coupling
capacit
or CS provides a low impedance path to the AC signal, thereby
bypassing

RS
.

This restores the gain to its original level for the AC component.



Depletion / Enhancement MOSFET


.


The Depletion / Enhancement MOSFET has a standing or quiescent current flo
wing
determined by the value of RL when 0V are applied to the gate.

Increasing or decreasing this bias (gate to source voltage VGS) above and below zero
volts will cause this quiescent DC current to change.

Depletion mode current reduces ID whereas in the
enhancement mode the gate voltage
will increase the amount of ID flowing.

The application of an AC signal voltage to the gate causes ID to swing about the
quiescent current operating point. When VGS = 0V positive half cycles increase drain
current (enhance
ment), negative half cycles reduce it (depletion).


Enhancement MOSFET.