Chapter 1 The Metal-Oxide Semiconductor

parkagendaElectronics - Devices

Nov 2, 2013 (3 years and 11 months ago)

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1
-
1

Chapter 1

The Metal
-
Oxide Semiconductor
Field Effect Transistors

Section 1.1

An Introduction
of
MOSFET

In this lecture notes, we shall use metal
-
oxide semiconductor field effect transistors
(MOSFET) as our conducting devices. We shall
not

discuss the electronics
pro
perties of these transistors. We merely introduce their functions.



There are two types of MOSFET

s: enhancement type and depletion type.
For each type, there are again two types: N
-
type and P
-
type, as shown in Table
1.1
-
1.


Table 1.
1
-
1

Type of transi
stors.


Ty p e


C h a n n e l

En h a n c e me n t

De p l e t i o n

N

En h a n c e me n t t y p e N MO S

De p l e t i o n t y p e N MO S

P

En h a n c e me n t t y p e P MO S

De p l e t i o n t y p e P MO S



F o r e a c h t y p e, we u s e t h e
s y mb o l s s h o wn i n F i g. 1.1
-
1.


1
-
2


Fig. 1.1
-
1


Enhancement a
nd depletion type transistors.



As shown in Fig. 1.1
-
1, there are three terminals for each transistor, namely drain
(D), source (S) and gate (G).
The terminal with an arrow sign is the source.
For all
of these transistors, there is no gate current. In
other words, there is only current
going through drain and source as shown in Fig. 1.1
-
2. The reader should note
that
the direction of the current

follows the arrow sign of the sources
. In NMOS
transistors, the current flows from drain to source while in

PMOS transistors, it flows
from source to drain.


1
-
3


Fig. 1.1
-
2
. Current directions in different type of transistors.




There is actually little difference among the
enhancement and depletion
transistors. Throughout of this le
cture notes, we shall use enhancement type
transistors.

To start with, we shall discuss

the NMOS transistors.



As shown in Fig. 1.1
-
3, there are three important p
arameters of an NMOS
transistor
,

namely

and
.

It should be reminded here that in an
NMOS transistor, the current flows from drain to source and there is no gate current.


Fig. 1.
1
-
3


Voltage and current in a NMOS transistor.



1
-
4


Suppose we have a fixed
, the

curve is as shown in Fig. 1.1
-
4.


Fig. 1.1
-
4


An I
-
V curve of an NMOS transistor.



At the very beginning, as

first increases,

increases linear
ly. After

reaches a certain point,

stops increasing and almost remains a constant.
Therefore, we say that there are two regions as indicated in Fig. 1.1
-
4. Region I is
called the triode, or ohmic, region a
nd Region II is called the saturation, or constant
current, region. For Region I, the transistor almost
behaves

as a resistor because
for
a resistor, the current increases linearly with respect to the voltage across it. That is
why this region is also ca
lled the ohmic region.



For different

s, there are different

curve
s, as shown in Fig.
1.1
-
5
. It can be seen that the higher

is, the higher

is.

This phenome
non
will be explained in the next section.

F
ig.
1.1
-
5


I
-
V curve of an NMOS transistor for different
V
GS

s.



1
-
5

Section 1.2

T
he
Current in the Saturation Region

In this section, we present
a
formula for the current in the saturation region.

T
here exists a certain threshold for
. This threshold is called
. The
transistor is cutoff if
.

is usually quite small. If
, the
transi
stor is
in the

triode region;
otherwise
, it is in the saturation region, as shown in
Fig.

1.2
-
1.

Fig. 1.2
-
1

The threshold voltage
V
t

of an NMOS transistor.



In the triode region, obviously,

is a func
tion of both

and

. The
relationship is given by the following formula:





(1.2
-
1
)


where

is a constant and

and

are the width

and length

of the gate
respectively. The parameter

is given by the integrated circuit manufacturing
process model. At the boundary between the triode and saturation regions, we have





(1.2
-
2)


and

(1.2
-
3)



Although Equation (1.2
-
3) is derived by assuming
, it is valid for

1
-
6


because once
, the transistor will be in the saturation
region

and
will be constant in this region
.



will now be independent of

and is only a function of
. Thus, we
may easily see that Equation (1.2
-
3) holds if
. Equation (1.2
-
3) is
illustrated in Fig. 1.2
-
2.

As will be seen later
,

will not be too large, except in
some rare cases. Thus,

is usually not very large either. Note that a large

will cause a very large power consumption.


Fig. 1.2
-
2
.

The relationship between

and
.



Fig. 1.2
-
2 can be quite misleading because it somehow gives the reader the
impression that

grows with respect to

without any limit. In practice, this
is not the case, as explained in the next section.


1
-
7

Section 1.3

The Behavior of
I
DS

with a Load

for NMOS
Transistors

Consider Fig. 1.3
-
1 where a load is connected to the drain of the NMOS transistor and
a power supply

is connected to the load

and a bias voltage

is
provid
ed

at
the gate
.


Fig. 1.3
-
1
. An NMOS transistor with a load.



From the circuit

shown

in Fig. 1.3
-
1, we have the following equation:



. (1.3
-
1)

In Equation (1.3
-
1),

there are two variables, namely

and
. But there
is only one equation. Therefore, we cannot determine

from this equation only.
But, we may draw a straight line to illustrate Equation

(1.3
-
1) as in Fig. 1.3
-
2.


Fig. 1.3
-
2
. The
load line.


1
-
8



What is missing in Equation (1.3
-
1) is the voltage
. Note that current

is heavily influenced by
,
as illustrated in Fig. 1.1
-
4

and Fig. 1.1
-
5
. Let us
combine Fig. 1.1
-
4 and Fig. 1.3
-
2 into Fig. 1.3
-
3.



Fig. 1.3
-
3
. The determination of

and
.



Fig. 1.3
-
3 shows how we can dete
rmine the value of

by finding the
intersection of the load line and the
I
-
V

curve of the transistor.

From Fig. 1.3
-
3, we
know that we can not only determine the value of
, but also that of
.
Note
that the
I
-
V

curve is fixed once

is given. But the value of

plays a critical
role now because it
determines

the slope of the load line
.

Different

s will give
different loa
d lines and
thus

different

s

and

s
.



Let us consider the case where

changes. There will be a family of
I
-
V

curves.


1
-
9

Case 1:

is small.


This case is illus
trated in Fig. 1.3
-
4.


Fig. 1.3
-
4
. Voltage and current of an NMOS circuit with a small
.


In this case,
as
V
GS

increases
,

we
should

note two phenomena: (1)

rises
sharply. (2)

falls
a little
.

We would like to point out here that

is more
important than

as it is usually the output of the circuit. We shall discuss this in
detail in the next chapter.
At present
, the reader may simply note that when

is small,

will not change much as

changes.



1
-
10

Case 2:

is
moderate
.



The case is illustrated in Fig. 1.3
-
5.

Fig. 1.3
-
5
. Voltage and current of an NMOS circuit with a moderate
.



We note that the changes of both

and

are moderate

as
V
GS

increases
.
In other words, none of them
changes sharply.



1
-
11

Case 3:


is
large
.



The case is illustrated in Fig. 1.3
-
6.

Fig. 1.
3
-
6
. Voltage and current of an NMOS circuit with a large
.



In this case, we note that

rises
a little

and

falls sharply

as
V
GS

increases
. Again, we shall emphasize here that the rate of change of

is rather
significant. In general, we would like

to ch
ange drastically.



Fig. 1.3
-
7 summarizes the three cases.


1
-
12


Fig. 1.3
-
7
.

versus

of an NMOS transistor circuit for three different loads.




is called the bia
s voltage. Its
significance

will be explained later.

is
called the operating point voltage, or simply operating point. Fig. 1.3
-
8 illustrates
how different operating points are produced. Note that it takes both

and

to produce an operating point.


1
-
13

Fig. 1.3
-
8
. The operati
ng

points.


1
-
14

Section 1.4

The PMOS Transistors

A typical PMOS transistor is now shown in Fig. 1.4
-
1.


Fig. 1.4
-
1
. A PMOS

transistor.



For a PMOS transistor, the
controlling

(biasing) voltage is
, as opposed to

in an NMOS transistor. The higher

is, the higher

will become.
Note t
hat in a PMOS transistor, the current flows from source to drain which is
different from the case in an NMOS transistor.. Fig. 1.4
-
2 illustrates a family of
I
-
V
curves for PMOS transistors.


Fig. 1.4
-
2
. I
-
V curve for a PMOS t
ransistor.



In Fig. 1.4
-
3, we show the difference between the NMOS circuits and the PMOS
circuits.


1
-
15


Fig. 1.4
-
3

NMOS and PMOS transistor circuits


For the PMOS circuit, we have
the following equation:





(1.4
-
1)



We use the
I
-
V

curves in Fig. 1.4
-
2. First, we plot
-

vs

as in Fig.
1.4
-
4.


Fig. 1.4
-
4
. I
-
V curve for

for

a PMOS transistor.



We then plot

as in Fig. 1.4
-
5.



1
-
16

Fig. 1.4
-
5


I
-
V curve for

for a PMOS transistor.



Finally, we add the load line which is

to Fig. 1.4
-
5 to produce Fig.
1.4
-
6.


Fig. 1.4
-
6

I
-
V curves and a load line for a PMOS transistor circuit



Let us compare the two circuits shown in Fig. 1.4
-
7.



Fig. 1.4
-
7
. An NMOS transistor
circuit

and a

PMOS transistor with the same
.




For NMOS transistors where S is grounded,

is
determined

by

and for PMOS transistors where the source is connected to
,

is
determined by
. But, in

this PMOS case,
. Since

is a
constant, we conclude that for PMOS transistors,

is
also
determined by
.
Thus, in both cases, we may simply say that

is the input

voltage
,

a
s shown in
Fig. 1.4
-
7.



It can be noted that for an NMOS transistor, the higher the current going through
it, the lower
. The situation is just the opposite for PMOS transistors. The
higher the current, the h
igher
. They are complementary to each other, a very

1
-
17

useful property which will be discussed later.



For NMOS transistors, if

increases, the current increases. Thus for these
transistors, the increase of

will increase the current and decrease the output
voltage
.


For PMOS transistors, if

increases,

decreases and
the
current decreases. However, it can be easily seen that this will in turn decrease the
output
.
Thus we conclude that for both NMOS and PMOS transistors, the
increase of

will decrease the output voltage
. Similarly, a decrease of

will increase the output voltage

for both NMOS and PMOS transistors.
This is another important property o
f these transistors.


1
-
18

Section 1.5

The Depletion Type MOSFET Transistors

The depletion type MOSFET transistors are quite similar to the enhancement type
MOSFET transistors. The only difference is the
polarity

of
.

is pos
itive for
enhancement type NMOS transistors, but negative for depletion type NMOS
transistors. It is negative for
enhancement type PMOS transistors, but positive for
depletion type PMOS transistors. Fig. 1.5
-
1 illustrates this.


Fig. 1.5
-
1
.

versus

for depletion type and enhancement type transistor
s
.

Section 1.6

Experiments

In this section, we show several experiments using the SPICE circuit simulation
system. For each circuit and for every

experiment, we
shall

give the SPICE program
written for the purpose. We cannot
explain the details of the SPICE program
grammatical rules. The reader may consult any SPICE manual. The VLSI model
for the transistors is mm0355v.1

TT.



In the above secti
ons, we did not mention a term, namely, the body of a transistor.
We
shall

not
elaborate

the physical meaning of the body. Throughout the
experiments, for NMOS transistors, the body is connected to the low power supply
while for the PMOS transistors, the

body is connected to the high power supply.


Experiment 1.6
-
1 I
-
V Curves


The purpose of this experiment is to show a family of I
-
V curves.
The power
supply voltage

is set at 3.3V.
Fig. 1.6
-
1 shows the circuit.
Table 1.6
-
1 show
s
the SPICE program and Fig. 1.6
-
2

shows the simulation result.


1
-
19


Fig. 1.6
-
1
. The circuit for Experiment 1.6
-
1.


Table 1.6
-
1
.
P
rogram for Experiment 1.6
-
1.

filename

.protect

.lib 'c:
\
mm0355v.l' TT

.unprotect

.op

.options nomod

post


VDD

1

0

3.3v

R1 1 2 100k

V2 2 0 0v


.param

W1=5u

M1

2

3

0

0


+nch L=0.35u

W='W1' m=1


+AD='0.95u*W1' PD='2*(0.95u+W1)'

+AS='0.95u*W1' PS='2*(0.95u+W1)'


VGS

3

0

0v

.DC V2 0 3.3v 0.1v SWEEP VGS 0.1v 3v 0.25v

.PROB
E

I(M1)

.end



1
-
20


Fig. 1.6
-
2
. I
-
V curve for the circuit in Fig 1.6
-
1.



Experiment 1.6
-
2 A Single I
-
V Curve and the Load Line



In this experiment, we shall show the intersection of a load line and a single I
-
V
curve. The circuit is biased at 0.65V. T
he load is 100K and the power supply
voltage

is set at 3.3V

as shown in Fig. 1.6
-
3
.

Fig. 1.6
-
4

shows the result.


Fig. 1.6
-
3
. The circuit for Experiment 1.6
-
2.



V
GS

V
D
S

I
D
S


1
-
21



Table 1.6
-
2
.
P
rogram for Experiment

1.6
-
2.

filename

.protect

.lib 'c:
\
mm0355v.l' TT

.unprotect

.op

.options nomod post


VDD

1


0


3.3 v

R1

1 2 1 0 0 k

V2 2 0 0 v


.p a r a m

W1 = 5 u

M1

2

3

0

0


+nch L=0.35u

W='W1' m=1


+AD='0.95u*W1' PD='2*(0.95u+W1)'

+AS='0.9
5u*W1' PS='2*(0.95u+W1)'


VGS

3

0

0.65v

.DC V2 0 3.3v 0.1v

.PROBE I(R1) I(M1)

.end



1
-
22


Fig. 1.6
-
4
. I
-
V curve and the load line for Experiment 1.6
-
2.


Experiment 1.6
-
3 The Operating Point with the Same
V
GS

and a Smaller
R
L
.



In this experiment, we use

the same bias voltage

, but a smaller load of
50K, as shown in Fig. 1.6
-
5. The program is in Table 1.6
-
3 and the simulation result
is shown in Fig. 1.6
-
6. As can be seen, we have a higher
. This may not be

so
good as we shall see later in the next chapters.


Fig. 1.6
-
5
. The circuit for Experiment 1.6
-
3.

I
DS

R
1
=100k


1
-
23


Table 1.6
-
3
.
P
rogram for Experiment 1.6
-
3.

filename

.protect

.lib 'c:
\
mm0355v.l' TT

.unprotect

.op

.options nomod post


VDD

1

0

3.3v

R1 1 2 50k

V2 2 0 0v


.param

W1=5u

M1

2

3

0

0


+nch L=0.35u

W='W1' m=1


+AD='0.95u*W1' PD='2*(0.95u+W1)'

+AS='0.95u*W1' PS='2*(0.95u+W1)'


VGS

3

0

0.65v

.DC V2 0 3.3v 0.1v

.PROBE I(R1) I(M1)

.end



1
-
24


Fig. 1.6
-
6
. I
-
V curve and the load line for Experiment 1.6
-
3.


Experiment 1.6
-
4
I
DS
-
V
GS

with Almost No Load



In this experiment, we set the load to be very small so that

can grow indefinitely
with

The circuit, th
e program and the experimenting result are shown below.


Fig. 1.6
-
7
. The circuit for Experiment 1.6
-
4.



I
DS

V
DS

R
1

= 50k


1
-
25

Table 1.6
-
4
.
P
rogram for Experiment 1.6
-
4.

filename

.protect

.lib 'c:
\
mm0355v.l' TT

.unprotect

.op

.options nomod post


VDD

1

0

3.3v

R1 1 2 0.01k



.param

W1=5u

M1

2

3

0

0


+nch L=0.35u

W='W1' m=1


+AD='0.95u*W1' PD='2*(0.95u+W1)'

+AS='0.95u*W1' PS='2*(0.95u+W1)'


VGS

3

0

0v

.DC VGS 0 3.3v 0.1v

.PROBE

I(M1)

.end




1
-
26


Fig. 1.6
-
8
.

versus

for Experiment 1.6
-
4.


Experiment 1.6
-
5
I
DS

and
V
DS

versus
V
GS

with a Relatively Large Load



We use a load of 100K. Now,

can not grow indefinitely with

The
circuit, the pr
ogram and the experimental results are shown as below. As can be
seen, the

quickly becomes a constant because of the load. Similarly, the
simulation also shows that

quickly drops
to 0. Note that we denote

to be
.


Fig. 1.6
-
9
. The circuit for Experiment 1.6
-
5.

I
DS

V
G
S

R
1

=
0.
0
1
k


1
-
27


Table 1.6
-
5
.
P
rogram for Experiment 1.6
-
5.

filename

.protect

.lib 'c:
\
mm0355v.l' TT

.unprotect

.op

.options nomod post


VD
D

1

0

3.3v

R1 1 2 100k


.param

W1=5u

M1

2

3

0

0


+nch L=0.35u

W='W1' m=1


+AD='0.95u*W1' PD='2*(0.95u+W1)'

+AS='0.95u*W1' PS='2*(0.95u+W1)'


VGS

3

0

0v

.DC VGS 0 3.3v 0.1v

.PROBE I(M1)

.end




1
-
28


Fig. 1.6
-
10
.

and
versus

for Experiment 1.6
-
5.


Experiment 1.6
-
6
V
DS
/
V
GS

Relationship with Different Loads



In this experiment, we tested the
V
DS
/
V
GS

relationship for small, moderate and
very large loads. It can be
seen that for

very small load,
V
DS

changes very slowly
with
respect

to
V
GS
. For
R
1
=100K, there is an appropriate
V
GS
, namely
V
GS
=0.65V.
But, for
R
1
=10000K,
V
GS

must be smaller than 0.5V. But
V
t
=0.5V. If
V
GS

is smaller
than 0.5V, the transistor is virtu
ally cutoff. An examination of the current for
R
1
=10000K shows that
it

is equal to 330na, which indicates that the transistor is
virtually cutoff.



The circuit is in Fig. 1.6
-
11.
The programs are in Table 1.6
-
6 to Table 1.6
-
9.
The results are in Fig. 1
.6
-
1
2

to Fig. 1.6
-
1
6
.



V
DS

V
G
S

I
D
S

R
1

=
10
0k



1
-
29


F
ig1.6
-
11. The circuit for Experiment 1.6
-
6.


Table
1.6
-
6
.
SPICE program for Experiment 1.6
-
6 with
R
1
=0.1k
.



example1



.protect



.lib 'C:
\
model
\
tsmc
\
MIXED035
\
mm0355v.l' TT



.unprotect



.op



.options nomod po
st



VDD

1

0

3.3v



R1 1 2 0.1k



.param

W1=5u



M1

2

3

0

0




+nch L=0.35u

W='W1' m=1




+AD='0.95u*W1' PD='2*(0.95u+W1)'



+AS='0.95u*W1' PS='2*(0.95u+W1)'



VGS

3

0

0v



.DC VGS 0 3.3v 0.1v



.PROBE I(M1)



.end




1
-
30


Fig
.

1.6
-
1
2
.

and
versus

with
=0.1k
for Experiment 1.6
-
6
.


Table 1.6
-
7
.
SPICE program for Experiment 1.6
-
6 with
R
1
=10k
.



example2



.protect



.lib 'C:
\
model
\
tsmc
\
MIXED
035
\
mm0355v.l' TT



.unprotect



.op



.options nomod post




VDD


1

0

3.3v



R1 1 2 10k




.param

W1=5u



M1

2

3

0

0




+nch L=0.35u

W='W1' m=1




+AD='0.95u*W1' PD='2*(0.95u+W1)'



+AS='0.95u*W1' PS='2*(0.95u+W1)'




VGS

3

0

0v



.DC VGS 0 3.3v 0.1v



.PROBE I
(M1)



.end

I
DS

V
ou
t

V
GS

R
1
=0.1K

V
GS

V
D
S


1
-
31


Fig
.

1.6
-
1
3
.

and
versus

with
=10k for Experiment 1.6
-
6.


Table 1.6
-
8
.
SPICE program for Experiment 1.6
-
6 with
R
1
=100k
.



example3



.protect



.lib 'C:
\
model
\
tsmc
\
MIXED035
\
mm0355v.l' TT



.unprotect



.op



.options nomod post




VDD

1

0

3.3v



R1 1 2 100k




.param

W1=5u



M1

2

3

0

0




+nch L=0.35u

W='W1' m=1




+AD='0.95u*W1' PD='2*(0.95u+W1)'



+AS='0.95u*W1' PS='2*(0.
95u+W1)'

I
DS

V
out

V
GS

R
1
=10K

V
D
S


1
-
32




VGS

3

0

0v



.DC VGS 0 3.3v 0.1v



.PROBE I(M1)



.end






Fig
.

1.6
-
1
4
.

and
versus

with
=100k for Experiment 1.6
-
6.


Table 1.6
-
9
.
SPICE program for Experiment 1.6
-
6 with
R
1
=10000k
.



example4



.protect



.lib 'C:
\
model
\
tsmc
\
MIXED035
\
mm0355v.l' TT



.unprotect



.op



.options nomod post




VDD

1

0

3.3v

I
DS

V
out

V
GS

R
1
=
100
K

V
GS

V
D
S


1
-
33



R1 1 2 10000k




.param

W1=5u



M1

2

3

0

0




+nch L=0.35u

W='W1' m=1




+AD='0.95u*W1' PD='2*(0.95u+W1)'



+AS='0.95u*W1' PS='2*(0.95u+W1)'




VGS

3

0

0v



.DC VGS 0 3.3v 0.1v



.PROBE I(M1)



.end




Fig
.

1.6
-
1
5
.

and
versus

with
=10000k for Experiment 1.6
-
6.


V
out

V
GS

V
D
S

I
DS

R
L
=
100
00
K


1
-
34


Fig
.

1.6
-
1
6
.

and
versus

with
=0.1k, 100k, 10k and 10000k for
Experiment 1.6
-
6.


Experiment 1.6
-
7 An
E
xperiment on a PMOS Circuit



In this experiment, we try to obtain I
-
V curves and load lines for a PMOS
transistor
circuit
.

The circuit is shown in Fig. 1.6
-
17.

The program is in Table
1.6
-
10 and the result is in
Fig. 1.6
-
18.



Fig. 1.6
-
17 A PMOS circuit for Experiment 1.6
-
7

R
1
=0.1k

R
1
=10k

R
1
=100k

R
1
=10000k

V
GS

V
DS

V
GS


1
-
35



Table 1.6
-
10 Program for Experiment 1.6
-
7

PMOS

.PROTECT

.OPTION POST

.LIB 'C:
\
model
\
tsmc
\
MIXED035
\
mm0355v.l' TT

.UNPROTECT

.op


VDD

1

0

3.3v


M1

2

3

1_1

1_1

PCH

W=5u

L=0.35u



VG


3

0

0.7 v

RL


2

0

2 k

Vo u t


2

0

0 v

Rd m1

1

1 _ 1

0


.DC Vo u t 0 3.3 v 0.1 v

.P RO BE I ( Rd m1 ) I ( RL)

.e n d




I n F i g. 1.6
-
7, t h e r e i s a r e s i s t o r
.
T
h e r e a d e r ma y wo n d e r w h y we n e e d
s u c h a r e s i s t o r. T h i s r e s i s t o r i
s t h e r e b e c a u s e we wa n t t o k n o w t h e v a l u e o f

i n
t h e P MO S t r a n s i t o r. B u t t h e S P I C E p r o g r a m i n s i s t s t h a t a l l c u r r e n t s i n a t r a n s i s t o r,
b e i t a n N MO S o r a P MO S, i s
. T h e r e f o r e i f we p r o b e t h e P MO S t r a n s i s t o r
d i
r e c t l y, we w i l l s e e n e g a t i v e c u r r e n t s b e c a u s e a f t e r a l l, c u r r e n t i n a P MO S i s f r o m
s o u r c e t o d r a i n. I f w e h a v e a r e s i s t o r w i t h n o v a l u e t h e r e, i t w i l l i n c l u e n c e t h e
b e h a v i o r o f t h e c i r c u i t. B u t i t w i l l a l l o w u s t o me a s u r e t h e c u r r e n t b y p r o b i n g t h e
c u r r e
n t i n t h e r e s i s t o r


1
-
36


Fig. 1.6
-
18 The I
-
V curve and the load line of the PMOS circuit in Fig.
1.6
-
17


Experiment 1.6
-
8

An
E
xperiment
of
I
-
V C
urves

on a PMOS Circuit



In this experiment, we try to show a family of I
-
V curves and load lines for a
PMOS tran
sistor
circuit
. The circuit is shown in Fig. 1.6
-
19. Table 1.6
-
11 shows
the SPICE program and Fig. 1.6
-
20 shows the simulation result.



Fig. 1.6
-
19 A PMOS circuit for Experiment 1.6
-
8


1
-
37


Table 1.6
-
11 Program for Experiment 1
.6
-
8

PMOS

.PROTECT

.OPTION POST

.LIB 'C:
\
model
\
tsmc
\
MIXED035
\
mm0355v.l' TT

.UNPROTECT

.op


VDD

1

0

3.3v


M1

2

3

1_1

1_1

PCH

W=5u

L=0.35u



VG


3

0

0 v

RL


2

0

2 k

Vo u t


2

0

0 v

Rd m1

1

1 _ 1

0


.DC Vo u t 0 3.3 v 0.1 v S WEEP VG 0 3.3 v 0.2 5 v

.P RO BE I ( Rd m1 ) I ( R
L)

.end




1
-
38


Fig. 1.6
-
20. A family of I
-
V curves and load lines for the circuit in Fig 1.6
-
19.


Experiment 1.6
-
9 A PMOS Circuit

Input/Output Curve


In this experiment, we plot an input/output curve of a PMOS circuit. The circuit is
shown in Fig. 1.6
-
19.

The SPICE program is in Table 1.6
-
11 and the result is in Fig.
1.6
-
20.


Fig. 1.6
-
19

A PMOS circuit


1
-
39


Table 6
-
11 Program for Experiment 1.6
-
8

.protect

.lib 'c:
\
mm0355v.l' TT

.unprotect

.op

.options nomod post


VDD

1

0

3.3v


M1

2

3

1_1

1_1

PCH

W=5u

L=0.35u



VG

3

0

0v

RL

2

0

100k

Rdm1

1

1_1

0


.DC VG 0 3.3v 0.1v

.end




Fig. 16.
-
20 Input/output urve of the PMOS circuit for Experiment 1.6
-
8

V
out
2

V
G


1
-
40


Section 1.7
Exercise 1

1.

Explain the current directions f
or NMOS and PMOS transistors.

2.

Draw a curve to explain the triode region and saturation region of an NMOS
transistor. Why is the triode region also called the ohmic region? Why is the
other region called the saturation region?

3.

What condition separates the

triode region and the saturation region?

4.

Derive the formula of

vs

in the saturation region. Note that

is
independent of
, which is expected in the saturation r
egion.

5.

Consider the following circuit

in Fig. 1.7
-
1
.


Fig. 1.7
-
1 A circuit for Problem 5 of Exercise 1


(a)

Give the formula relating

and
.

(b)

Explain how

and

are determined.

6.

In the above circuit, plot the curves relating and
=

for

small,

moderate and

large.

7.

Consider the
fol
lowing PMOS transistor below in Fig. 1.7
-
2



Fig. 1.7
-
2 A PMOS
circuit

for Problem 7 of Exercise 1

V
G


1
-
41


(a)

Give the equation describing the relationship between

and
.

(b)

Give the relations
hip between

and
.

(c)

Draw a diagram relating

and

for different
.

(d)

Explain how

and

are determin
ed.

8.

Consider the following circuits

in Fig. 1.7
-
3
. For both circuits,

decreases
as

increases. Explain.


Fig. 1.7
-
3 NMOS and PMOS circuits for Problem 8 of Exercise 1


9. We of
ten say that the gate bias voltage

can be neither too small, nor too
large. In other words, it has to be appropriate. Explain.