P5.1.
For each problem, restate each Boolean equation into a form such that it can be translated
into the p and n

complex of a CMOS gate.
a.
b.
c.
P5.2.
P5.3.
First, convert the equation into
its p and n

complex.
P5.4.
The truth table is given below in terms of voltages. The function is
A
B
F
0
0
Vdd
0
V
DD
0
V
DD
0
0
V
DD
V
DD
0
The worse case
V
OH
is
V
DD
and the worse case
V
OL
is 0V.
P5.5.
The fir
st circuit is a NOR gate while the second is a NAND gate. The
V
OL
and
V
OH
calculated are for the worst

case scenario. To find this, assume only one transistor turns
on, this just reduces to a pseudo

NMOS/PMOS inverter, so the other transistors are not
impo
rtant.
a.
The
V
OL
for the pseudo

NMOS (in 0.18
μm) is:
Since the minimum width is 2
λ
, we make that the width.
The
V
OH
for the pseudo

PMOS (in 0.18μm) is:
The pseudo

PM
OS circuit will have bigger devices than the pseudo

NMOS.
P5.6.
The steps to solving this question are the same as the pseudo

NMOS question in Chapter
4.
a.
For
V
OH
, recognize that
for operation so the output can only be as high as
. Since
, body effect must be taken into account and the full equation
is:
Iteration produces V
OH
=0.73V.
b.
For
V
OL
, we must first recognize that the worst

case
V
OL
occurs when on
ly one of the
pull

down transistors is on. Next we identify the regions of operation of the
transistors. In this case, the pull

up transistor is always in saturation and the pull

down is most likely in the linear region since it will have a high input (hig
h
V
GS
) and
a low output (low
V
DS
). Then, we equate the two currents together and solve for
V
OL
:
Using a programmable calculator or a spreadsheet program,
V
OL
= 0.205V.
The dc current with the output low is:
The power with the output low is:
P5.7.
See Example 5.2 which is based on the NAND gate. This question is the same except that
it addresses the NOR gate.
With both inputs tied together,
In the SPICE solution, the reason why the results vary for input A and B is due to body

effect.
P5.8.
The solution is shown below. Notice that there is no relevance with the lengths and
widths of the transistors when i
t comes to
V
OH
, although they the do matter when
calculating
V
OL
.
P5.9.
For
t
PLH
, we need to size the pull

up PMOS appropriately.
For
V
OL
:
P5.10.
The circuit is shown below:
Because the number of transistors in series is more than one, we must multiply the widths
by the appropriate number. Here, all the NMOS transistors will have a width of 54
λ
. The
PMOS transistors will have widths of 126
λ
and 190
λ
, respectively.
P5.11.
We estimate the dc power and dynamic switching power for this problem.
a.
The circuit’s dc power can be computed by computing the dc current when the output
is low. This is given by I
D
S
=550uA/um x 0.1um=55uA. Then P
DC
=66uW when the
output is low.
b.
Its dynamic power can be calculated by simply using the equation
.
Therefore, P
dyn
=(50fF)(V
DD

V
TN
)(V
DD
)(100MHz)=4.4uW.
P5.12.
The pseudo

NMOS inverter has static current whe
n the output is low. We can estimate it
as:
Then the average static power is P
stat
=(25.6uA)(1.2)/2 =15.4uW.
The dynamic power is
=(50fF)(1.2)(1.1)f
avg
assuming that V
OL
is
0.1V.
For the CMOS inverter,
the static power is almost zero: P
stat
=I
sub
V
DD
. It is far less than
the pseudo

NMOS case. The dynamic power
=(50fF)(1.2)
2
f
avg
is
slightly larger than the pseudo

NMOS case.
P5.13.
Model development to compute
sc
.
P5.14.
The energy delivered
by the voltage source is:
As can be seen, only half the energy is stored in the capacitor. The other half was
dissipated as heat through the resistor.
P5.15.
The average dynamic power does not depend on temperature if the frequency s
tays the
same. However, the short

circuit current will increase as temperature increases. In
addition, the subthreshold current increases as temperature increases. So the overall
power dissipation will be higher.
P5.16.
The circuit is shown below. The delay shoul
d incorporate both Q and Qb settling in
400ps. All NMOS and PMOS devices are the same size in both NAND gates.
P5.17.
The small glitch in J propagates through the flop even though it is small.
This is due to
the fact that the JK

flop of Figure 5.20 has the 1’s catching problem.
P5.18.
The small glitch in J does not propagate through the flop since the edge

triggered
configuration does not have a 1’s catching problem.
P5.19.
The positive

edge triggered FF
is as follows:
(a) With CK=D=0 and S=R=1, the outputs are
Gate
Signal
1
0
2
1
3
1
4
1
5
1
6
0
(b) Now CK=0
Gate
Signal
1
0
2
1
3
0
4
1
5
0
6
1
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