Implementing Fast Image Processing Pipelines in a Codesign Environment

pancakesnightmuteAI and Robotics

Nov 5, 2013 (3 years and 9 months ago)

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Implementing Fast Image Processing
Pipelines in a Codesign Environment

Accelerate image processing tasks through efficient use of FPGAs.

Combine already designed components at runtime to implement
series of transformations

Heather Quinn
, Dr. Miriam Leeser

Dr. Laurie Smith King

Northeastern University




College of the Holy Cross

Start App

HW Init

Send Data

Median

Repgm

Edge Det

Get Data

Display

300

ms

.00105 ms

per pixel

.00105 ms

per pixel

70

ms

Median Filter

&

Edge Detection

Possible Implementations

1a)
sw

sw
implementation
1b)
sw

hw
implementation
1c)
hw

sw
implementation
1d)
hw

h
w
implementation
Median
Filter
Edge
Detect
S
W
S
W
Median
Filter
Edge
Detect
Pad
Image
Remove
Padding
S
W
S
W
H
W
Median
Filter
Edge
Detect
Pad
Image
Remove
Padding
S
W
S
W
H
W
Median
Filter
Edge
Detect
R
P
R
G
Pad
Image
Fix
Padding
Remove
Padding
S
W
S
W
H
W

Inputs: a profiled library of image processing
components, a pipeline, and an image


Output: an assignment of each component to a
hardware or software implementation

Median Filter

Edge Detection Profiles

Median to Edge Running Time (with Initialization Time)
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0
1000
2000
3000
4000
5000
6000
7000
8000
Total Pixels
Millisecond
sw/sw total
hw/hw total
hw/sw total
sw/hw total

The fastest implementation changes with image size


If only one component in hardware, choose Edge Detector


Different algorithms used at runtime to determine best
implementation. See poster for details.