Simulation Modeling and Testing of SRAMs using Dynamic Current

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Nov 25, 2013 (4 years and 1 month ago)

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Simulation Modeling and Testing of SRAMs using Dynamic Current



Surya Kumar

Intel Corporation, Oregon, U.S.A.

Scott Thomas

University of North Carolina at Charlotte, Charlotte, NC 28223, U.S.A.

Rafic Makki

College of Information Technology, UAE University
, AL
-
Ain, UAE.

Ali Chehab and Ayman Kayssi

American University of Beirut, Beirut, Lebanon

{chehab, ayman}@aub.edu.lb



Abstract


We present an i
DDT
-
based methodology for
testing embedded SRAMs. The targeted defects are
opens, shorts and pattern sensitive

faults. We present
the test algorithm and we assess its fault coverage by
performing fault simulations for a large number of
defects introduced into a memory circuit. We build
and fabricate a test chip consisting of a defect free
circuit and defected memo
ry circuits and we assess
the effectiveness of the algorithm by performing
physical measurements on the chip. Also, we study
the effect of process variation on the test algorithm.


Keywords
: SRAMs, Dynamic power supply
current, design for current testabili
ty, opens, fault
simulation, very deep sub
-
micron technologies.


1.

Introduction


There exists a large body of literature on SRAM
testing [1, 2]. Much of the early work in this area is
focused on defect modeling and test generation using
voltage test methods.

The use of i
DDT

to test SRAMs
was first introduced by Su, et. al. in 1992 [3].

The premise is that abnormal switching of a
memory cell can be detected by observing the
individual i
DDT

pulses resulting from write/read
operations. The proposed method estab
lishes upper
and lower bound on the magnitude of the i
DDT

pulse
and uses a sensor to detect pulses outside the
established range. These bounds are established by
characterizing a “golden” SRAM chip and allowing
for noise effects and process variations.

Sin
ce a defective SRAM cell can be detected by
observing i
DDT
, it is not necessary to perform multiple
READ operations to test the memory. This results in
a large savings in test time. As a result, previously
impractical algorithms, such as Walking [2] can no
w
be used because the test length is reduced from O (n
2
)
to a short test of 5n. The proposed test method was
later verified experimentally [4
-
5]. However, the
method did not address the effect of large circuit
parameters such as large leakages, large bypas
s
capacitors, or embedded SRAMs (e
-
SRAMs) that can
have non
-
standard sizes including wide data buses.
Since the early 1990s, i
DDT

testing has been
investigated by a large number of researchers for
testing memories and random logic circuits [6
-
13].
Recent w
ork includes the use of statistical techniques
[11, 12] for testing random logic circuits and charge
analysis [6] as a diagnostic technique for memories.
Other work includes i
DDT

sensor development [13
-
14].


2.

Embedded SRAM Model for
i
DDT


2.1

Defect Model


Figure 1 shows a single SRAM cell and Figure 2
shows the SRAM model. The basic SRAM cell is a
standard type 6
-
Transistors cell. The SRAM model is
developed to simulate the effects of a much larger
SRAM. It includes the following parameters that are
used to

simulate the effect of worst
-
case conditions
of a 1 Mbit memory organized into 64 (512 x 32
-
cell
sub
-
array) blocks. These parameters are chosen after
consultation with industry [16]:

On
-
chip wire bonding inductance of 1 nH

On
-
chip wire bond resistance of
.01
-


On
-
chip bypass capacitance of
500 fF

Bitline capacitance of 3 pF

Power line capacitance of 40 pF



Figure 1. SRAM cell


Word
Precharge
Rd/Wr
Datain
Sense
Dataout
VDD
VDD_CELL
L
Bondwire
R
bondwire
R
met
C
Bypass
C
PRC
C
Bit
C
Bitbar
Bit
Bitbar
Leakage
Source
To i
DDT
Sensor
Figure 2. SRAM model

The effect of leakage is simulated by the
injection of a 10 mA c
urrent source into the power
source. The SRAM also includes a differential pair
based sense amplifier. The memory cell array has a
separate VDD line (VDD_CELL in Figure 2) from
the rest of the circuit. This is due to the fact that
without a separate power
pad, transients in the I/O
buffers and address decoders seriously affect the
i
DDT

pulses. Thus it is recommended to always separate
the two power lines. Data
-
out is separated from Data
-
in for simulation purposes. Finally, note that the
VDD inductance/resis
tance model is repeated (not
shown) on the VDD line used by support logic
outside the cell array.

Table 1 lists the various fault types and their
corresponding locations. Both capacitive and
resistive opens were employed in the fault model.
Gate
-
oxide shor
ts are modeled via resistive shorts
between the gate and substrate (also via the source
and drain)[15]. Shorts are modeled using resistive
bridges with varying resistor values.

In addition, a model is employed for disturb
-
type
pattern sensitivity [3]. In d
isturb
-
type pattern
sensitivity, a logic transition on one cell can disturb
the contents of another cell. This includes single
direction disturb where one cell is the aggressor and
another one is the victim. In such a situation, a diode
-
connected transisto
r can be used to model the fault. A
total of 219 faults were inserted as single faults into
the SRAM model of Figure 2.



2.2

Fault Simulation


All simulations are performed using SPICE with
the BSIM3v3.2 model. The fault
-
free
i
DDT

response
shows a maximu
m value of 0.2 mA for a cell
transition from 0 to 1 (i
DDT1
) and for a transition from
1 to 0 (i
DDT2
).

Table 2 shows a sample of the parameter values
obtained for each fault class for voltage testing, I
DDQ

and
i
DDT

testing. A “NO” in a column indicates that

the fault in not detected and a “YES” indicates the
fault is detected. Refer to Figure 1 for the locations of
the first eight faults listed. The remaining two PSF
faults are between the two SRAM cells in Figure 2.


VDD_CELL

VDD

Rd/Wr


Datain

Dataout

C
bitbar

Bypass

Bondwire

4

Cprc

To
sensor

Leakage

Bitbar

Sense

Precharge

Word




2.3

Test Algorithm and Fault Cover
age


The test algorithm that is employed targets all
the above fault models including disturb faults. It is
similar to a simple March test as shown below, and it
has a test length of 12n where n is the number of
cells:


{

(w0);


(r0,w1,r1,w0,r0);


(w1);

(r1,w0,r0,w1,r1);}


Note that, while the test is being executed, the
presence of the
i
DDT

monitor is able to detect
abnormal switching due to cell disturb faults and
opens/shorts anywhere in the array. The
i
DDT

test is
able to detect READ
-
enabled faults a
s well as
WRITE
-
enabled faults.

Table 3 summarizes the fault simulation results
of testing by voltage, I
DDQ

and
i
DDT
. In the case of
i
DDT
, a fault is said to be detected if
i
DDT

is at least
20% higher or lower than the fault
-
free response. The
20% figure i
s a relatively stringent requirement that
allows for power supply noise considerations. In the
case of I
DDQ
, a fault is said to be detected if I
DDQ

increases by 50uA or more (note that the modeled
normal leakage is 10 mA).


3.

Physical Test Results

3.1

Test C
ircuit


The test circuit consists of
one good and thirty
five defective cells. The purpose of the circuit was to
measure the difference in the
i
DDT

responses due to
the faults that were added to the circuit. The faults
that were added into the SRAM cells a
re:



1


Ground Open Fault at node #1 in Figure 3



1


VDD Open Fault at node #2 in Figure 3



Missing poly contact at the gate of the inverter
gate at node #3 in Figure 3

All the transistors in the SRAM cell are
minimum sized 5

/2


so that the area of the SRAM
cell
is minimized. The value of


is 0.3


and the
power supply is 5 V.


3.2

Measurement Results


At first the wordline is enabled and then zero is
written in the selected SRAM cell followed by a
write one operation. Finally, the wordline is disabled.
The i
DDT

r
esponse of a defect free memory circuit is
shown in figure 4 where we can see the 4 different
i
DDT

pulses corresponding to the 4 mentioned
operations. We obtain iDDT waveforms using Ohm’s
law after measuring the voltage across the power
supply resistor.


3
.3

Measurement Analysis

Table 4 contains a summary of the measurement
results for
i
DDT
. By referring to Figure 4, the

V
column represents the difference between the
maximum voltage at the power supply during the
period of transition and the input power su
pply
voltage of 5V. The

% column is the percentage
change in
i
DDT

with respect to the good circuit.

From the table,
i
DDT

measurements show good
results in terms of detection percentage. The
magnitude of
i
DDT

for the faulty circuits vary more
than 20% compared to the good circuit

and hence
such defects can be detected.









Figure 3. Fault locations in the SRAM cell


Table 4
.
i
DDT

Voltages at the power supply


i
DDT1

i
DDT2

i
DDT3

i
DDT4



V


%


V


%


V


%


V


%

FAULT FREE

0.45V

0

0.18V

0

0.45V

0

0.20V

0

GROUND OPEN

0.28V

-
37
%

0.10V

-
44%

0.22V

-
51%

0.24V

20%

VDD OPEN

0.19V

-
57%

0.06V

-
66%

0.08V

-
82%

0.02V

-
90%

WORDLINE OPEN

0.08V

-
82%

0.1V

-
44%

0.011V

-
97%

0.04V

-
80%




Figure 4. i
DDT

response of good SRAM cell



4.

Process Variations


4.1

Inter
-
Die Process Variation


A basi
c minimum sized inverter is laid out,
extracted and simulated with HP 0.5um process. The
rise time and fall time of the input signal are taken
care of by using buffers at the input and output of the
inverter. The
i
DDT

was simulated using ELDO Spice
for 40
runs of the HP 0.5um process. The values of
i
DDT

ranged between 780.34 uA and 603.61 uA with
an average of 700.11 uA. As a result, and with a
confidence level of 99% the current varies +/
-

22.2
uA (3%) from the mean value.

We repeat the same process for a
1024 SRAM
cell array. The simulations results show values of
i
DDT

ranging between 643.31 uA and 465.91 uA, with
an average of 543.87 uA. Hence, the
current varies
+/
-

21.2 uA (4%) from the mean value.

When we repeat the process for a 16 cell multi
-
port RA
M cell array we find that the current varies
by +/
-

28.8 uA (3.4%) from the average value.

The percentage change in
i
DDT

for different runs
varies by 20%
-
25% from run to run for all the three
test circuits. The
i
DDT

change caused by inter die
process varia
tion does not scale with the size of
memory array. Hence this has to be taken into
consideration when setting the threshold voltage for
i
DDT
.


4.2

Intra
-
Die Process Variation


Intra
-
die device variations are mostly structural
variations in the devices. The
y are the variations of
the gate length, gate width, oxide thickness, and
offset voltage. In the simulation for intra
-
die process
variation the threshold voltage and oxide thickness
are varied between 90% and 110% of the original
value and simulated for th
e effects. The results are
shown in Tables 5 and 6.








Table 5.i
DDT

variations due to intra
-
die Variation due to V
th

variations



INVERTER

8 Cell SRAM

1024 Cell SRAM

16 cell MPRAM

NOMINAL

780uA



141uA



582uA



929uA



90 % V
THO

805uA

3.20%

145uA

2.80%

637uA

9.40%

997uA

7.30%

110% V
THO

747uA

-
4.20%

137uA

-
2.80%

529uA

-
9.10%

860uA

-
7.40%



Table 6. i
DDT

variations due to intra
-
die variations due to t
OX

variations



INVERTER

8 Cell SRAM

1024 Cell SRAM

16 cell MPRAM

NOMINAL

780uA



141uA



582uA



929uA



90 % TOX

808uA

3.50%

144uA

2.80%

584uA

0.30%

997uA

7.30%

110% TOX

742uA

-
4.80%

137.5uA

-
2.80%

579uA

-
0.30%

860uA

-
7.40%



As seen from the tables, the change of magnitude
of
i
DDT

scales with size of the memory array. Hence,
for a larger memory

the
i
DDT

magnitude due to intra
die variations would be more.

To conclude, we can state the following:



i
DDT

change caused by inter die process
variation does not scale with the size of
memory array.



Worst case change in tox and Vth due to
intra die proces
s variation affects iDDT to a
maximum of 10% for small memories



iDDT change caused by intra die process
variation scales with the size of memory
array.



As a result, even with process variation, the
iDDT peak magnitudes for a good circuit are
still within t
he


20% thresholds.


5.

Conclusion


In this paper we presented an
i
DDT
-
based method
for testing embedded SRAMs. We verified the
detection capability of the method by applying it to
circuits with defects such as opens, shorts and pattern
sensitive faults. The

assessment of the method was
carried out both physically through the
manufacturing of test circuits and by simulation. The
fault simulation results (table 3) showed that the test
method detected 215 defects out of 219 defects
leading to a defect coverage
of 98.2%. The physical
measurement results (table 4) showed that the 3 types
of defects that were inserted into the 35 memory cells
exhibit at least a variation in the peak magnitude of
i
DDT

of 20%. Accordingly, if we set the threshold to
20% as originally

suggested, all defects can be
detected. We also studied the effect of inter

die and
intra
-
die process variations on the test algorithm. The
results showed that the maximum variation in the
peak magnitude of i
DDT

in both intra/inter
-
die process
variations
is 10%. Hence, such variation is taken of
by setting the threshold to 20%, and good circuits
will not be considered as faulty.


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[16]

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(Memory Design Group), Texas Instruments.

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-

DIP40 Kyocera
-
KD
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http://www.mosis.org/Technical/Packaging/Ceramic/p
kg
-
dip40
-
char.pdf

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