Study of De Morgan’s Theorems

nostrilswelderElectronics - Devices

Oct 10, 2013 (3 years and 10 months ago)

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This is to certify that the project of

Study of
De Morgan’s Theorems

Contains the bonafied works of

____________________________________________

Who has worked on the project and completed the same

In the academic year 2009
-
10
.

H
is/h
er

project work

is in Electronics Discipline as per

The Maharashtra State Board of Secondary & Higher Secondary Education,

Pune; Syllabus.





Principal









Head of the Department


Project Guide




2





It adds to my pleasure to acknowledge the pers
ons who have helped

me while the project work was in progress!

First of all I am thankful to
M
M
r
r
.
.


D
D
.
.


S
S
.
.


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a
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g
a
a
r
r


s
s
i
i
r
r
, our Project Guide,
who has helped us in bringing out this project in present status!

Our
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, who has also encouraged us and
helped us during the
completion of this project, for which we are also

thankful to her.

I am grateful to our Head of the department,

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,
,





for providing us the facility of excellent lab instruments and
relevant accessories.

I am also deeply grate
ful to our
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whose discipline has created regularity in us, so as to complete

the project in time.

Last but not the least; I am thankful to
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for his help

in this project work.





3



Basic Gates



AND gate


Definition: an AND
gate is a logic circuit, whose output becomes high ONLY
WHEN ALL ITS INPUTS ARE HIGH. Its logic equation is Y = A.B. This equation shows that
inputs A & B are related to each other with AND mathematical operator. Thus, when A AND B
both are high, then only

Y is high, otherwise low. In this way, the AND multiplication rules for
all possible inputs combinations are as follows



a)

When A = B = 0, then Y = A.B = 0.0 = 0

b)

When A = 0, B = 1, then Y = A.B = 0.1 = 0

c)

When A = 1
, B = 0, then Y = A.B = 1.0 = 0

d)

When A = B = 1,
then only

Y = A.B = 1.1 = 1



OR gate


Definition: an OR gate is a logic circuit whose output becomes high WHEN ANY
ONE OF ITS INPUTS IS HIGH. It
s logic equation is Y = A + B. This equation shows that inputs
A and B are related with OR mathematical operator. Thus, when A OR B is high, Y is high. The
OR addition rules for all possible combinations of inputs are



a)

When A = B = 0, Y = A + B = 0 + 0 =

0

b)

When A = 0, B = 1, Y = A + B = 0 + 1 = 1

c)

When A = 1, B = 0, Y = A + B = 1 + 0 = 1

d)

When A = B = 1, Y = A + B = 1 + 1 = 1





NOT gate


Definition: a NOT gate has only one input and one output. It gives high output
WHEN ITS INPUT IS LOW. Its logic equa
tion is Y =
. Thus, it shows that Y is complement
of A. The rules of NOT operations are



a)

When A = 0, then Y =

=

= 1

b)

When A = 1, then Y =

=

= 0





A

B

Y = A.B

0

0

0

0

1

0

1

0

0

1

1

1

A

B

Y = A + B

0

0

0

0

1

1

1

0

1

1

1

1

A

Y =

0

1

1

0


4


De Morgan’s Theorems


First theorem


i
t states that the complement of product is equal to the sum of the complements.

Logic equation



Proof



w
e shall prove above
theorem

by

showing that
LHS
&

RHS

of given equation are equal
.

LHS =

Let

A = B = 0; then

=

=

= 1

Let

A = 0 & B = 1; then

=

=

= 1

Let

A = 1 & B = 0; then

=

=

= 1

Let

A = B = 1; then

=

=

= 0


RHS =


Let

A = B = 0; then

=

= 1 + 1 = 1

Let

A = 0 & B = 1; then

=

= 1+ 0 = 1

Let

A = 1 & B = 0; then

=

= 0 + 1 = 1

Let

A = B = 1; then

=

= 0 + 0 = 0



Thus, LHS = RHS,
hence proved.



Second

theorem


i
t states that the complement of
sum

is equal to the
product
of the
complements.

Logic equation



Proof



w
e shall prove
the

theorem

by showing that
LHS
&

RHS

of given equation are equal
.


LHS =

Let

A = B = 0; then

=

=

= 1

Let

A = 0 & B
= 1; then

=

=

= 0

Let

A = 1 & B = 0; then

=

=

= 0

Let

A = B = 1; then

=

=

= 0


RHS =


Let

A = B = 0; then

=

= 1.1 = 1

Let

A = 0 & B = 1; then

=

= 1.0 = 0

Let

A = 1 & B = 0; th
en

=

= 0.1 = 0

Let

A = B = 1; then

=

= 0.0 = 0



Thus, LHS = RHS,
hence proved.




1


1


1


0


1


1


1


0


1


0


0


0


1


0


0


0



5

Derived Gates


derived gate means a combination of basic gates. There are tw
o types of
derived gates NAND gate and NOR gate.


1)

NAND gate


it is the combination of AND gate and NOT gate. Its output becomes LOW
ONLY WHEN ALL ITS INPUTS ARE HIGH. In other words, its output is high when at least
one of its inputs is low. Its logic equ
ation is given by


Y =


1)

Let A = B = 0; then

=

=

= 1

2)

Let A = 0 & B = 1; then

=

=

= 1

3)

Let A = 1 & B = 0; then

=

=

= 1

4)

Let A = B = 1; then

=

=

= 0





2)

NOR gate


it is the combination of OR gate and NOT gate. Its output becomes HIGH ONLY
WHEN ALL OF ITS INPUTS ARE LOW. In other words, its output is low when at least one
or all of its inputs are high. Its logic equation is
given by


Y =


1)

Let A = B = 0; then

=

=

= 1

2)

Let A = 0 & B = 1; then

=

=

= 0

3)

Let A = 1 & B = 0; then

=

=

= 0

4)

Let A = B = 1; then

=

=

= 0









A

B

Y =

0

0

1

0

1

1

1

0

1

1

1

0

A

B

Y =

0

0

1

0

1

0

1

0

0

1

1

0


6

NAND gate & NOR gate as universal building blocks


these above gates are derived gates
created by combining basic gates. These gates are called universal building blocks, because any
type of gate can be constructed using these g
ates. For this, remember following rules


A + A = A,

= A, A.1 = A, A +

= 1, A .

= 0, A . A = A, A + 1 = 1


1)

NOT gate using NAND gate


when both inputs of a NAND gate

are connected to each other
and
treated as single input

it forms a NOT gate. Here both
input terminals of NAND gate are connected together. So
input signal at terminal A will be equally distributed to both
inputs of NAND gate. Hence, the output will be th
e same as NOT gate with a single input.

When A = 0, Y =

=

= 1 =


Y =

When A = 1, Y =

=

= 0 =


Y =


2)

OR gate using NAND gate


a bubbled NAND gate forms OR gate





3)

AND gate using NAND gate


when output of NAND gate is inverted again, it forms an
AND gate as follows









––––––––––––––––––––––––––––––––––––––







7


Costing of the Project



The costing of components, used in this project is as follows



Sr.
Nos.

Item

Price

1)


IC
s

SN
7400, 7402,
7404, 7408, 7432,

LM 7805


2)


Transformer 6
-
0
-
6V/500mA


(step down)


3)


Banana sockets


4)


Resistors


( carbon composition)


5)


Capacitors
(all types)


6)


Socket

of ICs


7)


Mains cord
(9 feet)


8)


Sunmica board


9)


Indicator LED


10)


Miscellaneous, nut bolts, flexible wire etc.






The prices given here are according

to the bill
-
receipt obtained from the
shopkeeper. The above said material was purchased on / / 2009.

And the material was purchased from ________ market.


Signature of the student






8



References




Digital circuits :

By Harihar Ghime

S. Chand and
Publications, ND




Digital principles and applications :






By Malvino






Mc Graw Hill co. ltd.




Linear Integrated Circuits
:


By
Ramakant Gaikwad

Peoples Publishing House, N. D.



Nomenclature of ICs and transistors:

S. Ramabhadran






S. Chand and Co. New Delhi, 1987.