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Power efficient multi-stage CMOS rectifier design for UHF RFID tags
$
Shu-Yi Wong,Chunhong Chen
n
Department of Electrical and Computer Engineering,University of Windsor,Ontario,Canada N9B 3P4
a r t i c l e i n f o
Article history:
Received 5 April 2010
Received in revised form
7 March 2011
Accepted 8 March 2011
Available online 17 March 2011
Keywords:
RFID
Low power
Differential-drive rectifier
a b s t r a c t
Power efficiency of a UHF rectifier circuit,which is part of long-range IC-based passive RFID tags,has
become a serious bottleneck in implementing power-hungry intelligent sensors.This paper presents an
analytical approach for multi-stage rectifiers,which provides design tradeoffs as well as a set of design
rules to improve power efficiency of the rectifier.As an example,three-stage rectifiers are designed
with ST 90 nm CMOS technology for optimized performance at both 10 and 22 m distances.When
compared with existing results at the same level of output power,the proposed rectifiers show a
3 better performance in power efficiency (73%) and 55% reduction in power-up threshold with longer
operating range.
& 2011 Elsevier B.V.All rights reserved.
1.Introduction
Passive radio-frequency identification (
OR
RFID) tags are a class
of RFID devices that obtain the power solely from the incident
radio frequency energy [3,4,10].Some of them fulfill the function
as bar-code replacements with no need for sophisticated power
harvesting schemes due to their low power consumption of a few
micro-Watt [4].RFID applications for the auto industry (such as
remotely powered intelligent sensors),however,require power of
at least an order of magnitude higher while maintaining a long
detection range.It is,therefore,necessary for these sensors to have
a highly efficient power supply.To this end,the focus is on design
of the tag’s analog front-end circuit and,in particular,rectifier for
power extraction.Due to the relatively higher regulatory limit for
equivalent isotropic radiative power (P
EIRP
) of 4 W,the operating
frequency of 915 MHz is desirable for the UHF RFID,which offers a
good balance between detection range and available power.
Conventional rectifier circuits are based on the Dickson multi-
plier topology [2,5,6,8],where the MOS transistors are used in the
diode-connected mode.These circuits suffer from inferior power
conversion efficiency (PCE) due to the forward voltage drop which
should be greater than transistor’s threshold voltage (V
th
).
While process enhancements help solve the problem [11,18],a
variety of circuit design methods have achieved better perfor-
mance with standard process by introducing a gate bias to reduce
the effect of V
th
.Examples include the external threshold-voltage
cancellation (EVC) [6],internal threshold-voltage cancellation
(IVC) [5],and self threshold-voltage cancellation (SVC) [7].An
extreme case is the use of zero-threshold transistors [2] with
which,however,comes significant amount of the reverse leakage
that degrades the power efficiency.
To address the conflicting issues of reducing both forward-
voltage drop and leakage,a recent study on differential-drive
CMOS rectifier [1] shows a much higher PCE (up to 66%) than
previous works on the same subject [16].Apart fromthe absence
of design methodology,the above study only applies to a single-
stage rectifier.In general,more stages are needed for a practical
tag in order to produce a sufficient output voltage.While a three-
stage rectifier has also been designed [3],the reported PCE is only
24% with little or no roomfor improvement due to the conflicting
requirement of bandwidth and detection range.Traditionally,
cascading of stages tends to degrade the power efficiency due to
the body effect of transistor.However,as we will see later in this
work,this is not necessarily the case.Meanwhile,existing design
methods attempt to minimize the power consumption for a given
output power using a linear model of the rectifier.While the
linear assumption does simplify the design by associating some
design metrics with the PCE,it is only valid for the case of low
efficiency where linear parasitic components dominate [3].In this
work,we aim to maximize the rectifier output power for a given
operating range instead,with the proposed piece-wise linear
model of the rectifier which is applicable for high PCE operation.
We develop a new design methodology for multi-stage rectifiers
which promise the high PCE.Also,we show that the output
voltage at individual stages,when well controlled,plays an
important role in improving the rectifier’s PCE.
The rest of the paper is organized as follows.Section 2
provides an overview of the proposed design method with brief
description of main contributions of this work.Section 3 presents
an analytical model for multi-stage differential-drive CMOS rec-
tifiers with discussions.The contour analysis shown in Section 4
identifies the rectifier’s optimal operating conditions.Section 5 is
Contents lists available at ScienceDirect
journal homepage:www.elsevier.com/locate/vlsi
INTEGRATION,the VLSI journal
0167-9260/$- see front matter & 2011 Elsevier B.V.All rights reserved.
doi:10.1016/j.vlsi.2011.03.005
$
This work was supported in part by the AUTO21 Network of Centers of
Excellence,Canada.
n
Corresponding author.
E-mail addresses:wong11j@uwindsor.ca (S.-Y.Wong),
cchen@uwindsor.ca (C.Chen).
INTEGRATION,the VLSI journal 44 (2011) 242–255
devoted to developing a piece-wise linear approximation model
for the rectifier.With this model,the matching theory for a piece-
wise linear load is discussed in Section 6.Section 7 looks at design
considerations with tradeoffs among the bandwidth,operating
range and technology process.Section 8 proposes our design
for three-stage differential-drive CMOS rectifiers,followed by
simulation results and conclusions given in Sections 9 and 10,
respectively.
2.Overview and main contributions
This section begins with description of general design pro-
blems for differential-drive CMOS rectifier circuits along with
some definitions,followed by an outline of the proposed design
method and main contributions of this work.
2.1.Design problems for power efficient rectifier
Fig.1 illustrates the block diagramof a UHF rectifier [17],where
the incident RF energy is first converted to electrical power by the
antenna.The matching network is responsible for controlling the
voltage and current of this power in such a way that the highest
possible portion of the power can be delivered through the rectifier
to the load under desired conditions.The rectifier circuit converts
the incoming AC power into DC power at the output where there is
usually a shunt voltage regulator for stabilizing the voltage for the
load.In this work,we only study the differential-drive CMOS
rectifier and the matching technique.The antenna is assumed to
have resistive impedance with an infinite bandwidth.To facilitate
calculations,we also assume a simple half-wave dipole antenna
with an impedance of 73
O
and antenna gain of 1.64.The choice of
such a narrowband antenna may not be optimal,but it serves as a
vehicle for development of a theory that is equally applicable for
other antennas with different impedance and gain.For the match-
ing network,we use a simple off-chip first-order L-match network
since our goal is to explore the potential of obtaining high power
efficiency for the rectifier.An off-chip matching network is
typically not an issue because it can be easily integrated with
the antenna,which has to be off-chip anyway due to its physical
size for the operating frequency under consideration.An off-chip
matching network provides additional design flexibility while
supporting higher Q and larger component values,which would
otherwise be impossible for a chip-integration solution.
Prior to further discussions on design problems,some defini-
tions are given below.First,the PCE is used exclusively to
represent the rectifier’s power efficiency as follows [3]:
PCE ¼
P
L
P
R
ð1Þ
where P
L
denotes the average output power at the load and P
R
is
the average real input power to the rectifier.Another important
quantity is systemefficiency [3].To avoid confusion between these
two terms,we shall refer to the latter as power utilization (PU),
which is defined as
PU ¼
P
L
P
A
ð2Þ
where P
A
is the available power from the antenna,given by [14]
P
A
¼
P
EIRP
4
p
r
2
l
2
4
p
G ð3Þ
where P
EIRP
is the equivalent isotropic radiative power of the
source,r is the distance between the tag and the source,
l
is the
wavelength of the incident RF energy and G is the antenna gain.
Design of a power efficient rectifier involves (a) maximization of
PCE through the well-designed rectifier and (b) maximization of PU
by making P
R
as close to P
A
as possible through proper matching.
Traditional design methods [5–7,9] have demonstrated how the
transistors’ on-resistance could affect the rectifier’s efficiency.
Therefore,the natural step for boosting the latter is to reduce the
diode-drop,or the voltage across the resistors.Ideally,the effi-
ciency would become very high when the voltage drop approaches
zero.In reality,this does not happen because a close-to-zero
voltage drop would mean that the transistors are turned off most
of the time,and that there is very little power being transferred to
the load.In this case,the off-resistance due to substrate loss and
channel leakage becomes dominant [2,3].The benefit of analyzing
the voltage drop is the result of its linearity in both high and low
values,in alignment with the linear model of power matching.
However,the high PCE of CMOS differential-drive rectifier [1,12] is
a good reminder that the rectifier is non-linear in nature.Intui-
tively,it should operate most efficiently when the power is
transferred via the non-linear transistor switches to the load,
instead of being dissipated in the turn-on or parasitic resistance.
This represents the demand for a non-linear matching model for
the rectifier.Also,under such a non-linear condition,it is of interest
to find the efficiency and to determine where its upper bound may
lie.Our approach starts with an analytical model,which provides a
set of salient efficiency-determining parameters while a fully
analytical solution is not available due to the model’s complexity.
It is found that by fixing these parameters,rectifier circuits remain
scalable for most load conditions.This allows us to decompose the
original design problem into two independent ones.The first is
efficiency optimization,which is done by simulating the analytical
model described in Sections 3 and 4.The second is matching
problem,which is discussed after Section 5.
2.2.Main contributions
The general idea behind this work is as follows.We begin by
developing a PCE model,which captures most of CMOS transis-
tor’s non-linear effects.We then seek to determine a set of circuit
design parameters,which uniquely fix the PCE.Unlike previous
work which assumes the importance of load current,our work
shows that the more important parameters are,in fact,the output
voltage (V
out
),the ratio of input to output voltages (
d
) and the
transistor width ratio between the PFET and NFET pair (g
2
).
Instead of scaling transistors directly based on the load current
requirement,we first find the set of V
out
,
d
and g
2
for the
maximum PCE.Subsequently,the transistors are scaled in order
to meet the load current requirement while keeping the set of
parameters constant.This allows us to (a) scale transistors freely
for any output current level without affecting the PCE,and
(b) cascade multiple rectifier stages without incurring PCE degra-
dation.Finally,a piece-wise linear model is presented for approx-
imations with the non-linear rectifier,which allow for the power
matching and PU optimization.It is found that the proposed
model can account for all effects with the rectifier at the point of
peak PCE,and yield results quite different from those expected
A
C
L
compensate
R
a
=73Ω
L
LS
C
LP
Model
For
Differential-Drive
CMOS Rectifier
S
h
unt
Reg
ul
a
t
o
r
T
ag
C
i
rcu
i
t
s
V
L
I
L
P
L
=V
L
I
L
Rectifier
Matching Circuit
Load
Antenna
Fig.1.Block diagram for the overall rectifier circuit.
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255 243
with the traditional matching technique.The main contributions
of this work are summarized as follows:
(i) Development of an analytical model for the rectifier.
(ii) Discussion of conditions for maximum PCE.
(iii) Description of a PCE-invariant design scaling method.
(iv) Investigation of a piece-wise linear approximation model for
the rectifier and a newmatching theory for piece-wise linear
loads.
(v) Establishment of relationship among the rectifier’s band-
width,operating range and technology process.
(vi) Design of three-stage rectifiers with ST 90 nm CMOS tech-
nology for optimal performance at 10 and 22 m.
(vii) Demonstration of simulation results showing that the
obtained PU is potentially 3 times as much,and that the
maximumoperating range is 55% longer,when compared to
the existing results under the same level of available power.
3.An analytical model for multi-stage rectifiers
This section first describes a general multi-stage differential-
drive CMOS rectifier.It is shown that such a rectifier can be fully
characterized by its half-wave bridge version,the detailed analy-
sis of which is then given in order to develop our design theory.
3.1.Multi-stage differential-drive CMOS rectifiers
Typical RFID tags require a supply voltage beyond a single-
stage rectifier can provide.A three-stage differential-drive CMOS
rectifier is shown in Fig.2,where C
int
represents the uniform
charge reservoirs,and C
o
is the output capacitor which could have
a bigger value than C
int
,depending on the transient load current.
While all bulk connections of the NMOS transistors in Fig.2 are
wired together,the separate N-wells of PMOS transistors allow a
degree of freedom for their biasing (i.e.,V
b1
,V
b2
and V
b3
),which
can be utilized for some design advantages (see Section 4.2 for
details).The dotted lines in Fig.2 indicate stage boundaries,
where basic cells of rectifier are cascaded.For convenience of
discussion,a basic cell of rectifier is also illustrated in Fig.3(a),
where voltage sources V
x
and V
x1
are used to replace C
int
of Fig.2
(the suffix x denotes the stage number).This replacement is
reasonable since (a) the ripple effect can be made arbitrarily small
by using a large capacitor,and (b) a shunt voltage regulator in the
tag also enables the voltage to stay within a tight range.
With DC analysis,it can be seen from Fig.3 that the output
current (I
ox
) equals the input current (I
ix
).If the output voltage
(V
x
) is divided into two voltages,V
ex
and V
x1
,then an effective
ground can be created,as shown in its equivalent circuit of
Fig.3(b).Since both gate voltages (V
i1x
and V
i2x
) are raised by
V
x1
,the coupling capacitors (i.e.,C
c
) are needed in Fig.2 for DC
blocking.If V
ex
equals V
1
for all stages,it follows that V
x
¼xV
1
,and
one only needs to fully characterize one basic cell in order to
understand the multi-stage rectifier.Also,the basic cell shares the
form of a full-wave bridge rectifier with its two identical alter-
nately conducting half-wave bridge circuits.In the following
discussions,we refer to the above rectifier circuits as the differ-
ential-drive CMOS full-wave bridge rectifier (DDCFB) and half-
wave bridge rectifier (DDCHB),respectively.
3.2.Differential-drive CMOS half-wave bridge rectifier
A DDCHB consists of a pair of complementary MOS transistors,
as shown in Fig.4.Both transistors are connected in series with an
output capacitor.For convenience of discussion,we introduce
some terms as follows:
V
in
—RF input voltage;
V
thn
,V
thp
—threshold voltages of NMOS and PMOS transistors;
V
gsn
,V
gsp
—gate-to-source voltages for NMOS and PMOS
transistors;
V
dsp
,V
dsn
—drain-to-source voltages for NMOS and PMOS
transistors;
V
out
—output voltage across the output capacitor;
I—current through the output capacitor;
g
2
—transistor sizing parameter.
Particularly,g
2
encapsulates the geometric properties of the
circuit and is defined as
g
2
¼
b
n
b
p
ð4Þ
where
b
n
(
b
p
) represents the technology process and geometry
constant of the NMOS (PMOS) transistors and is given by
b
n
¼
m
n
C
ox
W
n
L
n
,
b
p
¼
m
p
C
ox
W
p
L
p
ð5Þ
Throughout this paper,the channel lengths for both NMOS and
PMOS transistors are assumed to be the same (i.e.,L
n
¼L
p
).With
A
C
C
c
C
c
C
c
C
c
C
c
C
c
Q
2
Q
4
Q
5
Q
3
Q
6
Q
8
Q
7
Q
1
Q
12
Q
11
Q
10
Q
9
C
int
C
int
C
o
V
1
V
2
V
3
V
b1
V
b2
V
b3
1
st
stage 2
nd
stage 3
rd
stage
Fig.2.Schematic of a three-stage differential-drive CMOS rectifier.
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255244
the level-one SPICE model,one can get some insight to the
operation of Fig.4.More specifically,the DC operation curve for
one signal cycle involves six different regions of operation as
described below.
3.2.1.Region one (forward conduction region)
It can be seen fromFig.4 that if V
in
ZV
out
,then V
gsn
¼V
gsn1
and
V
gsp
¼V
gsp1
.Under this condition,the current I flows from top to
bottom with V
in
¼V
gsp
¼V
gsn
and V
in
V
out
¼V
dsn
þV
dsp.
.As a result,
V
dsp
(or V
dsn
)oV
in
V
out
.When V
out
Z9V
thp
9,the transistors will
always operate in triode mode,and the current is given by [15]
I
tcr
¼
b
p
ðV
in
V
thp
ÞV
dsp

1
2
V
2
dsp
 
ð6Þ
or
I
tcr
¼
b
n
ðV
in
V
thn
ÞV
dsn

1
2
V
2
dsn
 
ð7Þ
Solving (6) and (7) with the above conditions leads to an
expression for I
tcr
in terms of V
in
,V
out
,V
thn
and V
thp
only.It should
be noticed that the bulk is intentionally connected to drain
terminals such that the body effect will decrease the threshold
voltage for a slightly higher forward current.However,this
current change due to the body effect is very small,and (6) or
(7) still provides a good estimate for the total current.
The advantage of this rectifier is evident when compared to
the Dickson multiplier topology.For instance,a transistor in the
Dickson multiplier will turn on only when V
in
V
out
ZV
thp
.But the
transistor in differential-drive rectifier turns on when V
in
ZV
thp
,
which means that it can work at a lower input level.
3.2.2.Region two (reversed triode conduction)
When V
in
becomes smaller than V
out
,we have V
gsn
¼V
gsn2
and
V
gsp
¼V
gsp2
and the current I starts flowing in the reversed
direction (i.e.,from bottom to top in Fig.4),and both V
dsn
and
V
dsp
become negative.Under this condition,V
gsn
¼V
out
þV
dsp
,
V
gsp
¼V
in
V
dsp
and 9V
dsp
9 (or 9V
dsn
9)oV
out
V
in
.As long as
V
in
Z9V
thp
9,the transistors remain in triode mode,and (6) and
(7) apply.The bulk terminals are now connected with source
terminals with no body effect.Otherwise,the reverse leakage
current (particularly the subthreshold and reverse conduction
currents) will increase,causing undesirable power loss.
3.2.3.Region three (partial saturation)
When V
thn
rV
in
o9V
thp
9,the PMOS transistor works in satura-
tion mode while the NMOS transistor stays in triode mode.The
current for the PMOS becomes
I
ps
¼
1
2
b
p
V
in
V
thp
V
dsp
 
2
ð8Þ
3.2.4.Region four (full saturation)
If we define
n
¼V
thn
þV
thp
V
out
ð9Þ
Then the transistors enter the saturation region when
n
rV
in
oV
thn
.The resulting current is given by [15]
I
fs
¼
1
2
g
2
ð1þgÞ
2
b
p
ðV
in

n
Þ
2
ð10Þ
3.2.5.Region five (subthreshold conduction)
When V
in
is smaller than
n
,both V
gsn
and V
gsp
are still forward
biased,and the transistors are in the subthreshold mode of
operation.The current can be expressed as [15]
I
sc
¼
t
p
b
p
e
ðV
gsp
V
sbp
Þ=nV
T
ð1e
V
dsp
=V
T
Þð1
l
subp
V
dsp
Þ ð11Þ
V
bx
V
x
V
x-1
V
i1x
V
i2x
I
ix
I
ox
V
bx
V
x-1
V
i1x
V
i2x
I
ix
I
ox
V
ex
Point A
Effective
Ground
Q
h1
Q
h2
Q
h1
Q
h2
Fig.3.A basic cell of rectifier (a) and its equivalent circuit (b).
AC
V
in
V
ex
V
dsp
V
dsn
V
gsp1
V
gsp2
V
gsn1
V
gsn2
I
Q
h1
Q
h2
V
i2x
V
i1x
V
bx
V
x-1
Fig.4.A differential half-bridge rectifier circuit.
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255 245
where V
sbp
is the source-to-bulk voltage,
l
subp
is for modeling the
effect of drain induced barrier lowering (DIBL) of the PMOS
transistor and
t
p
is given by
t
p
¼
I
sop
m
p
C
ox
ð12Þ
where I
sop
is the curve-fit offset leakage current for the PMOS
transistor.
Since V
gsn
¼V
out
þV
dsp
and V
gsp
¼V
in
V
dsp
,the differential-drive
CMOS rectifier is clearly better than Dickson multiplier in which
the transistors are biased with a constant voltage when V
in
rV
out
.
This is because the constant V
gs
bias significantly raises the
subthreshold current which is exponentially related to V
gs
,and
is hence highly disadvantageous for the PCE.
3.2.6.Region six (full reverse conduction)
If the size of the NMOS transistor is much larger than that of
the PMOS transistor,V
dsp
becomes much greater than V
dsn
and is
close to the value of V
out
as V
in
approaches zero.As a result,
V
gsn
E0 and V
gsp
EV
out
.The NMOS transistor will operate in
reverse leakage mode when V
in
o0.Conversely,when the PMOS
transistor is much larger than the NMOS transistor,the former
will first enter the reverse leakage mode when V
in
o0.On the
other hand,when the two transistors are sized such that V
dsp
equals V
dsn
,both of them will enter the reverse leakage mode in
the range of V
out
rV
in
r0.Under the reverse leakage mode,the
current I is given by
I
rl
¼
t
p
b
p
e
ðV
sbp
=nV
T
Þ
ð1e
V
dsp
=V
T
Þð1
l
subp
V
dsp
Þ ð13Þ
which depends on V
sb
(but not V
gs
).
The above analytical model will be used in Section 4 for PCE
optimization.Fig.5 depicts the current waveform for a half-cycle
of conduction through all of the six operating regions described
above.In Section 3.3,we focus on investigation of matching issue.
The idea is to use the rectifier’s AC model and,through step-by-
step simplification,obtain a piece-wise linear matching model
which will be derived in Section 5.
3.3.AC model for differential-drive CMOS rectifier
The model discussed so far only applies to DC analysis.
However,parasitic capacitances of actual transistors will lead to
extra AC currents.For modeling of the AC currents,small signal
model will not yield useful result as the input AC signal spans a
wide range of voltages and the rectifier also behaves non-linearly,
especially when it operates with high PCE [3].A large signal
model for parasitic capacitances has been given by well known
sources (such as [13]).Fig.6(a) depicts a PMOS with parasitic
capacitors across each pair of its terminals.These capacitors
represent the gate-to-source,gate-to-drain,gate-to-bulk,drain-
to-bulk and source-to-bulk capacitances,denoted by C
gsp
,C
gdp
,
C
gbp
,C
dbp
and C
sbp
,respectively.The leakage current through the
gate of a 90 nmPMOS is still in the pico-ampere range even when
the transistor width is tens of micro-meters.Normally,the
transistor’s substrate is reversely biased with respect to the
channel,the source and the drain.Therefore,the leakage currents
through the substrate consist of junction leakages.However,
these currents are orders of magnitude smaller than the dominant
channel conduction current due to the triode mode and the
subthreshold mode conduction.For this reason,these leakage
currents can be ignored,leading to the replacement of the
PMOS by an equivalent P-type non-linear resistor,as depicted in
Fig.6(b),whose operations follow the equations given in Section
3.2.In this analysis process,we are not interested in the non-
linear resistor’s exact circuit model.Rather,we seek to find its
behavioral model at the point of circuit’s optimal efficiency.This
is done by separating the non-linear circuit element from the
linear elements in order to approximate the rectifier circuit by a
simple linear RC network with an in-parallel non-linear resistor,
which is to be described at the end of this section.Due to the
resistor’s non-linearity,instead of analyzing it directly we discuss
the conditions of optimal PCE based on the simulation of Section 4.
It is under these conditions that the piece-wise linear model
approximates the non-linear resistor (refer to Section 5).
By the same token,the NMOS can also be modeled by C
gsn
,C
gdn
,
C
gbn
,C
dbn
,C
sbn
and an N-type non-linear resistor.This model can be
used to replace the PMOS and NMOS transistors in Fig.4 and result
in the equivalent circuit of Fig.7.Furthermore,for AC analysis,the
fixed voltage sources of V
bx
,V
x1
and V
ex
are treated as a short-
circuit,and so are the C
dbn
and C
dbp
capacitors in parallel with the
sources.By rearranging components of Fig.7,we ultimately obtain
the AC equivalent circuit of Fig.4,shown in the top half of Fig.8.The
AC equivalent circuit for the other half-bridge of the rectifier is
shown at the bottompart of Fig.8.If the same voltage is applied to
each respective half-bridge,the values of the capacitors C
0
in Fig.8
should be exactly the same as the values of capacitors C since the
two circuits are symmetrical.In general,all capacitances in Fig.8 are
non-linear and their values depend on the biasing level.For
instance,when the transistors are in cut-off region,C
gsn
,C
gdn
,C
gsp
and C
gdp
mainly consist of overlap capacitors,which have relatively
small values while C
gbn
and C
gbp
have much bigger values.When the
transistor turns on instead,with a strong inversion layer,the values
of C
gbn
and C
gbp
diminish while C
gsn
,C
gdn
,C
gsp
and C
gdp
increase [13].
When both top and bottom half-bridges of Fig.8 are considered
Fig.5.Current for a half-cycle of conduction through all six-regions.
C
gd
C
db
C
gs
C
sb
C
gb
drain
substrate
gate
source
C
gd
C
db
C
gs
C
sb
C
gb
P
-
t
ypeN
o
n-li
n
e
a
r
R
e
si
s
t
o
r
V
dsp
Fig.6.PMOS model of [13] (a) and its approximated model (b).
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255246
together,the C and C
0
values tend to change in complementary of
each other due to their AC input being 1801 out of phase for a
sinusoidal input.Another feature of the rectifier’s AC equivalent
circuit is that the currents I and Iþ in Fig.8 are identical due to
the symmetrical nature of the circuit,leading to an average current
of I that equals zero.This implies the center-tap that connects the
non-linear resistors to the capacitors can be disconnected for
simplicity of modeling.These phenomena allow us to use a fixed-
value capacitor (denoted by a parasitic capacitor C
p
) to model the
above capacitive network.Ideally,C
p
is purely reactive and con-
sumes no power.Thus,although the circuit of Fig.4 is fully
characterized with AC and DC analysis,the DC analysis can be
applied first to get the most important insight about PCE.The AC
effect is then taken into consideration for non-ideal properties of C
p
.
For instance,the high resistivity of poly-silicon gates and the
substrate loss will manifest themselves as losses.As an approxima-
tion,these losses can be represented by a loss resistor R
loss(AC)
,which
connects in parallel with C
p
.More discussions about the AC loss will
be given later in Sections 4.3 and 5.
4.PCE contour analysis
Based on the rectifier model derived in Section 3,this section
discusses the conditions for maximum PCE with the rectifier.
4.1.3-dimensional contour for PCE
Combining the expressions of current I from (6)–(13) leads to
I ¼
I
tcr
,V
thp
rV
in
I
ps
,V
thn
rV
in
oV
thp
I
fs
,
n
rV
in
oV
thn
I
sc
,
i
rV
in
o
n
I
rl
,V
in
o
i
8
>
>
>
>
>
>
<
>
>
>
>
>
>
:
ð14Þ
where
i
is defined as a voltage in the range of [V
out
,0],which
depends on the ratio of transistor sizes (refer to Section 3.2).Since
the rectifier is typically supplied with a sinusoidal input voltage
V
in
,we assume V
in
¼V sin
y
,where
y
is an arbitrary frequency
parameter in radian.From(1),the rectifier’s PCE can be written as
PCE ¼
V
out
R
2
p
0
I d
y
V
R
2
p
0
I sin
y
d
y
ð15Þ
where I is given by (14).Since
b
p
is a common termin (14),it will
be canceled in calculating (15).This implies that the effect of
transistor geometry on the PCE is due to g
2
(defined by (4)),and
the PCE can be maintained while scaling the transistors for any
output power level.Intuitively,a high PCE would occur when the
forward voltage drop through the transistors is small.From (15),
this happens when VEV
out
and
y
E
p
/2,leading to PCEEV
out
/V.
For any value of
y
,the PCE is generally dependent on the ratio
V
out
/V which is denoted as
d
¼
V
out
V
ð16Þ
where
d
ranges from 0 to 1.From the above analysis,it follows
that the PCE depends upon three key parameters,namely g
2
,
d
and V
out
(the body effect will be discussed in the next subsection).
Other parameters are process-related and can be treated as a
constant during the design.To account for channel modulation
effects,we rely on BSIM3 simulation results to fine-tune (6)–(13).
With all these effects included,it would be too complicated to
find an analytical solution for (15).In general,the PCE vs.above
key parameters can be examined in a four-dimensional coordi-
nate system.However,with (16) in mind,we can look at the
projection of the above four-dimension problem into 3-dimen-
sional contours with various values of
d
.Also,to handle the
complexity with large volume of data,we resort to MATLAB
for computation.Fig.9 illustrates an example of PCE contour
P-type
Non-linear
Resistor
N-type
Non-linear
Resistor
P-type
Non-linear
Resistor
N-type
Non-linear
Resistor
AC
C
gsp
C’
gsp
C
gsn
C’
gsn
C
sbp
C
gbn
C
gdn
C
gbp
C
sbn
C
gdp
C’
sbp
C’
gbn
C’
gdn
C’
gbp
C’
sbn
C’
gdp
PR
NR
PR’
NR’
I+
I-
I
Fig.8.AC equivalent circuit of DDCFB.
Fig.9.A PCE contour example for V
sb
¼0 and
d
¼0.82.
N-type
Non-linear
Resistor
A
C
P-type
Non-linear
Resistor
C
gsp
C
gsn
C
sbp
C
gbn
C
gdn
C
gbp
C
sbn
C
dbp
C
gdp
C
dbn
V
bx
V
x-1
V
ex
PR NR
Fig.7.Equivalent circuit of DDCHB with parasitic capacitors.
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255 247
(for V
sb
¼0 and
d
¼0.82) from a single-stage rectifier with CMOS
90 nm technology.
It can be seen fromFig.9 that the PCE peaks at V
out
¼0.28V and
g
2
¼0.5,and it drops when V
out
deviates 0.28 V.On one hand,V
out
must be greater than 9V
thp
9 in order for the transistors to operate
in triode mode for low loss (refer to Section 3.2).On the other,if
V
out
is too high such that V
in
rV
out
,the leakage becomes sig-
nificant,leading to a reduced PCE.The fact that the PCE peaks at
g
2
¼0.5 indicates the existence of an optimal transistor size ratio.
This is because the transistor size ratio affects the V
ds
(in the
subthreshold region) and hence the transistors’ percentage time
spent in the subthreshold mode of conduction,which is a
significant contributor to the leakage.While Fig.9 shows only
one contour for
d
¼0.82,more contours can be obtained with
different values of
d
.Analytically,the global optimal PCE can be
determined by solving
@PCE
@V
out
¼
@PCE
@g
2
¼
@PCE
@
d
¼0 ð17Þ
Our simulation shows that the optimal PCE of 74.6% occurs at
the contour with
d
¼0.82 and V
sb
¼0 (for both transistors).
4.2.Maximum PCE vs.body effect
Traditional analysis has identified the threshold voltage V
th
as
a culprit for power loss in rectifier circuits.Thus,it is natural to
assume that the body effect will degrade the PCE,especially for
multi-stage rectifier designs using regular CMOS transistors with
non-zero V
th
[2].This is because the bulk of NMOS transistors in
intermediate stages will unavoidably experience an increasingly
negative bias voltage.However,the above assumption is not
necessarily valid for a CMOS differential bridge rectifier.Figs.10
and 11 showa top viewof PCE contour diagrams for two different
source-to-bulk bias voltages,where the darker color represents
lower PCE while the brighter area corresponds to higher PCE.
It can be seen from Figs.10 and 11 that with a higher source-
to-bulk bias voltage of 0.66 V for the NMOS transistor,the point of
maximum PCE simply shifts to a higher value of 78.8% when
V
out
¼0.3 V and g
2
¼1.2.While this may seem to be counter-
intuitive,it is recognized that unlike the Dickson multiplier
topology,the DDCHB or DDCFB conducts with the transistors
mainly operating in their triode regions (refer to Section 3.2),
where the V
ds
is significantly lower than V
th
.In this sense,the
rectifier performance is less affected by V
th
.Since maximum PCE
would require V
out
bias to be just slightly above V
th
,this leads to a
low forward conduction current that accentuates the effect of
subthreshold current.Fortunately,a higher V
sb
now suppresses
both the subthreshold and reverse leakage currents (see (11)
and (13)),resulting in a possible improvement in PCE.Never-
theless,only a little improvement could be expected in this case,
because the subthreshold current is much less significant com-
pared to the currents in other operation regions.
The fact that increasing V
th
will not necessarily degrade the
PCE can be utilized to our design advantage.For instance,we
can match the required load voltage to the optimal rectifier
voltage by controlling the source-to-bulk bias.Section 3.1 shows
a multi-stage rectifier circuit where the source-to-bulk of PMOS
transistor can be independently biased.For instance,assuming
the required load voltage is 0.33 V while the optimal rectifier
voltage V
out
is 0.29 V,the latter can be shifted to the desired
0.33 V by raising the PMOS transistor’s source-to-bulk voltage in
that particular stage.
4.3.Effects of finite gate and substrate resistance
To account for effects of the finite gate and substrate resistance
which are ignored in the above analysis,we simulated a single-
stage rectifier circuit with 915 MHz input sources using Cadence
Spectre tools.Results show the maximum PCE turns out to be
72.4% and 74.3% for V
sbn
¼0 and 0.66 V,respectively,compared to
74.6% and 78.8% (without consideration of the above effects) as
shown in Figs.10 and 11.This slight difference in PCE due to the
loss resistance allows us to combine the DC results obtained so far
with a simple linear loss model for covering both AC and DC
effects with reasonable accuracy,as will be discussed in the
section that follows.
5.Piece-wise linear model
This section describes a piece-wise linear approximation
model for the rectifier.This model is useful for development of
our matching theory as well as consideration of design tradeoffs,
which are to be discussed in the next few sections.
Fig.10.PCE contour for V
sbp
¼0,V
sbn
¼0 and
d
¼0.82 (maximum PCE of 74.6%
occurs at V
out
¼0.28 V and g
2
¼0.5).
Fig.11.PCE contour for V
sbp
¼0,V
sbn
¼0.66 V and
d
¼0.82 (maximumPCE of 78.8%
occurs at V
out
¼0.3 V and g
2
¼1.2).
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255248
As it can be seen fromFigs.9 and 11,when the PCE reaches its
peak value with V
out
Z9V
thp
9,the transistors operate in triode
mode and behave in a nearly linear fashion.Therefore,they can be
modeled as a linear fixed-value resistor.Fig.12 shows such a
model for the DDCFB,where the transistors are modeled by a
resistor connected to a switch that turns on when V
in
Z9V
thp
9.The
average current (I
o
) for a sinusoidal input V
in
¼V sin
y
is calculated as
I
o
¼
1
2
p
Z
p
sin
1
w
d
sin
1
w
d
Vsin
y
V
out
R
d
y
¼
V
2
p
R
2
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1ð
w
d
Þ
2
q

d
p
þ2
d
sin
1
ð
w
d
Þ
 
ð18Þ
where R is the fixed-value resistor and
w
¼9V
thp
9/V
out
.The transistors
can be sized in such a way that the model gives the same I
o
as the
real circuit would.Figs.13 and 14 compare the fixed-resistor model
with actual simulation results (in terms of current and power loss,
respectively) when the circuit is subject to a full cycle of sinusoidal
input signal (V
in
).It can be seen fromthe figures that there is about
10% difference in peak current value.The average power is calcu-
lated by integrating the main envelope of Fig.14 for the forward
region,and the side envelopes for the reverse region.The power
discrepancy between models was found to be 3% and 69%,respec-
tively.To account for the error in power loss in the reverse region,a
shunt resistor (known as ‘‘loss element’’) is introduced (as shown in
Fig.12),which can be sized to offset the above discrepancy.If the
resistance of this loss element is denoted by R
loss
,the PCE can be
obtained by substituting (18) into (15) as
PCE
ðfixedresÞ
¼
d
2
ð2=
d
Þ
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1ð
w
d
Þ
2
q

p
þ2sin
1
ð
w
d
Þ
ð
p
=2Þsin
1
ð
w
d
Þþ
d
ð
w
2Þ
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1ð
w
d
Þ
2
q
þð
p
R=R
loss
Þ
ð19Þ
Since the fixed-resistor model represents a circuit that
switches between two perfectly linear regions,it is hence named
‘‘piece-wise linear model’’.Fig.15 shows a comparison of PCE (for
915 MHz) from the piece-wise linear model and the actual
Cadence Spectre simulation for a single-stage rectifier design
example.It should be noticed that the factor
p
R/R
loss
in (19)
causes the downward bending of the modeled curve in Fig.15.
To increase the peak value of PCE,we need to either decrease R or
increase R
loss
.As mentioned in Section 3,increasing V
out
forces the
transistors to work in the triode region,leading to an increase in I
o
or,equivalently,a decrease in R.However,if V
out
is increased too
much,the reverse conduction current will go up as well,which
results in a decrease in R
loss
.Therefore,a more practical way to
improve the peak value of PCE is to keep V
out
slightly above 9V
thp
9
V
in
V
out
R
I
o
Loss Element
I
loss
I
in
On when V
in
≥V
thp
AC
Fig.12.A fixed-resistor model for the half-bridge rectifier.
Fig.13.Current waveform for fixed-resistor model (dotted line) vs.actual
simulation (solid line).
Fig.14.Power waveform for fixed-resistor model (dotted line) vs.actual simula-
tion (solid line).
Fig.15.Simulated PCE vs.modeled PCE.
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255 249
and,at the same time,reduce the reverse leakage current by
increasing the source-to-bulk bias (equivalent to increasing R
loss
).
The fact that the modeled curve traces the simulated curve
closely until the maximum PCE of 73.3% means that this simple
model can be used in the real circuit for both low and high PCE
analysis.In Fig.15,the value of
d
at the point of maximumPCE is
marked as
d
max
.As the value of
d
goes beyond
d
max
,the modeled
PCE deviates fromthe simulated PCE.This is because at high value
of
d
,the reverse current (see Section 3.2) becomes increasingly
dominant with the highly non-linear nature which cannot be
modeled accurately by a linear resistor.Fortunately,our goal is to
achieve the maximumPCE for which the effect of non-linearity is
not yet dominant.Thus,the proposed piece-wise linear model is
sufficient for our analysis.Our assumption in Section 4.1 that PCE
is strongly related to
d
is also confirmed by Fig.15 which shows
that
d
indeed follows the PCE closely.
6.Matching of rectifier to antenna
For the DDCHB or DDCFB rectifier,PCE peaks only at a specific
combination of g
2
,
d
and V
out
values.If the input of the rectifier is
modeled by a traditional linear impedance model for impedance
matching without considering the above combination,it could
lead to an inferior PCE.Conversely,if the combination of g
2
,
d
and
V
out
is met without satisfying the impedance requirement,the
power transfer would not be maximized.Therefore,a natural
question to ask is whether both power transfer to the load (or PU)
and the PCE can be optimized at the same time.This section
discusses the matching problem based on the above piece-wise
linear model.
6.1.Piece-wise linear model for matching
Consider the matching problem in an antenna-coupled recti-
fier circuit with the proposed piece-wise linear model,as shown
in Fig.16 where R
r
is the equivalent radiative resistance fromthe
antenna and U
0
is the amplitude of the sinusoidal source with
y
¼
o
t.If we assume
k ¼ 1þ
R
r
R
loss
 
V
out
U
0
ð20Þ
s
¼
RðR
r
þR
loss
Þ
R
r
R
loss
ð21Þ
the power at the load (with the output voltage V
out
) can be
expressed as
P
L
¼
1
2
p
Z
p
sin
1
ð
w

sin
1
ð
w

V
out
U
0
sin
y
V
out
R
r
==R
loss
þR
d
y
¼
U
2
0
8R
r
R
loss
R
loss
þR
r
 
8k
ð1þ
s
Þ
p
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1ð
w

2
q
þksin
1
ð
w
kÞ
k
p
2
 
ð22Þ
Since the term U
o
2
/8R
r
in (22) is the available power (P
A
) from
the antenna,R
r
can be written from (3) as
R
r
¼
2
P
EIRP
G
p
rU
0
l
 
2
ð23Þ
where
l
and P
EIRP
are typically a constant and,for our particular
case with 915 MHz band,equal to 327.87 mm and 4 W,respec-
tively,G¼1.64 for a simple dipole antenna,and the value of r is
set by the operating range,leaving U
0
as an only unknown
variable.Table 1 shows a list of P
A
for different values of r.
6.2.Power utilization
At the beginning of a design cycle,design specifications
typically include the range requirement (or estimated P
A
from
Table 1) and load requirement in terms of voltage and current.
What is unknown is how much of the available power can
actually be delivered to the load,which is defined as the power
utilization (PU) as shown in (2).Dividing (22) by P
A
results in the
following expression of PU for a half-bridge rectifier:
PU
half
¼
R
loss
R
loss
þR
r
 
8k
ð1þ
s
Þ
p
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1ð
w

2
q
þksin
1
ð
w
kÞ
k
p
2
 
ð24Þ
Since a full bridge consists of two identical half-bridge circuits
in parallel,the PU for a full bridge (PU
full
) is simply
PU
full
¼2 PU
half
ð25Þ
To find the maximum value of PU,let @PU
half
=@k ¼0.This
leads to
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1ð
w

2
q
þ2ksin
1
ð
w
kÞk
p
þð1
w
Þ
w
k
2
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1ð
w

2
q
¼0 ð26Þ
The solution of (26) for k is denoted by k
max
.For the special
case of
w
¼1,k
max
is found to be 0.3942.The maximum PU also
depends on the value of
s
.For
s
¼0 in particular,the PU maxima
for the full-bridge and half-bridge rectifiers are 0.9226 and
0.4613,respectively.This implies that even with a lossless
rectifier,the power that can be extracted would be no more than
92% of the available power since generally 0o
s
.
6.3.Transistor sizing for optimal power transfer
According to (21),the accurate value of
s
is unknown since the
values of R,R
r
and R
loss
are not available.However,an estimate of
s
can still be obtained by the following method.As is shown in
Section 4.1,
d
¼V
out
/V,where V is the voltage amplitude across R
and V
out
in Fig.16.For a narrow band antenna and matching
network,V is approximately sinusoidal.In Fig.16,the peak
current through R can be expressed in terms of V or in terms of
d
max
and V
out
,where
d
max
is the value of
d
that maximizes the PCE
(refer to Fig.15).By using (20) and (21),the best resistance ratio
s
,defined as
s
match
,can be estimated as
s
match

k
max
ð1
d
max
Þ
d
max
k
max
ð27Þ
AC
U
0
sin (￿t)
U
0
sin (￿t)
R
r
R
loss
R
V
out
AC
R
r
//R
loss
R
V
ou
t
R
r
+ R
loss
R
loss

Fig.16.Model of an antenna-coupled rectifier circuit (a) and its equivalent
circuit (b).
Table 1
Available power (P
A
) at various distances for P
EIRP
¼4 W.
Distance r (m) Available power P
A
(
m
W)
1.76 1450
3 496
5 178
10 44
20 11
30 5
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255250
where k
max
is the value of k that maximize the PU.Since R
loss
is
due to transistors’ leakage and AC parasitic loss,and is typically
much larger than R
r
,the estimated value of P
A
and hence
maximum operating range r can be found from (2),(24) and
(25) for a given P
L
by substituting (27) into (25).Alternatively,one
can find the estimated value of P
L
if P
A
is given as an initial design
parameter.Either way,the value of R can be found from(16) and
(18) with given values of
d
max
,V
out
,I
o
and
w
.
It has been shown in Section 4.1 that the global maximum
value of PCE is independent of transistor size scaling as long as
d
,
V
out
and g
2
are constants.Our goal is then to maintain
d
max
at an
available power level of P
A
.The value of R
loss
can be found by
substituting R and the PCE into (19).Thus,the transistors in a
basic cell of rectifier (see Fig.3) can be scaled linearly for the
output current I
o
while keeping g
2
constant.This can be done
through simulation with Cadence Spectre tools.Assuming that all
transistors have the same channel length,it becomes clear that
the maximum PU will be obtained only with transistors of
particular sizes for a designed level of P
A
.In other words,for
any given target operating range,an optimal transistor size exists
for maximum power transfer.
6.4.Coupling capacitors and parasitic gate capacitances
As is shown in Section 3.1,for a multi-stage DDCFB rectifier,
the DC bias generated by the stage cascading requires the use of
coupling capacitors (C
c
) in all stages (except the first stage) for DC
blocking.These capacitors represent a capacitive divider with
parasitic gate capacitances (C
p
) of transistors,as shown in Fig.17
where V
in(eff)
is introduced as an effective input voltage to the
bridge rectifier.The amplitude of the voltage across R and V
out
in
Fig.17,denoted by V
r
,can be determined (without proof) as
follows,regardless of R and V
out
:
V
r
V
inðeff Þ
C
c
C
c
þ2C
p
ð28Þ
This is because the charge loss due to I
o
through the capacitor
network in one half-cycle will be compensated by the charge gain
in the next.If V
in(eff)
is viewed as the output from the matching
circuit,then an equivalent rectifier circuit can be obtained with
some effective parameters,as shown in Fig.18 where C
p(eff)
,
V
out(eff)
and R
eff
are given by
C
pðeff Þ
¼
C
c
C
c
þ2C
p
 
C
p
ð29Þ
V
outðeff Þ
¼ 1þ
2C
p
C
c
 
V
out
ð30Þ
R
eff
¼ 1þ
2C
p
C
c
 
R ð31Þ
and the value of C
p
is estimated by multiplying a constant to
the total width of all transistors,depending on the technology
process.For the CMOS 90 nm process under our consideration,
this constant is 0.5932 fF/
m
m.The value of R
loss(eff)
in Fig.18 can
be obtained by scaling R
loss
.However,since R
loss(eff)
is generally
very large,its impact on matching is negligible.The matching
network in Fig.18 will be briefly discussed later in Section 6.6.
6.5.Determining the equivalent radiative resistance
In order to determine the equivalent radiative resistance (R
r
),
one can find U
0
by substituting (30) and k
max
into (20) (again with
the assumption of R
r
/R
loss
E0 since R
loss
bR
r
).The value of U
0
is then
substituted into (23) to obtain R
r
.Further substituting the value of
R
r
into (21) gives the value of
s
,which may not match
s
match
due to
the narrow-band approximation in deriving (27).In general,the
above procedure needs to be done iteratively until the value of
s
converges.However,as will be seen in Sections 8 and 9,a single
iteration is usually satisfactory with reasonably good results.
6.6.Matching with an L-match network
Typically,the value of R
r
as determined above is much larger
than the low impedance of a simple antenna (73
O
for a simple
dipole antenna).This allows us to use an L-match network,as
shown in Fig.18 where Q
L
is the quality factor for the L-match.The
inductor L
compensate
in the network is required because our PU
analysis assumes no reactive current.The reactive impedance due
to C
p(eff)
can be canceled by an appropriately sized inductor.Real
inductors and capacitors contain parasitic loss elements,the effect
of which can be easily estimated by adjusting R
loss(eff)
in Fig.18.
7.Design tradeoffs
This section looks at the relationship among the rectifier’s
bandwidth,operating range and technology process.
7.1.Bandwidth for an optimal rectifier
Bandwidth is an important attribute for the rectifier in mobile
tags that are situated in a noisy automotive environment,and
should be considered based on both the matching network and
antenna system.Since antenna design varies drastically with
different performance characteristics and is beyond the scope of
our discussion,this work shall only address the matching network
and its effects on bandwidth.
It can be seen in Fig.18 that the bandwidth (B) depends on both
Q
L
of the L-match and the quality factor (Q
C
) of the reactance
compensation network.However,since most of the power is
delivered to the load when the rectifier turns on,the Q
C
due to R
eff
is a very small number (typically less than one) because of the small
value of R
eff
.As a result,the bandwidth characteristic is mainly
determined by the relatively large Q
L
.By using (20),(23),(30) as
AC
½C
c
C
p
R
V
out
AC
R
V
ou
t
½C
c
+ C
p
C
c
C
c
2C
p
+
V
in (eff)
V
in (eff)
Fig.17.A capacitive divider with parasitic gate capacitances.
AC
C
p(eff )
L
compensate
73Ω
L
LS
C
LP
R
loss(eff )
R
eff
V
out(eff )
Equivalent Rectifier
Matching Network
1
73
−=
r
L
R
Q
Fig.18.An equivalent rectifier with L-match network to a dipole antenna.
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255 251
well as the value of Q
L
given in Fig.18,the expression for the
bandwidth (B) can be approximately written as
B 
1
r
k
max
c
p
ð1þð2C
p
=C
c
ÞÞV
out
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
R
a
P
EIRP
G
2
r
ð32Þ
where R
a
and c represent the radiative resistance of the physical
antenna and the speed of light,respectively.
7.2.Tradeoffs for the rectifier design
It is interesting to see from (32) that the bandwidth B of the
rectifier is independent of the operating frequency.A general
observation is that B is inversely proportional to the designed
operating range (r) and the rectifier’s output voltage (V
out
).For
instance,the rectifier designed in 0.18 or 0.35
m
m CMOS process
for the same operating range will have a narrower bandwidth
than that of the 90 nm process which has a lower threshold
voltage.
8.Multi-stage rectifier design
This section details two multi-stage rectifier designs based on
differential-drive CMOS full-wave bridge topology with CMOS
90 nm technology,and addresses other issues that arise.
8.1.Optimum number of stages
It has been shown that an optimal PCE only occurs at a
particular value of V
out
that is slightly higher than 9V
thp
9.For
CMOS 90 nmprocess,9V
thp
9 is around 300 mV.Since circuits on an
RFID tag typically require a power supply of 1 V to operate,there
is a need for multiple stages.Also,Section 6 shows that the
maximum power transfer will occur only when the ratio of U
0
(i.e.,effective antenna voltage) and V
out(eff)
is approximately equal
to k
max
.A simple strategy to ensure this is to have all stages
operating at roughly the same V
out
.Thus,the optimal number of
stages (N
opt
) can be expressed as
N
opt
¼
desired total output voltage
9V
thp

D
ð33Þ
where
D
is an additional offset to ensure that V
out
of individual
stages operate above 9V
thp
9 in order to achieve the maximumPCE.
The value of
D
can be obtained fromempirical observation of the
PCE contour (see Section 4),and it ranges from 0.01 to 0.03 V.
Assuming
D
¼0.02 V,V
sb
¼0 and 9V
thp
9¼0.2785 V (for ST 90 nm
process),(33) gives the value of 3.35.One can round this value to
3 for a three-stage design by setting the sumof 9V
thp
9 and
D
to be
0.33 V per stage.This can be done by modifying the body bias of
the PMOS transistors based on the threshold voltage at different
body bias voltages,as shown in Table 2.
If each stage is set to V
out
of 0.33 V,we can connect the output
of the second stage (0.66 V) to the P-type bulk of the first stage.
Likewise,the final stage’s output at 0.99 V can be used to set the
bulk voltage of the second stage.If this is done,the 9V
thp
9 for first
two stages becomes 0.3117 V.While the V
sb
for the final stage
remains at zero,the V
sb
for the N-type of the same stage will be
biased to 0.66 V,forcing the V
thn
to be higher than 9V
thp
9 at a value
of 0.2806 V.Therefore,the bridge circuit will turn on at V
thn
(instead of 9V
thp
9) which,however,is still lower than 0.33 V when
compared to other stages,and the optimal PCE may not be
reached.Fortunately,as can be seen from the PCE contour in
Section 4,the region around the optimal PCE is rather flat,which
means that the resulting PCE would be very close to its optimum.
After the optimum number of stages is determined,the tran-
sistors in each stage should be sized using the procedure from
Section 6.3 such that the average output current at V
out
remains the
same for all stages.This would require various transistor sizes for
different stages,as opposed to the same transistor sizes used by
other existing design methods.
8.2.Sizing for coupling capacitors
Different transistor sizes result in different size of C
p
at each
stage (refer to Section 6.4).Strictly speaking,the C
c
also needs to
be sized accordingly to ensure that V
out(eff)
also stays the same
throughout the rectifier for optimal PCE (refer to (30)).In practice,
however,keeping the same C
c
would be quite acceptable,again
due to the flat region around the optimal point on the PCE
contour.From (32),the size of the C
c
also affects the bandwidth
of the rectifier.It should be noticed that as C
c
becomes much
larger than C
p
,any further increase in C
c
provides little or no
improvement in the bandwidth.
8.3.Equivalent resistances with multi-stage rectifier
For the multiple-stage rectifier where individual resistances at
each stage are almost the same and are connected in parallel,its
overall effective resistances would be lower than the single-stage
counterpart.More specifically,the R
eff
or R
loss(eff)
as described in
Section 6.4 for the single-stage rectifier should be divided by N
opt
given in (33) for the case of multiple-stage design.
8.4.Other parasitic parameters
Significant amount of parasitic loss comes fromthe finite gate
resistance and substrate resistance of transistors.These resis-
tances can be modeled by finding the quality factor of the gate
capacitance to be lumped with the equivalent loss resistance
R
loss(eff)
.Practically,the negative effect of the gate resistance can
be reduced to a negligible level by introducing a sufficient
number of gate fingers.Another point of caution is the selection
of driving plate for the coupling capacitor C
c
.Let us first consider
the top plate driving method where the input signal is connected
to the top plate of C
c
,as shown in Fig.19 where C
a
represents the
bottom plate coupling to the substrate.In this case,C
a
’s are
directly across C
p
,which reduces V
r
according to (28).This is not
desirable as an increased Q
L
is required for compensating the
voltage loss with the reduced bandwidth.Fig.20 shows another
case where the bottom plate is driven instead.In this case,no
negative side-effects are present because the C
a
’s are in parallel
with the source.For both cases of Figs.19 and 20,however,the
substrate loss would decrease the PCE of the rectifier circuit.Since
the value of C
a
is proportional to the size of C
c
,small C
c
or
capacitors with low C
a
should be used.The MIM-type capacitor
supported by ST 90 nm technology is ideal for this purpose as it
uses a lot less area than regular capacitors for obtaining the same
capacitance.
Table 2
V
th
at different body bias voltages with ST 90 nm process.
V
sb
(V) V
thn
(V) 9V
thp
9 (V)
0 0.2237 0.2785
0.2 0.2434 0.2991
0.3 0.2523 0.3088
0.33 0.2549 0.3117
0.36 0.2574 0.3145
0.6 0.2763 0.3364
0.66 0.2806 0.3417
0.72 0.2849 0.3469
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255252
8.5.Rectifier optimized for 10-m range (RF10)
Two three-stage rectifiers were designed for different range
and bandwidth requirements.The matching network’s compo-
nents as well as the antenna are assumed to be external while
transistors,coupling capacitors and output capacitors are inte-
grated on individual ICs with ST CMOS 90 nm technology.An
output voltage of 0.99 and 0.33 V is assumed for the overall
rectifier and each stage,respectively.The first rectifier was
designed for the optimized power transfer to the load at 10 m.
This design is labeled ‘‘RF10’’ whose target performance is shown
in Table 3.Table 4 provides piece-wise model and other design
parameters for the matching network used in RF10.
It can be seen fromTable 4 that our piece-wise linear matching
model produces the effective radiative resistance (R
r
) that is
almost seven times as much as the effective on-resistance of the
switch (R
eff
).This is quite different fromthe traditional concept of
matching which suggests an equal value for these two resistances.
Transistor parameters and other component values for RF10 are
shown in Tables 5 and 6,respectively,where p_fingers and
n_fingers are the number of fingers used in P- and N-type gate
contacts,and C
output
is the output capacitor at individual stages.
The channel length of all transistors is assumed to be 0.1
m
m.
8.6.Rectifier optimized for 22-m range (RF22)
The second rectifier labeled ‘‘RF22’’ was designed for the opti-
mized power transfer to the load at 22 m.Transistor parameters as
well as component values for the design are given in Tables 7 and 8,
respectively.
9.Simulation results for three-stage rectifiers
We simulated three-stage rectifiers for both RF10 and RF22
with Cadence Spectre tools using parameters from Tables 5 to 8.
Results for the RF10 design are summarized in Tables 9 and 10.It
can be seen fromTable 9 that the PCE reaches its maximumvalue
of 74%,and the obtained PU is 72%.The output current at 10 m
distance is 32.45
m
A,which is potentially 80 times better than the
silicon implementation result of [6] under comparable conditions.
Both PU and PCE are higher than the simulated results of [3],
C
p
C
c
C
c
C
￿
C
￿
AC
Top Plate
Top Plate
Substrate Loss
Fig.19.Input signal driving the top plate of C
c.
.
C
p
C
c
C
c
C
￿
C
￿
AC
Bottom Plate
Substrate Loss
Fig.20.Input signal driving the bottom plate of C
c.
.
Table 3
Design performance for RF10 at 10 m.
P
A
44.59
m
W
Target P
L
33.14
m
W
Designed PU 74.3%
Target I
o
33.48
m
A
PCE (1st stage) 73.33% at g
2
¼0.6
PCE (2nd stage) 74.15% at g
2
¼0.8
PCE (3rd stage) 74.1% at g
2
¼1.4
Table 4
Model and matching parameters for RF10.
C
p(eff)
163.87 fF
R
eff
341.57
O
R
r
2382.41
O
Q
L
5.62
B 162.68 MHz
d
max
0.77
k
max
0.39
Table 5
Transistor parameters for RF10.
Stage 1 Stage 2 Stage 3
W
p
(
m
m) 40.2 40.87 31.35
p_fingers 120 122 95
W
n
(
m
m) 9.9 12.92 16.75
n_fingers 30 38 50
Table 6
Other component values for RF10 (refer to Figs.1 and 16).
Component Value
L
L
(nH) 71.42
C
L
(pF) 0.410
L
compensate
(nH) 184.63
C
c
(pF) 1.2
C
output
(pF) 1.2
Table 7
Transistor parameters for RF22.
Stage 1 Stage 2 Stage 3
W
p
(
m
m) 8.84 9.1 7
p_fingers 26 26 20
W
n
(
m
m) 2.19 2.88 3.75
n_fingers 6 8 10
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255 253
which compare well with the silicon measurements of the same
study.In terms of ‘‘power-up threshold’’ which is defined as the
minimum P
A
for an output power of 2
m
W [3],our simulation
shows that the proposed design can potentially operate as far as
19 m or at the P
A
level of 19.1 dBm with the output current
of 2.3
m
A.
Results for the RF22 design are shown in Tables 11 and 12,
where the PCE is at its maximumvalue of 74%,and the PU is 73%.
The output power in this case is 6.76
m
A0.99 V¼6.7
m
W,which
is potentially more than 3 times better than the silicon imple-
mentation result of [3] under comparable conditions.In terms of
power-up threshold,RF22 can operate at 24.14 dBm or an
equivalent distance of 34 m,which is potentially 55% better than
that of [3].It is evident that the simulated bandwidth generally
matches the estimation from (32).Since each of the circuits
simulated is optimized for only one distance (i.e.,22 m),the PU
drops when the distance is shorter than the designed values.
However,as can be seen from Tables 9 and 11,the resulting
rectifier designs can still provide sufficient output currents.
10.Conclusions
We have presented a new approach for analysis,design and
optimization of CMOS differential-drive full-wave bridge rectifier
circuits.It has been shown that maximum power conversion
efficiency (PCE) of the rectifier occurs only when a particular
value of output voltage,input-to-output voltage ratio,and tran-
sistor sizes are chosen.The method of transistor scaling has been
discussed for different load current requirements without affect-
ing PCE.It has also been demonstrated that the increased bulk
biasing level would not necessarily degrade PCE.Instead,this
body effect has been strategically utilized to improve the PCE of
multi-stage rectifiers.
To address the non-linear nature of matching problem for
rectifiers operating at high PCE,which has not been investigated
in prior work,we have proposed a piece-wise linear model of the
rectifier that allows us to formulate the matching problem.It has
been shown that maximum power transfer does not occur when
the rectifier’s impedance is matched to the source in a traditional
sense.It has also been found that when driven by a sinusoidal
source,the rectifier under investigation can transfer no more than
92% of available power from the antenna to the load,even under
ideal conditions.
To validate the proposed design theory,two three-stage
rectifier circuits,one of which is optimized for 10 m and the
other optimized for 22 m,have been designed for the operating
frequency of 915 MHz with different transistor sizes and P-type
bulk connections for different stages.For the case of 10 m,
simulation results have revealed an improvement in output
current (32.45
m
A) that is potentially 80 times that of the silicon
test results of [6] under similar conditions.The rectifier designed
for 22 m distance,its power utilization (PU) exceeds that of the
simulated results of [3] by at least three times while providing
55% improvement in power-up threshold.Since the silicon mea-
surements of [3] match the simulated counterparts,it is reason-
able to expect similar performance improvement in actual silicon
implementation.At the designed operating range,the output
current of two rectifier circuits differs by 5 times while main-
taining the same PCE.This confirms the validity of the proposed
scaling method for PCE-invariant design.It has also been shown
that our method results in a high PCE that does not degrade with
body effect.This is evident in our three-stage rectifiers which
operate with the PCE of 74%,the highest simulated value ever
reported at the designed distance,especially for multi-stage
rectifiers,regardless of transistor’s source-to-bulk bias level.The
proposed rectifier circuits have also been simulated for different
distances ranging from a very short distance (o1 m) to 19 and
34 m without any observable intermediate dead-zone.
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L
(nH) 147.74
C
L
(pF) 0.203
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compensate
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C
c
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Shu-Yi Wong (M’93) received the B.A.Sc.degree in
electrical engineering fromthe University of Waterloo,
Ontario,Canada,in 1994.Since then,he had worked in
different companies as a communication firmware
designer,mix-signal analog/digital designer and chief
design engineer.In 2008,he left his job at Tyco Safety
Products Canada,Ltd.and joined the University of
Windsor,Ontario,where he received his M.A.Sc.
degree in 2009.He is currently pursuing the Ph.D.
degree at the Department of Electrical and Computer
Engineering,the University of Toronto,Ontario,
Canada.His research interest is in the area of low
power design methodologies.
Chunhong Chen (M’99-SM’04) received the B.S.and
M.S.degrees from Tianjin University,China,in 1983
and 1986,respectively,and Ph.D.degree from Fudan
University,China,in 1997,all in electrical engineering.
From September 1997 to August 1998,he was a
Research Associate at the Hong Kong University of
Science and Technology.From December 1998 to
August 2000,he was a Postdoctoral Fellow at North-
western University,Evanston,IL.Since 2001,he has
been with the Department of Electrical and Computer
Engineering at University of Windsor,Ontario,Canada,
where he is presently a professor.His research inter-
ests include timing analysis and power optimization
for integrated circuits and systems,and more recently reliability and timing issues
with single-electron devices and circuits.
S.-Y.Wong,C.Chen/INTEGRATION,the VLSI journal 44 (2011) 242–255 255