VLSI Fabrication Technology

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Nov 26, 2013 (3 years and 8 months ago)

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1

VLSI Fabrication Technology

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

2

Copyright


2004 by Oxford University Press, Inc.

Figure A.1
Silicon ingot and wafer slices.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

3

Copyright


2004 by Oxford University Press, Inc.

Figure A.2 (a)

An 8
-
pin plastic dual
-
in
-
line IC package,
(b)

A 16
-
pin surface mount package.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

4

Copyright


2004 by Oxford University Press, Inc.

Figure A.3
A typical
n
-
well CMOS process flow.

(a) Define
n
-
well diffusion

(mask #1)

(b) Define active regions

(mask #2)

(e)
n
+

diffusion

(mask #4)

(f)
p
+

diffusion

(mask #5)

(c) LOCOS oxidation

(g) Contact holes

(mask #6)

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

5

Copyright


2004 by Oxford University Press, Inc.

Figure A.3
(Continued)

(d) Polysilicon gate

(mask #3)

(h) Metallization

(mask #7)

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

6

Copyright


2004 by Oxford University Press, Inc.

Figure A.4
Cross
-
sectional diagram of an
n
-

and
p
-
MOSFET.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

7

Copyright


2004 by Oxford University Press, Inc.

Figure A.5
Cross sections of resistors of various types available from a typical
n
-
well CMOS process.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

8

Copyright


2004 by Oxford University Press, Inc.

Figure A.6
Interpoly and MOS capacitors in an
n
-
well CMOS process.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

9

Copyright


2004 by Oxford University Press, Inc.

Figure A.7
A
pn

junction diode in an
n
-
well CMOS process.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

10

Copyright


2004 by Oxford University Press, Inc.

Figure A.8
Cross
-
sectional diagram of a BiCMOS process.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

11

Copyright


2004 by Oxford University Press, Inc.

Figure A.9
A lateral
pnp

transistor.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

12

Copyright


2004 by Oxford University Press, Inc.

Figure A.10
p
-
Base and pinched
p
-
base resistors.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

13

Copyright


2004 by Oxford University Press, Inc.

Figure A.11
Cross
-
sectional diagram of a symmetrical self
-
aligned
npn

SiGe heterojunction bipolar transistor (HBT).

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

14

Copyright


2004 by Oxford University Press, Inc.

Figure A.12
A CMOS inverter schematic and its layout.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

15

Copyright


2004 by Oxford University Press, Inc.

Figure A.13
Cross section along the plane AA


of a CMOS inverter.

Microelectronic Circuits
-

Fifth Edition Sedra/Smith

16

Copyright


2004 by Oxford University Press, Inc.

Figure A.14
A set of photomasks for the
n
-
well CMOS inverter. Note that each layer requires a separate plate:
(a)
,
(d)
,
(e)
, and
(f)

dark
-
field masks;
(b)
,
(c)
, and
(g)

clear
-
field masks.